JPH0358434A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable a high output semiconductor device having excellent low noise characteristics capable of high speed operation to be manufactured by a method wherein a metallic thin film is formed on a semiconductor layer between a source electrode and a gate electrode as well as between a drain electrode and the gate electrode. CONSTITUTION:A very thin metallic film 5 is provided on the surface of a semiconductor layer between a source electrode 7 and a gate electrode 9 as well as between a drain electrode 8 and the gate electrode 9 so as to lower the level of the band bending on the surface. Accordingly, two-dimensional electron gas 11 will not be modulated by the surface depletion layer 12 between the source electrode 7 and the gate electrode 9 as well as between the drain electrode 8 and the gate electrode 9 so that the two-dimensional electron gas concentration almost three times of that of the conventional high electron mobility transistor(HEMT) may be attained so as to lower the source resistance. Through these procedures, the source resistance can be lowered without increasing the capacitance between source and gate thereby enabling a high output semiconductor device having excellent low noise characteristics capable of high-speed operation to be manufactured.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a high-power semiconductor device with excellent low-noise characteristics, and particularly to a low-noise and high-power semiconductor device using a compound semiconductor such as GaAs or InGaAs. related to Schottky gate field effect transistors (MESFETs) and high electron mobility transistors (Hll!MT).

(Prior art) Generally. While silicon (Si) is an indirect transition type semiconductor, many compound semiconductors are direct transition type semiconductors, and are characterized by high carrier mobility. As a high-speed/high-frequency semiconductor device that takes advantage of this feature, for example, MESF using GaAs! GaAs Mt!, for which ET is already in practical use! SFt! The characteristic of T is that it can operate at 10GHz, which is the limit of conventional St bipolar transistors.
It is possible to amplify at frequencies exceeding Furthermore, in multi-component compound semiconductors, various semiconductor mixed crystals can be artificially created by changing the m ratio, so it is possible to form a heterojunction that can achieve lattice matching between different semiconductor mixed crystals. HE? using such a heterojunction and using modulation doping?
Ultra high speed semiconductor devices for IT etc. Various optoelectronic devices, including light emitting diodes and semiconductor lasers, as well as new devices using superlattice structures, are being developed.

Among them, A IGaAs / GaAs II E
In recent years, MT has attracted attention as a low-noise and high-output semiconductor device, and its applications are rapidly expanding. The most common structure of such AIGaAs/GaAa-based 1{EMT is shown in FIG. In this figure, an undoped GaAs layer 2, an undoped AIGaAs spacer layer 3, and an n''-AIG
The aAs layers 4 are sequentially stacked. n”-A, which is the electron supply layer
On the IGaAs layer 4 are a source electrode 7 and a drain electrode 8.
, and a gate electrode 9 are provided. Undove A
IGaAs spacer layer 3 and n”-AIGaAs layer 4
A surface depletion skin l2 is formed by surface states. Series resistance between source and gate, i.e. source resistance 1? ．．
This causes an increase in RE of such a planar structure
In contrast to the FIT, an Ht!MT having a recessed structure in which a thick n''-GaAs cap layer 17 of about 2,000 layers is provided as shown in FIG. 3 has been proposed.

The recessed structure is created by recessing only the channel region directly under the gate electrode 9. By making the region other than the channel thicker than the surface depletion layer l2, the source resistance R. The aim is to reduce the

(Problems to be Solved by the Invention) In general, the cutoff frequency ft, which is an index of high-speed operation of a 2 transistor, is expressed by the following equation (1).

b=c. /2πc,. Q) Here, +Glj is the transistor's intrinsic mutual conductance, and +C91m is the source-gate capacitance. ``To achieve high-speed operation of transistors by increasing , G.
It is necessary to increase C,i and/or decrease C,i. In recent years, it has been used as a method to increase Ga.
For example, in Figure 2, the electron supply layer n・-AIG
It has been proposed to increase the impurity concentration in the aAs layer 4 or to planarly dope the impurity.
On the other hand, in order to reduce C,1. The gate length is being shortened.

In addition, the minimum noise figure NF, which is an index of the low noise characteristics of a transistor, is also used. i is expressed by the following equation (2).

(Left below) ? Here, κf is the fitting parameter, ``is the operating frequency + RI is the source resistance + R9 is the gate resistance + GI6
and Cps are as defined above, NF■. In order to improve the low noise characteristics of the transistor, G. an increase in and/or C. It is necessary to reduce the resistance R3 and R, and it is also effective to reduce the resistance R3 and R to some extent.

The lit! structure as shown in Figure 2! In MT, since the 1''-AIGaAs layer 4, which is the electron supply layer, is very thin, usually about 400λ, there is a
The dimensional electron gas l1 is modulated by the surface depletion layer l2,
The two-dimensional electron gas concentration is 3 to 5 x 10 cm-, which is about 1/3 of that when the n''-AIGaAs layer 4 is sufficiently thick. Because it relies only on electronic gas 11,
Source resistance R1 increases. On the other hand, in a HEMT with a deep recess structure as shown in FIG. 3, the source resistance R. It is possible to reduce However, as shown in Figure 4, n ”
- A surface depletion layer 12 is formed in the GaAs cap layer 17 due to surface states. A depletion layer 18 directly under the gate due to a Schottky barrier is formed in the n-AIGaAs layer 4, so that the gate electrode 9 and . The capacitance (gate fringe capacitance Ct) between the n''-GaAs cap layer 17 and the n''-AIGaAs layer 4 near the gate electrode increases. Figure 5 is.
Gate length Lg when gate width is 200μ
The relationship between Cwt and the source-gate capacitance Cwt is shown. As is clear from this figure. If a large gate fringe capacitance Ct exists, even if Lg is shortened to the submicron level, C, . is not effectively reduced. The present invention solves the above-mentioned conventional problems, and its purpose is to reduce the source resistance deviation without increasing the source-gate capacitance C,3, thereby achieving low noise characteristics. The object of the present invention is to provide a high-output semiconductor device that is excellent in performance and capable of high-speed operation.

(Means for Solving the Problems) A semiconductor device of the present invention includes a semiconductor layer formed above a semiconductor substrate, and a source electrode and a train electrode provided on the semiconductor layer to form an orthogonal junction. , and a gate electrode provided on the semiconductor layer to form a Schottky junction. The above object is achieved by including a metal thin film formed on at least a portion of the semiconductor layer between the source electrode and the gate electrode and between the drain electrode and the gate electrode.

The semiconductor device of the present invention is a semiconductor device whose operating principle is to control source-drain current by applying a voltage between the source and gate. The metal thin film provided between the source electrode and the gate electrode and between the drain electrode and the gate electrode. It is formed on a part or all of the above semiconductor layer, such as aluminum (AI),
) 7 (Ti), chromium (Cr), nickel (N
Is it from metals such as i)? . The thickness is preferably about 3 atomic layers or less, as explained below.

(Effect) Usually, G is treated with chemical treatments such as wet etching.
An oxide film with a thickness of about 10 mm is formed on the surface of the aAs layer (S.P. Kowalczyk, et al.
al. +Appl. Phys. Lett, 38,
167 (1981)) - This surface oxide film is composed of Asz03 and GalO. , including both. In this way, the surface of GaAsM is As. When covered with an oxide film containing both 03 and Ga202, the height of the band pending at the interface is approximately 0.
．． 7 eV. On the other hand, Ga. The band-pending height at the surface of the GaAs layer covered with a thin film made only of Os is about 0.3 eV.

Furthermore, when an AI thin film with a thickness of 40 or more is deposited on the surface of +GaAs, the barrier height of the Schottky junction formed at the interface is 0.7 eV, which is the same as that of As■03 and GaAs. 0. GaAs covered with an oxide film containing both
It is approximately the same as the height of the band pending at the surface of the layer. On the other hand, when the thickness of the AI thin film is, for example, 3 atomic layers or less, the barrier height of the Schottky junction is 0.3 eV, and the barrier height of the Schottky junction is 0.3 eV when the thickness of the AI thin film is 40 or more. Barrier height, Asz03 and Ga
This value is lower than the height of the band pending on the surface of the GaAs layer covered with the oxide film containing both Js and Js.

This phenomenon can be explained as follows.

When the At thin film is very thin (for example, about 3 atomic layers or less), the following reaction occurs on the surface of the GaAs layer.

2AI +＾S20,→As203 +Asz ↑
In other words, AI that attacks the AI thin film reduces Ass contained in the oxide film formed on the surface of the GaAs layer, thereby converting Ass. Ass has a high vapor pressure and easily diffuses into the atmosphere. In contrast to this. Very thin A
In the I thin film, Gaze3 in the oxide film does not participate in the above reaction and does not change. Therefore. In this case, the surface of the GaAs layer is apparently covered with a thin film consisting only of Ga203, and the band pending height on the surface is as low as 0.3 eV.

On the other hand, if the All film is sufficiently thick (40 or more), the Gaz01 contained in the oxide film further causes the following reaction. 2AI +Ga=O= →A3z03 +2Ga In other words, the AI that makes up the AI thin film is the Ga. O. is reduced to form Ga. Ga is a metal element and remains on the surface of the GaAs layer. Therefore. In this case, the surface of the GaAs layer is apparently covered with an Al film, and a normal Schottky junction is formed.

In the semiconductor device of the present invention, a very thin metal thin film is provided on the surface of the semiconductor layer between the source electrode and the gate electrode and between the drain electrode and the gate electrode.
The height of the band pending on the surface of the semiconductor layer does not have such a metal thin film. For example, it is lower than the conventional HEH↑ as shown in FIG. Therefore, the two-dimensional electron gas is not modulated by the surface depletion layer between the source electrode and the gate electrode and between the drain electrode and the gate electrode. 1 to 1, nearly three times that of conventional HEMT
．． A two-dimensional electron gas concentration of 5XIO"cm-" can be obtained, and the source resistance R. It is possible to reduce the Also,
Since the semiconductor device of the present invention has a planar structure, it has a deep recess structure, for example, compared to the conventional HEMT shown in FIG.
There is no such large gate fringe capacitance Cf.

Therefore, the source-gate capacitance C, . without increasing <, R. This makes it possible to freeze at a low temperature. Although the case where an AI thin film is provided has been explained here, the above Ti, C
It was also found that metals such as r and Ni have the same effect as AI.

(Example) Examples of the present invention will be described below.

FIG. 1(a) shows an AIGaAs/
1 is a cross-sectional view of a GaAs-based IEMT. This HEM'r
was created as follows. first. After etching the surface of the semi-insulating GaAs substrate l with a mixed solution of sulfuric acid, hydrogen peroxide, and water,
As shown in b), on this semi-insulating GaAs substrate 1,
Undoped GaAs layer 2 (thickness s, ooo), undoped AIGaAs base layer 3 (AI group ratio 0.2
6, thickness 20λ) + 2 XIO"cm-'St-doped n"-AIGaAs layer 4 (AI composition ratio 0.26, thickness 200), 2 XIO"cm-'Si-doped n"-AI. Gal-, As graded Ji5 (Al
Group J ratio x = 0.26 → O, thickness 100), and I
Layer 6 (150 layers thick) was continuously elongated by molecular beam epitaxy (MBE). Note that the growth temperature was 600'C, and the V/■Franks ratio was 6.

Next, using the photoresist as an etching mask, etching was performed in a mesa shape to electrically isolate the active region as shown in Figure 1(C), and then the photoresist used as an etching mask was removed. In addition, GaA
A mixed solution of phosphoric acid, hydrogen peroxide, and water was used as an etchant for etching the sJI and AIGaAs layers.

Subsequently, a source electrode 7 and a drain electrode 8 as shown in FIG. 1(d) were formed by a normal process technique such as a photoetching process or an alloying process. Then, after providing a photoresist pattern 13 for forming a gate, using this photoresist pattern 13 as a mask, aluminum (
By depositing AI) to a thickness of 2000,
A1 with gate electrode 9 formed as shown in Figure (e)
The photoresist pattern 13 on which 1114 was deposited was removed using an organic solvent such as acetone (FIG. 1(f)). Next, a photoresist pattern l5 as shown in FIG.
After forming . Using this photoresist pattern 15 as a mask, an AI thin film 10 was formed by irradiating Al flux using a molecular beam epitaxy apparatus. The rotation speed of the substrate was 3 revolutions per second, and the substrate temperature was room temperature. The flux irradiation time depends on the flux intensity. For example, the Al flux strength is 6
In the case of XIO-''Torr, it was 16 seconds.

Finally, the photoresist pattern l5 on which the At thin film 16 has been deposited is removed using an organic solvent such as acetone to form an AIGaAs/GaAs HE as shown in Figure 1(a).
I got MT. The HEMT obtained in this way has a higher source-gate capacitance than the conventional HEMT shown in Figure 2.
Gate width is 200 μm without increasing 91
In this case, the source resistance R, was reduced by 2Ω.

(Effects of the Invention) According to the present invention, the MESPET has a reduced source resistance R8 without increasing the source-gate capacitance c1.
YaHl! A semiconductor device such as an MT can be obtained. Such a semiconductor device is useful as a high-power semiconductor device that has excellent low noise characteristics and is capable of high-speed operation.

Figure 1 (a) to (A
A cross-sectional view showing the manufacturing process of an As/GaAs HEMT, Figure 2 is a conventional AIGaAs/G with a planar structure.
Cross-sectional view of aAs-based HEMT. Figure 3 is a cross-sectional view of a conventional AIGaAs/GaAs HEMT with a recessed structure, and Figure 4 is a cross-sectional view of the AIGaAs/GaAs HEMT shown in Figure 3.
A cross-sectional view showing a distribution model of the gate fringe capacitance Cf at T, FIG. A IGaAs/Ga
In As-based II E MT. Gate width W, -20
3 is a graph showing the relationship between gate length L and source-gate capacitance C■ in the case of 0 μm.

1... Semi-insulating GaAs group temporary, 2... Andobe G
aAs layer 3... undoped AIGaAs spacer layer, 4.=n"-AIGaAs layer, 5...n"
-AIXGa,-. As graded layer (AI composition ratio x=0.26→0), 6・”n””-GaA
s N, 7-source electrode, 8... drain electrode,
9... Gate electrode, 10... A1 thin film, 11.
...Two-dimensional electron gas, 12...Surface depletion layer, l7...
・r1''-GaAs cap layer, 18... Depletion layer directly under the gate.

that's all

Claims (1)

[Claims] 1. A semiconductor layer formed above a semiconductor substrate, a source electrode and a drain electrode provided to form an ohmic contact on the semiconductor layer, and a Schottky junction on the semiconductor layer. A semiconductor device comprising: a gate electrode provided to form a semiconductor layer on at least a portion of the semiconductor layer between the source electrode and the gate electrode and between the drain electrode and the gate electrode; A semiconductor device having a formed metal thin film.