JPH0355912A - Hysteresis circuit - Google Patents

Abstract

PURPOSE:To decrease the effect of the operating speed and to facilitate the check and revision by using a comparator in a semiconductor circuit employing a P-channel MOS transistor(TR) and an N-channel MOS TR and using two transfer gates so as to select between two different reference voltages depending on low or high level being an output logical level of the comparator. CONSTITUTION:Transfer gates 2,3 are provided and V1, V2 are different refer ence voltages. With an output of a comparator 1 at a low level, the reference voltage of the comparator 1 is V1 and with an output of the comparator 1 at a high level, the reference voltage of the comparator 1 is V2. The two differ ent reference voltages are switched by the transfer gates and the load of the comparator is only the gate of the next stage, the effect on the operating speed is less and the low level input voltage, the high level input voltage and the hysteresis width depend only on the two reference voltages.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to hysteresis circuits, and particularly to hysteresis circuits in CMOS integrated circuits.

[Conventional technology]

Conventionally, a hysteresis circuit using a comparator
As shown in the figure, the feed signal is output from the output of the comparator 10.
The circuit structure was such that a resistor R was connected to the back-up signal line.

[Problem to be solved by the invention]

In the conventional hysteresis circuit described above, the reference potential is created by the combined impedance of resistor R, resistor R1, and resistor R2, so there is a drawback that the resistance value must be increased depending on the case. As a result, the load on the comparator 10 becomes large and the operating speed becomes slow. In addition, ' (Low) level input voltage, high (High)
h) When changing the level input voltage and hysteresis width, it is necessary to redesign all the resistance values of the resistors R1 to R3, making it difficult to change the design.

[Means to solve the problem]

The hysteresis circuit of the present invention has a structure in which two different reference potentials are obtained by being switched by a transfer gate depending on the low/high output logic value of the comparator.

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1 shows one embodiment of the present invention. 2 and 3 are transfer gates, V. ,V. are different reference potentials. :I
When the output of the comparator 1 is low, the reference potential of the comparator 1 is v1, and when the output is high, the reference potential of the comparator 1 is %vt. This circuit is connected to the reference voltage V. ,V
2 are 2.5V and 1.9V, respectively, and the power supply voltage is 5V.
Figure 2(a) shows the simulation results when
Shown in (b).

〔Effect of the invention〕

As explained above, the present invention switches two different reference potentials using a transfer gate and has hysteresis. Therefore, the load on the comparator is only the gate of the next stage, which has little effect on the operating speed, and the low level input voltage, high level input voltage, and hysteresis width are different from each other.
Since it is determined by only one reference potential, it has the advantage of being easy to change the design.

[Brief Description of the Drawings] Figure 1 shows the hysteresis circuit of the present invention, Figure 2 (a)
, (b) shows a simulation result of the circuit of FIG. 1, and FIG. 3 shows a conventional hysteresis circuit.

Claims (1)

[Claims] A semiconductor circuit using a P-type MOS transistor and an N-type MOS transistor, characterized in that a comparator is used, and two different reference potentials are switched by two transfer gates depending on the low or high output logical value of the comparator. Hysteresis circuit.