Nothing Special   »   [go: up one dir, main page]

JPH0349217A - Plasma doping device for semiconductor substrate - Google Patents

Plasma doping device for semiconductor substrate

Info

Publication number
JPH0349217A
JPH0349217A JP18510189A JP18510189A JPH0349217A JP H0349217 A JPH0349217 A JP H0349217A JP 18510189 A JP18510189 A JP 18510189A JP 18510189 A JP18510189 A JP 18510189A JP H0349217 A JPH0349217 A JP H0349217A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
substrate
impurity
electrode
impurities
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18510189A
Other languages
Japanese (ja)
Inventor
Noritada Sato
則忠 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP18510189A priority Critical patent/JPH0349217A/en
Publication of JPH0349217A publication Critical patent/JPH0349217A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To activate impurity in a substrate surface layer introduced through plasma doping by forming one of electrodes, facing each other, of a thin resistance wire for generating light when current is fed to heat it and irradiating a semiconductor substrate placed on the other electrode. CONSTITUTION:A sealed container 1 is evacuated through an evaculating system 4 and then a vacuum valve 8 is closed to lower the evacuating speed, and at the same time, atmospheric gas is introduced into the sealed container 1 through a control circuit 6 and voltage is applied across the electrodes 2B and 2C to generate glow discharge therebetween so that a semiconductor region containing that impurity is formed on a semiconductor substrate 3 disposed on the electrode 2B. Then, the container 1 is evacuated again, and then the electrode 2C is heated by feeding current to a wire 7C for heating the thin resistance wire thus generating infrared rays. The generated infrared rays irradiate the surface of the substrate 3 uniformly to raise the surface temperature of the substrate 3. As a result, impurity atoms introduced before enter into the lattice positions of the semiconductor substrate from the interlattice positions to substitute for the substrate atoms thus increasing the concentration of the electrically activated impurity.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体基体に不純物を導入する装置に係り、
特にプラズマドーピングされた不純物を活性化するプラ
ズマドーピング!装置に関する。
[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to an apparatus for introducing impurities into a semiconductor substrate,
Plasma doping that especially activates plasma-doped impurities! Regarding equipment.

〔従来の技術〕[Conventional technology]

半導体基体に不純物をドープして基体と不純物濃度の異
なる半導体領域を形成する方法として固相拡散法や気相
拡散法などの熱拡散法が知られているが、これらは80
0℃〜1200℃の高温度下で拡散を行うものであり、
そのため設備が複雑で高価であり、またその保守が厄介
である。また熱拡散法は半導体基体の不純物の面内均一
性に間ねがあり、しかもl pm以下の浅い拡散層の形
成が困難である。また、前記のような高温度の熱処理は
、半導体基体中に格子欠陥を先じさせたり重金属元素が
基体中に拡散してキャリアのライフタイムを低下させる
等の問題を生ずる。この問題の解決には、拡散工程にお
ける処理@度を下げればよいが、800℃以下ではドー
ピングする不純物元素の拡散係数が低下するので経済性
が低く、再現性も悪化してしまう。
Thermal diffusion methods such as solid-phase diffusion and vapor-phase diffusion are known as methods for doping impurities into a semiconductor substrate to form a semiconductor region having an impurity concentration different from that of the substrate.
Diffusion is performed at high temperatures of 0°C to 1200°C,
Therefore, the equipment is complicated and expensive, and its maintenance is troublesome. Further, in the thermal diffusion method, there is a problem in the in-plane uniformity of impurities in the semiconductor substrate, and furthermore, it is difficult to form a shallow diffusion layer of 1 pm or less. Furthermore, the above-mentioned high-temperature heat treatment causes problems such as lattice defects being formed in the semiconductor substrate and heavy metal elements being diffused into the substrate, reducing the lifetime of carriers. This problem can be solved by lowering the processing temperature in the diffusion step, but at temperatures below 800° C., the diffusion coefficient of the impurity element to be doped is reduced, resulting in low economic efficiency and poor reproducibility.

イオン注入法はこのような半導体ウェハ面内の不純物濃
度の不均一性や高温度処理に伴う種々の問題点を解決で
きるもので、広く半導体装置の製造プロセスに利用され
るに至っているが、非常な高エネルギで半導体に不純物
を打ち込むので、半導体表面に損傷を与えてしまう問題
が本質的にあり、また打ち込まれたそのママの状態では
不純物の電気的活性度が低いので、半導体表面のダメー
ジを回復しかつ不純物を活性化するため800℃〜12
50℃の高温熱処理を必要とし、高温熱処理を完全にな
くすことができないという問題がある。
The ion implantation method can solve various problems associated with the non-uniformity of impurity concentration within the semiconductor wafer surface and high temperature processing, and has come to be widely used in the manufacturing process of semiconductor devices. Since impurities are implanted into the semiconductor with high energy, there is an inherent problem of damaging the semiconductor surface.Also, since the impurity has low electrical activity in its original state, it is difficult to damage the semiconductor surface. 800°C to 12°C to recover and activate impurities
There is a problem that high temperature heat treatment of 50° C. is required and high temperature heat treatment cannot be completely eliminated.

このような従来の不純物導入方法の問題点を解決するた
めζこ本発明者らは先に%開11859−218727
号公報に2いてプラズマドーピング法による不純物導入
方法を開示した。この方法は半導体基体に導入するべき
不純物元素を含むドーピングガスを水素で稀釈してふん
い気ガスとし、これをグロー放電によりプラズマ化し、
このプラズマによりてドーピングガスを分解して半導体
基体表面に不純物を導入する手法である。この方法は2
00℃程度の低温度においても不純物を導入することが
できるので、ブレーナ素子やMO8ICでは酸化膜汚染
や接合深さの変動、さらに高熱による格子欠陥が生じな
い。さらにプラズマドーピング装置が極めて単純な構造
のものを用いることができる特徴がある。才だ不純物を
導入する際の工ふルギも小さいために、半導体基体表面
の格子欠陥の発生も少ない。このプラズマドーピング法
はイオン注入法とは異なり、半導体基体表面でドープし
た不純物濃度が高く(約1022原子/d)、深さ方向
に濃度が急減するプロファイルを示し、濃度分布も約0
.2pmと極めて浅い。このため浅い接合や浅いオーミ
ックコンタクト層の形成に有効に使用することができる
In order to solve the problems of the conventional impurity introduction method, the present inventors have previously developed
No. 2 discloses a method of introducing impurities by plasma doping. In this method, a doping gas containing impurity elements to be introduced into a semiconductor substrate is diluted with hydrogen to form a gas, which is turned into plasma by glow discharge.
This method uses this plasma to decompose the doping gas and introduce impurities onto the surface of the semiconductor substrate. This method is 2
Since impurities can be introduced even at temperatures as low as 00° C., oxide film contamination, junction depth fluctuations, and lattice defects due to high heat do not occur in Brehner elements and MO8ICs. Furthermore, a plasma doping apparatus having an extremely simple structure can be used. Since the effort required to introduce the impurities is small, lattice defects on the surface of the semiconductor substrate are also less likely to occur. This plasma doping method differs from the ion implantation method in that the concentration of impurities doped at the surface of the semiconductor substrate is high (approximately 1022 atoms/d), and the concentration shows a profile in which the concentration decreases rapidly in the depth direction, and the concentration distribution is also approximately 0.
.. Extremely shallow at 2pm. Therefore, it can be effectively used for forming shallow junctions and shallow ohmic contact layers.

さらに不出願人は先に、このプラズマドーピング方法を
用いて半導体基体中に導入された不純物を活性化するた
めの装置を、冥願昭63−18341号にて提案してい
る。第4図にその装置の構成を示す。この装置は密閉容
器l、対向電極2である網目状電極2人および平板状電
極2B、半導体基体3、真空排気系4.ドーピングガス
を稀釈したふんい気ガス5.ガスの圧力と流量を調整す
るための調整回路6.グロー放電用直流電源7A、半導
体加熱用電源7B、グロー放電時のガス圧力を調整する
ための真空バルブ8.真空計9.およびタングステンフ
ィラメントを石英ガラス管に封じ込んだ多数個の棒状の
赤外線ランプ10.該ランプ用電源11.該ランプから
発生する赤外線を反射させる反射板12から構成されて
いる。
Furthermore, the applicant has previously proposed in Meikan Sho 63-18341 an apparatus for activating impurities introduced into a semiconductor substrate using this plasma doping method. Figure 4 shows the configuration of the device. This device includes a sealed container 1, two mesh electrodes serving as counter electrodes 2 and a flat electrode 2B, a semiconductor substrate 3, and a vacuum exhaust system 4. Feed gas diluted with doping gas 5. Adjustment circuit for adjusting gas pressure and flow rate 6. DC power source 7A for glow discharge, power source 7B for semiconductor heating, vacuum valve 8 for adjusting gas pressure during glow discharge. Vacuum gauge9. and multiple rod-shaped infrared lamps with tungsten filaments sealed in quartz glass tubes 10. Power supply for the lamp 11. It is composed of a reflecting plate 12 that reflects infrared rays generated from the lamp.

この装着によれば、プラズマドーピングにより、平板状
電極2Bにl!l!&された半導体基体3中に所定の不
純物を導入した後、網目状電極2人の網目を通して、赤
外線ランプlOから赤外l1ii8照射することにより
、半導体基体3の表面のみを短時間に加熱し、不純物を
電気的に活性にすることができる。
According to this installation, l! is applied to the flat electrode 2B by plasma doping. l! After introducing a predetermined impurity into the semiconductor substrate 3, only the surface of the semiconductor substrate 3 is heated in a short time by irradiating infrared rays from an infrared lamp IO through the mesh of the two mesh electrodes, Impurities can be made electrically active.

〔発明が解決しようとするaM〕[aM that the invention attempts to solve]

しかしながら前述の公報で開示したプラズマドーピング
による不純物の導入方法においては、導入された不純物
の全濃度は確かに高濃度ではあるが、このうち電気的に
活性な不純物濃度は約10′6原子/−であり、充分な
半導体特性を得ることができないという問題がある。そ
のために本発明者らが特開昭59−218728号公報
で開示したようCへプラズマドーピング法で所定の不純
物を半導体基体中にドープしたのち、さらにアルゴンプ
ラズマを用いて、導入された不純物の活性化を図ること
が行われる。しかしながらこの方法では全体の工程が二
工程となるために不純物導入に長時間を要し、能率的な
方法とは言えない問題が生ずる。
However, in the method of introducing impurities by plasma doping disclosed in the above-mentioned publication, although the total concentration of introduced impurities is certainly high, the concentration of electrically active impurities is about 10'6 atoms/- Therefore, there is a problem that sufficient semiconductor characteristics cannot be obtained. For this purpose, as disclosed in Japanese Patent Application Laid-open No. 59-218728, the present inventors doped certain impurities into a semiconductor substrate using a C plasma doping method, and then activated the introduced impurities using argon plasma. The aim is to improve the However, this method requires a long time to introduce impurities because the entire process consists of two steps, resulting in a problem that it cannot be said to be an efficient method.

菫た、笑願昭63−18341号に提案した前記第4図
の構成の場合、半導体基体を加熱する光源である赤外線
ランプの管球表面にもドーピングする不純物が被着し、
光源の光量が減少する。そのため、数回のプラズマドー
ピングを行う毎に、光源の管球を取り外して洗浄する必
要が生じ、装置のメンテナンスが煩雑になるという問題
がある。
In the case of the configuration shown in FIG. 4 proposed in Sumita, Shogan No. 18341/1986, doping impurities also adhere to the bulb surface of the infrared lamp, which is the light source for heating the semiconductor substrate.
The light intensity of the light source decreases. Therefore, every time plasma doping is performed several times, it becomes necessary to remove and clean the bulb of the light source, resulting in a problem that maintenance of the apparatus becomes complicated.

この発明は上述の点に鑑みてなされ、その目的は、半導
体基体の不純物の導入された表面層を短時間加熱するの
みで半導体基体表面の浅い部分(こ電気的に活性な不純
物の高濃度領域を形成可能で、かつfcllのメンテナ
ンスが容易な半導体基体用プラズマドーピング装置を提
供することにある。
The present invention has been made in view of the above-mentioned points, and its purpose is to heat shallow parts of the surface of the semiconductor substrate (areas with high concentration of electrically active impurities) by simply heating the impurity-introduced surface layer of the semiconductor substrate for a short period of time. It is an object of the present invention to provide a plasma doping apparatus for semiconductor substrates that can form FCL and facilitate maintenance of FCLL.

CI’l1題を解決するための手段〕 上記の目的を連取するために、本発明によれば、密閉容
器内に対向電極を備え、ドーピングガスを稀釈したふん
い気ガスを密閉容器内に満たし、前記対向電極に所定の
電圧を印加して、ふんい気ガス内にプラズマを発生させ
る半導体基体用プラズマドーピング装置において、前記
対向電極の一方の電極を、通電加熱により光を発生し眩
光を他方の電極に載置された半導体基体に照射する抵抗
細線にて形成するものとする。なお、抵抗細線にて形成
された対向電極に対し、半導体基体とは反対側に、光を
反射する反射板を設けることが望ましい。
Means for Solving the CI'l1 Problem] In order to achieve the above objects, the present invention provides a counter electrode in a sealed container, and fills the sealed container with a fume gas diluted with a doping gas. , in a plasma doping apparatus for a semiconductor substrate in which a predetermined voltage is applied to the counter electrode to generate plasma in the air gas, one of the counter electrodes is electrically heated to generate light and dazzle to the other. It shall be formed by a resistive thin wire that irradiates the semiconductor substrate placed on the electrode. Note that it is desirable to provide a reflective plate for reflecting light on the opposite side of the semiconductor substrate to the counter electrode formed of the resistive thin wire.

不純物元素を含むドーピングガスとしては、フォスフイ
ン(PH3)−アルシン(AsHs)’IFのような無
機系ガスや、%棟の不純物元素を含む有機金属化合物ガ
スが用いられる。ドーピングガスの稀釈はヘリウムガス
、アルゴンガス、水素ガス、窒素ガス等を用いてなされ
る。ふんい気ガスは数Torrの圧力で密閉容器内に満
たされる。対向眠極間に例えば直流電圧が印加されると
、グロー放電により上記ふんい気はプラズマ化される。
As the doping gas containing an impurity element, an inorganic gas such as phosphine (PH3)-arsine (AsHs)'IF, or an organometallic compound gas containing a large number of impurity elements is used. The doping gas is diluted using helium gas, argon gas, hydrogen gas, nitrogen gas, or the like. The airtight container is filled with the air gas at a pressure of several Torr. When, for example, a DC voltage is applied between the opposing sleeping poles, the above-mentioned feces are turned into plasma by glow discharge.

このプラズマはドーピングガスを分解し、分解によりて
生じた不純物原子は基体内部に拡散する。半導体基体と
しては、結晶質、非晶質のシリコン、ゲルマニウム等が
用いられる。不純物の導入された基体表面層の加熱は、
一方の対向電極を形成する抵抗細線9例えばタングステ
ン細線を通電加熱することによって発生する光照射によ
りて行われる。
This plasma decomposes the doping gas, and impurity atoms generated by the decomposition diffuse into the interior of the substrate. As the semiconductor substrate, crystalline or amorphous silicon, germanium, etc. are used. Heating the substrate surface layer into which impurities have been introduced is
This is carried out by irradiation with light generated by heating the resistive thin wire 9, for example, a thin tungsten wire, which forms one of the opposing electrodes.

〔作用〕[Effect]

抵抗細線電極による光照射は短時間性われる。 Light irradiation by the resistive thin wire electrode takes place for a short period of time.

元は半導体基体中で吸収されるので表面層に近い根元強
度は強く、従りて光照射によって表面層の温度が最も高
く刀口熱される。この表面層の温度上昇によつて、表面
層内の導入不純物は、単結晶の場合は、格子間位置から
基体の原子の位置へ置換し、活性化される。また上記活
性化は短時間に起こるので光照射は短時間でよく、温度
上昇による結晶欠陥の発生を防止できる。また、光照射
は抵抗細線にて形成された一方の対向電極自体からなさ
れ、例え抵抗細線に不純物が付層しても放電の際にこの
不純物は除去されるので、赤外線ランプを用いる場合の
ような管球表面の汚染1こよる光量不足が生じることは
ない。
Since it is originally absorbed in the semiconductor substrate, the root strength near the surface layer is strong, and therefore, the surface layer is heated to the highest temperature by light irradiation. Due to this temperature rise in the surface layer, impurities introduced into the surface layer, in the case of a single crystal, are substituted from interstitial positions to atomic positions of the substrate and activated. Further, since the activation occurs in a short time, light irradiation can be performed for a short time, and crystal defects caused by temperature rise can be prevented. In addition, light irradiation is performed from one counter electrode itself formed of a thin resistance wire, and even if impurities are layered on the thin resistance wire, these impurities are removed during discharge, so it is similar to when using an infrared lamp. There will be no shortage of light due to contamination of the tube surface.

〔実施例〕〔Example〕

次にこの発明の実施例を図面に基づいて説明する。 Next, embodiments of the present invention will be described based on the drawings.

第1図は本発明の実施例1こ用いた装置の構成を示すも
ので、@4図と同一の部材には同一の符号を付し、その
説明を省略する。
FIG. 1 shows the configuration of an apparatus used in Example 1 of the present invention, and the same members as in FIG.

対向電極加の一方の電極は、抵抗細線により形成された
抵抗細線電極2Cとなりでいる。この抵抗細線電極2C
は抵抗細線加熱用電源7C4こより通IJL 7111
熱され、赤外線を発生する。12Aは反射板であって、
抵抗細線電極2Cから発生した赤外線のうち、半導体基
体3とは反対側に向りて照射されたものを、半導体基体
3側に反射する。
One of the opposing electrodes serves as a resistive thin wire electrode 2C formed of a resistive thin wire. This resistance thin wire electrode 2C
IJL 7111 is a power supply for heating thin resistance wires 7C4
It is heated and emits infrared radiation. 12A is a reflective plate,
Among the infrared rays generated from the resistive thin wire electrode 2C, the infrared rays irradiated toward the side opposite to the semiconductor substrate 3 are reflected toward the semiconductor substrate 3 side.

以上の構成において半導体基体3に不純物を導入する具
体的な手順は次の通りである。
The specific procedure for introducing impurities into the semiconductor substrate 3 in the above configuration is as follows.

まず、真空排気系4により密閉容器l内を排気し、約l
Xl0Torrの真空にしたのち、真空バルブ8を絞り
、真空排気系4の排気速度を下げると同時に密閉容器I
Iこふんい気ガスを調整回路6を通して導入し、公知の
方法で電極2B、2C間に電圧を印加してグロー放電を
発生させると電極2B上に配置した半導体基体3にその
不純物を含む半導体領域が形成される。次いで、密閉容
器1内を再び排気しt約lX10TOrrの真空にした
のち、抵抗細線電極2Cを抵抗細線加熱用電源7Cによ
り通電加熱し、赤外線を発生させる。発生した赤外線は
半導体基体3の表面に均等に照射され、この照射赤外線
により該基体3の表面温度が上昇する。その結果、先に
導入した不純物原子が半導体基体の格子間位置から格子
位置に該基体原子と置換して入り、電気的に活性化した
不純物原子の濃度が増加する。
First, the inside of the closed container l is evacuated by the vacuum evacuation system 4, and about 1
After creating a vacuum of
When air gas is introduced through the adjustment circuit 6 and a voltage is applied between the electrodes 2B and 2C using a known method to generate a glow discharge, the semiconductor containing the impurities is transferred to the semiconductor substrate 3 placed on the electrode 2B. A region is formed. Next, the inside of the sealed container 1 is evacuated again to a vacuum of about 1×10 TOrr, and then the resistive thin wire electrode 2C is heated with electricity by the resistive thin wire heating power source 7C to generate infrared rays. The generated infrared rays are uniformly irradiated onto the surface of the semiconductor substrate 3, and the surface temperature of the substrate 3 is increased by the irradiated infrared rays. As a result, the previously introduced impurity atoms enter the semiconductor substrate from interstitial positions to lattice positions, replacing the base atoms, and the concentration of electrically activated impurity atoms increases.

第2図はシリコン単結晶基体3にホウ素原子を導入した
場合のホウ素の濃度分布を示すプロファイル線図である
。この場合不純物は下記の電性で導入された。
FIG. 2 is a profile diagram showing the concentration distribution of boron when boron atoms are introduced into the silicon single crystal substrate 3. FIG. In this case, impurities were introduced with the following charge.

半導体基体:シリコン単結晶、n型、比抵抗約100Ω
cm、@面仕上げ 基体温度:200℃ ふんい気ガス:水累で1ooo ppmに稀釈したジボ
ラン グロー放電時の圧カニ 4 T□rr 放電パワー: D C900V 、 2 mA/cs(
電極間距離:501m 放電時間:60秒 赤外線照射時間:20秒、40秒 第2図において曲線13は、赤外線照射前のホウ素濃度
分布を示し、このときの電気的に活性化したホウ素濃度
分布を曲線141こ示す。曲線15は抵抗細線電極2C
を通電7JO熱して半導体基体3にm秒間赤外線を照射
した場合で、曲線16は初秒間赤外線を照射した場合の
電気的に活性化したホウ素濃度分布である。このように
赤外線の照射時間の増加とともに基体3表面の温度が上
昇するため、電気的に活性化したホウ素濃度は増加する
。上記の場合に2いて曲線13に示すホウ素全濃度分布
は、二次イオン質量分析法(5econdary Io
n MassSpectrometrye S I M
S )を用いて測定された。また電気的に活性な不純t
tlJia度は拡がり抵抗法で測定された。ざらに、抵
抗細線電極2Cを通τ加熱して基体3異而に赤外線を照
射する時間がか秒と40秒のときの該基体表面の最高m
匣はそれぞれ900℃と1】00℃であることが熱電対
(0,211φ。
Semiconductor substrate: silicon single crystal, n-type, specific resistance approximately 100Ω
cm, @Surface finish Substrate temperature: 200℃ Air gas: Diborane diluted to 100 ppm with water Pressure crab during glow discharge 4 T□rr Discharge power: DC900V, 2 mA/cs (
Distance between electrodes: 501 m Discharge time: 60 seconds Infrared irradiation time: 20 seconds, 40 seconds In Fig. 2, curve 13 shows the boron concentration distribution before infrared irradiation, and the electrically activated boron concentration distribution at this time. A curve 141 is shown. Curve 15 is resistance thin wire electrode 2C
Curve 16 shows the electrically activated boron concentration distribution when the semiconductor substrate 3 is heated for 7JO and irradiated with infrared rays for m seconds. In this way, as the irradiation time of infrared rays increases, the temperature of the surface of the substrate 3 increases, so the concentration of electrically activated boron increases. In the above case, the total boron concentration distribution shown in curve 13 is calculated using secondary ion mass spectrometry (5 secondary ion mass spectrometry).
n Mass Spectrometry S I M
S). Also, electrically active impurity t
The tlJia degree was measured by the spreading resistance method. Roughly speaking, the maximum m of the surface of the substrate 3 when the time for heating the resistive thin wire electrode 2C with τ and irradiating the substrate 3 with infrared rays is 40 seconds.
The box has a thermocouple (0,211φ) that is 900°C and 100°C, respectively.

白金−白金ロジウム)を用いた実験で確認された。This was confirmed in an experiment using platinum-platinum rhodium.

第3図はンリコン単結晶基体3に不純物としてリンを導
入した場合のリンの濃度分布を示すプロファイル線図で
ある。この場合不純物は下記条件で導入された。
FIG. 3 is a profile diagram showing the concentration distribution of phosphorus when phosphorus is introduced as an impurity into the NRICON single crystal substrate 3. In this case, impurities were introduced under the following conditions.

半導体基体:シリコン単結晶、P型、比抵抗的iooΩ
cm 、鏡面仕上げ 基体温度:200°C ドーパント不純物ガス:水累でloooppm  に稀
釈したフォスフイン グロー放電時の圧カニ 4 Torr 放電パワー: D C90(l V * 2 mA/c
m電極間距111i : 50m1m 放電時間:60秒 赤外線照射時間:20秒、 40秒 第3図において曲11117は赤外線照射前のリン濃度
分布であり、このときの電気的に活性なリン濃度分布は
曲918で示される。曲@19は赤外線照射時間が(9
)秒1曲線21は赤外線照射時間が荀秒の場合の電気的
に活性なリンの濃度分布である。
Semiconductor substrate: silicon single crystal, P type, resistivity iooΩ
cm, mirror finish Substrate temperature: 200°C Dopant impurity gas: Phosphate diluted to loooppm with water Pressure crab during glow discharge 4 Torr Discharge power: DC90 (l V * 2 mA/c
Distance between m electrodes 111i: 50m1m Discharge time: 60 seconds Infrared irradiation time: 20 seconds, 40 seconds In Figure 3, track 11117 is the phosphorus concentration distribution before infrared irradiation, and the electrically active phosphorus concentration distribution at this time is 918. Song @19 has infrared irradiation time (9
) Second 1 curve 21 is the concentration distribution of electrically active phosphorus when the infrared irradiation time is 1 second.

〔発明の効果〕〔Effect of the invention〕

この発明によれば、密閉容器内に対向電極を備え、ドー
ピングガスを稀釈したふんい気ガスを密閉容器内に満た
し、前記対向電極に所定の電圧を印刀口して、ふんい気
ガス内にプラズマを発生させる半導体基体用プラズマド
ーピング装置において、前記対向電極の一方の電極を、
通電過熱により光を発生し該光を他方の電極に載置され
た半導体基体に照射する抵抗細線にて形成するものとし
た。
According to the present invention, a counter electrode is provided in a sealed container, the airtight container is filled with a doping gas diluted, and a predetermined voltage is applied to the counter electrode to fill the airtight gas. In a plasma doping apparatus for a semiconductor substrate that generates plasma, one electrode of the counter electrode is
The resistor wire was formed of a thin resistive wire that generates light by heating and energizing it and irradiates the semiconductor substrate placed on the other electrode with the light.

よってこの装置を用いると、光照射による加熱効果が半
導体基体に対して平均的ζこ小さくその結果結晶欠陥を
生じさせることなくプラズマドーピングにより導入され
た基体表面層の不純物を電気的に活性化することができ
る。
Therefore, when this device is used, the heating effect due to light irradiation is on average smaller than ζ on the semiconductor substrate, and as a result, impurities in the surface layer of the substrate introduced by plasma doping can be electrically activated without causing crystal defects. be able to.

また不純物の活性化は短時間の光照射により達成される
ので、不純物導入の全工程を短時間で行うことができる
。さらに光照射による不純物活性化の過程が短時間に達
成されるため、半導体基体表面層の不純物領域が拡散で
拡がることがないので、プラズマドーピングで得られた
不純物領域をそのま望維持することができ、極めて浅い
領域に不純物を導入できるというプラズマドーピングの
長所がそのまま生かされる。光照射は抵抗細線から成る
電極目体を発光体として行うため、赤外線ランプを用い
る場合のようにランプの管球表面の汚染による光量不足
は主じない。よって再現性良く不純物の活性化が可能と
なるとともに、メンテナンス性が向上するという効果も
奏せられる。
Furthermore, since activation of impurities is achieved by short-time light irradiation, the entire process of introducing impurities can be performed in a short time. Furthermore, since the process of impurity activation by light irradiation is achieved in a short time, the impurity region in the surface layer of the semiconductor substrate does not spread due to diffusion, so the impurity region obtained by plasma doping can be maintained as desired. The advantage of plasma doping, which allows impurities to be introduced into extremely shallow regions, can be utilized as is. Since the light irradiation is performed using the electrode eye made of a thin resistive wire as the light emitter, there is no problem of insufficient light intensity due to contamination of the lamp bulb surface, unlike when using an infrared lamp. Therefore, it is possible to activate impurities with good reproducibility, and it is also possible to improve maintainability.

従って本発明は放射線検出累子に通用し−た場合はpn
接合層のような放射線1こ対して不感層となる領域を薄
くできるばかりでなく、MO8ICデバイスや三次元デ
バイスなどの拡散層などの形成に際して有効に利用でき
る。
Therefore, if the present invention is applicable to a radiation detection device, pn
Not only can a region such as a bonding layer that is insensitive to radiation be made thinner, but it can also be effectively used in forming a diffusion layer of MO8IC devices, three-dimensional devices, and the like.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の実施例に係るプラズマド−ピング装
置の構成図、第2図はこの発明の実施例に係るホウ素の
濃度分布を示すプロファイル線図、第3図はこの発明の
実施例に係るリンの濃度分布を示すプロファイル線図、
第4図は本出願人が先に出願した装置の構成図である。 l・・・密閉容器、2.20・・・対向電極、2A・・
・網目状電極、2B・・・平板状電極、2C・・・抵抗
細線電極、3・・・半導体基体、4・・・真空排気系、
5・・・ふんい気ガス、6・・・ガス圧、ガス流量調整
回路、7A・・・グロー放電用直流電源、7B・・・基
体加熱用電源、7C・・・抵抗細線加熱用電源、8・・
・真空バルブ、9・・・真空計、10・・・赤外線ラン
プ、11・・・ランプ用電ビ 術 口 暮4不表雨カ゛脅費拒駒雀(入) 第3 図
FIG. 1 is a configuration diagram of a plasma doping apparatus according to an embodiment of the present invention, FIG. 2 is a profile diagram showing the boron concentration distribution according to an embodiment of the present invention, and FIG. 3 is an embodiment of the present invention. A profile diagram showing the concentration distribution of phosphorus related to
FIG. 4 is a block diagram of a device previously filed by the present applicant. l...Airtight container, 2.20...Counter electrode, 2A...
-Mesh electrode, 2B... Flat electrode, 2C... Resistance thin wire electrode, 3... Semiconductor substrate, 4... Vacuum exhaust system,
5... Air gas, 6... Gas pressure, gas flow rate adjustment circuit, 7A... DC power source for glow discharge, 7B... Power source for base heating, 7C... Power source for heating thin resistance wire, 8...
・Vacuum valve, 9...Vacuum gauge, 10...Infrared lamp, 11...Electric cable for lamp 4. Unexpected rain, threat of rejection of expenses (included) Figure 3

Claims (1)

【特許請求の範囲】[Claims] 1)密閉容器内に対向電極を備え、ドーピングガスを稀
釈したふんい気ガスを密閉容器内に満たし、前記対向電
極に所定の電圧を印加して、ふんい気ガス内にプラズマ
を発生させる半導体基体用プラズマドーピング装置にお
いて、前記対向電極の一方の電極を、通電加熱により光
を発生し該光を他方の電極に載置された半導体基体に照
射する抵抗細線にて形成したことを特徴とする半導体基
体用プラズマドーピング装置。
1) A semiconductor that includes a counter electrode in a sealed container, fills the container with a doping gas diluted air gas, and applies a predetermined voltage to the counter electrode to generate plasma in the air gas. In the plasma doping apparatus for a substrate, one of the opposing electrodes is formed of a resistive thin wire that generates light by heating with electricity and irradiates the semiconductor substrate placed on the other electrode with the light. Plasma doping equipment for semiconductor substrates.
JP18510189A 1989-07-18 1989-07-18 Plasma doping device for semiconductor substrate Pending JPH0349217A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18510189A JPH0349217A (en) 1989-07-18 1989-07-18 Plasma doping device for semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18510189A JPH0349217A (en) 1989-07-18 1989-07-18 Plasma doping device for semiconductor substrate

Publications (1)

Publication Number Publication Date
JPH0349217A true JPH0349217A (en) 1991-03-04

Family

ID=16164873

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18510189A Pending JPH0349217A (en) 1989-07-18 1989-07-18 Plasma doping device for semiconductor substrate

Country Status (1)

Country Link
JP (1) JPH0349217A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0616729A1 (en) * 1991-12-13 1994-09-28 United Solar Systems Corp Semiconductor device and microwave process for its manufacture.
US6343105B1 (en) 1997-06-10 2002-01-29 Nec Corporation Viterbi decoder
JP2002118074A (en) * 2000-10-06 2002-04-19 Semiconductor Energy Lab Co Ltd Method of forming semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0616729A1 (en) * 1991-12-13 1994-09-28 United Solar Systems Corp Semiconductor device and microwave process for its manufacture.
EP0616729A4 (en) * 1991-12-13 1994-11-30 United Solar Systems Corp SEMICONDUCTOR DEVICE AND PRODUCTION METHOD BY MEANS OF MICROWAVE DEPOSITION.
US6343105B1 (en) 1997-06-10 2002-01-29 Nec Corporation Viterbi decoder
JP2002118074A (en) * 2000-10-06 2002-04-19 Semiconductor Energy Lab Co Ltd Method of forming semiconductor device

Similar Documents

Publication Publication Date Title
US5627081A (en) Method for processing silicon solar cells
US4539431A (en) Pulse anneal method for solar cell
US4398343A (en) Method of making semi-amorphous semiconductor device
US4468853A (en) Method of manufacturing a solar cell
US4661177A (en) Method for doping semiconductor wafers by rapid thermal processing of solid planar diffusion sources
JPH04302136A (en) Improved method for forming laser crystallized cladding layers for amorphous silicon light emitting diodes and radiation sensors
JPS588128B2 (en) Semiconductor device manufacturing method
US4069492A (en) Electroluminescent semiconductor device having a body of amorphous silicon
US4169740A (en) Method of doping a body of amorphous semiconductor material by ion implantation
US5514620A (en) Method of producing PN junction device
JPH0338756B2 (en)
US4618381A (en) Method for adding impurities to semiconductor base material
JPS6165441A (en) Treatment method for plasma silicon nitride insulation film
US3732471A (en) Method of obtaining type conversion in zinc telluride and resultant p-n junction devices
JPH0349217A (en) Plasma doping device for semiconductor substrate
Gelpey et al. Advanced annealing for sub-130nm junction formation
JPS6355856B2 (en)
Tsuo et al. High-flux solar furnace processing of silicon solar cells
US3599059A (en) Ion implanted cadmium sulfide pn junction device
JPH08148443A (en) Method of ion implantation
JPH01129413A (en) Introduction of impurity into semiconductor substrate
JP3150681B2 (en) Thin film amorphous semiconductor device
EP4276920A1 (en) Method for manufacturing a semi-finished cdte based thin film solar cell device
CA2031417A1 (en) Method of producing mis transistor having gate electrode of matched conductivity type
JPH07106265A (en) Method for manufacturing silicon carbide semiconductor device