JPH0344934A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0344934A JPH0344934A JP1180743A JP18074389A JPH0344934A JP H0344934 A JPH0344934 A JP H0344934A JP 1180743 A JP1180743 A JP 1180743A JP 18074389 A JP18074389 A JP 18074389A JP H0344934 A JPH0344934 A JP H0344934A
- Authority
- JP
- Japan
- Prior art keywords
- film
- layer
- electrodes
- close contact
- gold bumps
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 239000010931 gold Substances 0.000 claims abstract description 23
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052737 gold Inorganic materials 0.000 claims abstract description 14
- 238000009792 diffusion process Methods 0.000 claims abstract description 8
- 230000004888 barrier function Effects 0.000 claims abstract description 6
- 238000009713 electroplating Methods 0.000 claims abstract description 4
- 238000007747 plating Methods 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052782 aluminium Inorganic materials 0.000 abstract description 5
- 238000002161 passivation Methods 0.000 abstract description 5
- 238000004544 sputter deposition Methods 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 2
- 238000000992 sputter etching Methods 0.000 abstract description 2
- 230000001681 protective effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000011241 protective layer Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、半導体装置の構造に関し、特に外部端子であ
る電極用金バンプを有する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a semiconductor device, and particularly to a semiconductor device having gold bumps for electrodes serving as external terminals.
［従来の技術］
従来、半導体装置の電極用金バンプの構造に関しては数
多くの提案がなされ、改良が加えられている。第２図は
、集積回路上に形成された電極用金バンプの断面図であ
る。[Prior Art] Conventionally, many proposals have been made regarding the structure of gold bumps for electrodes of semiconductor devices, and improvements have been made. FIG. 2 is a cross-sectional view of gold bumps for electrodes formed on an integrated circuit.
第２図に示すように集積回路上の金バンプは、密着層で
あるＣｒ膜２５、拡散バリア層であるＴａ膜膜幅６保護
層であるＡｕ膜２７を付着させた後、その上に金メッキ
部２８を形成するような構造をとっていた。As shown in Fig. 2, gold bumps on an integrated circuit are formed by depositing a Cr film 25 as an adhesion layer, a Ta film 6 width as a diffusion barrier layer, and an Au film 27 as a protective layer. The structure was such that a section 28 was formed.
このような材料にて形成された金バンプは、Ｃｒ膜２５
、Ｔａ膜膜幅６大気に晒されているために、高湿度の雰
囲気で使用した場合、Ｃｒ膜２５、Ｔａ膜膜幅６腐食す
るという欠点があった。A gold bump formed of such a material is coated with a Cr film 25.
Since the Ta film 25 and the Ta film width 6 are exposed to the atmosphere, there is a drawback that the Cr film 25 and the Ta film width 6 corrode when used in a high humidity atmosphere.
［発明が解決しようとする課題］
本発明の目的は、上記欠点を解決しようとするもので、
高湿度雰囲気で使用しても腐食しないＴｉ膜及びＴａ１
ｌを用い、高信頼性半導体装置を提供することにある。[Problem to be solved by the invention] The purpose of the present invention is to solve the above-mentioned drawbacks,
Ti film and Ta1 that do not corrode even when used in high humidity atmosphere
The object of the present invention is to provide a highly reliable semiconductor device using 1.
［課題を解決するための手段］
拡散、絶縁膜、配線を形成した集積回路の前記絶縁膜及
び配線の上に、密着層としてのＴｉ膜、拡散バリア層と
してのＴａ膜、メッキ下１ｔ！ｌｕ層であるＡｕ膜、及
び電解メッキによる金バンプにより構成される電極が形
成されてなることを特徴とする半導体装置。[Means for solving the problem] A Ti film as an adhesion layer, a Ta film as a diffusion barrier layer, and 1t below plating on the insulating film and wiring of an integrated circuit in which diffusion, insulating film, and wiring are formed! A semiconductor device characterized in that an electrode is formed of an Au film as a lu layer and gold bumps formed by electrolytic plating.
［実施例コ
以下に、本発明について、製造方法の実施例にもとずき
詳細に説明をする。[Example] The present invention will be explained in detail below based on an example of a manufacturing method.
第１図にあるように、本発明の電極用金バンプは、シリ
コン基板１１、シリコン酸化膜１２、アルミ電極バット
１３及びパッシベーション膜１４から成る集積回路上に
形成する。As shown in FIG. 1, the gold bumps for electrodes of the present invention are formed on an integrated circuit consisting of a silicon substrate 11, a silicon oxide film 12, an aluminum electrode butt 13, and a passivation film 14.
アルミ電極パッド１３及びパッシベーション膜１４との
密着を得るためのＴｉ膜１５をスパッタリング法にて０
．１μｍ、拡散バ■ノアとしてのＴａ膜１６をスパッタ
リング法にて０．１μｍ、保護層としてのＡＬＩ膜１７
をスパッリングにて０．１μｍ形成する。A Ti film 15 is deposited by sputtering to obtain close contact with the aluminum electrode pad 13 and the passivation film 14.
．． A Ta film 16 as a diffusion bar with a thickness of 0.1 μm was formed by sputtering, and an ALI film 17 as a protective layer.
is formed by sputtering to a thickness of 0.1 μm.
次に、２０μｍ以上の膜厚のフォトレジストパターンを
用いて、メッキ部１８を電解メッキ法により２０μｍ厚
になるように形成する。Next, using a photoresist pattern with a film thickness of 20 μm or more, the plated portion 18 is formed to have a thickness of 20 μm by electrolytic plating.
次に、メッキ部Ｘ８をマスクとして、Ａｕ１ｉ１７、Ｔ
ａ膜１６、Ｔｉ膜１５をイオンミーリング法を用いてエ
ツチングすると、第１図のような電極用金バンブを得る
ことができる。Next, using the plated part X8 as a mask, Au1i17, T
When the a film 16 and the Ti film 15 are etched using an ion milling method, a gold bump for an electrode as shown in FIG. 1 can be obtained.
［発明の効果］
本発明は、・半導体装置の電極用金バンプにおいて、密
着層としてＴｉ膜、拡散バリア層としてＴａ膜、保護層
としてＡｕ膜を用いることにより、高湿度雰囲気で使用
しても６膜が腐食せず、高い信頼性の金バンブを得るこ
とができた。さらに、使用電圧も従来より高く、より有
用で使用性の高い金バンブを得ることができた。[Effects of the Invention] The present invention provides gold bumps for electrodes of semiconductor devices that can be used in a high humidity atmosphere by using a Ti film as an adhesion layer, a Ta film as a diffusion barrier layer, and an Au film as a protective layer. 6 film was not corroded and a highly reliable gold bump could be obtained. Furthermore, the working voltage was higher than before, making it possible to obtain gold bumps that were more useful and had higher usability.
第１図は、本発明の実施例によるバンプ形電極の断面図
。
第２図は、従来のバンプ形電極の断面図。
シリコン基板
シリコン酸化膜
アルミ電極パッド
パッシベーション膜
Ｔｉ膜
Ｃｕ膜
Ａｕ膜
Ａｕメッキ部
シリコン基板
シリコン酸化膜
アルミ電極パッド
パッシベーション膜
Ｃｒ膜
Ｔａ膜
Ａｕｙ。
Ａｕメッキ部
以上FIG. 1 is a sectional view of a bump-shaped electrode according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of a conventional bump-shaped electrode. Silicon substrate Silicon oxide film Aluminum electrode pad passivation film Ti film Cu film Au film Au plating part Silicon substrate Silicon oxide film Aluminum electrode pad passivation film Cr film Ta film Auy. Above the Au plated part
Claims (1)
び配線の上に、密着層としてのＴｉ膜、拡散バリア層と
してのＴａ膜、メッキ下地層であるＡｕ膜、及び電解メ
ッキによる金バンプにより構成される電極が形成されて
成ることを特徴とする半導体装置。A Ti film as an adhesion layer, a Ta film as a diffusion barrier layer, an Au film as a plating base layer, and gold bumps by electrolytic plating are placed on the insulating film and wiring of the integrated circuit in which the diffusion, insulating film, and wiring have been formed. 1. A semiconductor device comprising an electrode formed of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1180743A JPH0344934A (en) | 1989-07-13 | 1989-07-13 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1180743A JPH0344934A (en) | 1989-07-13 | 1989-07-13 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0344934A true JPH0344934A (en) | 1991-02-26 |
Family
ID=16088538
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1180743A Pending JPH0344934A (en) | 1989-07-13 | 1989-07-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0344934A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0586890A2 (en) * | 1992-08-31 | 1994-03-16 | International Business Machines Corporation | Etching processes for avoiding edge stress in semiconductor chip solder bumps |
| KR20020069769A (en) * | 2001-02-27 | 2002-09-05 | 설동수 | Saving Water Comparator |
-
1989
- 1989-07-13 JP JP1180743A patent/JPH0344934A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0586890A2 (en) * | 1992-08-31 | 1994-03-16 | International Business Machines Corporation | Etching processes for avoiding edge stress in semiconductor chip solder bumps |
| EP0586890A3 (en) * | 1992-08-31 | 1994-06-08 | Ibm | Etching processes for avoiding edge stress in semiconductor chip solder bumps |
| KR20020069769A (en) * | 2001-02-27 | 2002-09-05 | 설동수 | Saving Water Comparator |
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