JPH033517A - Clock generator - Google Patents

Abstract

PURPOSE:To stabilize fluctuation of a power voltage or ambient temperature and to eliminate the need for a period acquisition time till a clock is generated by storing in advance a switching pattern of a frequency division number of a variable frequency divider in response to an output clock of a desired frequency, and controlling the frequency division number of the variable frequency divider in response to the switching pattern. CONSTITUTION:A variable frequency divider 13 divides the frequency of a system clock from an input terminal 11 by one-optional integral number, and outputs the resulting clock from a terminal 12. Then a frequency division controller 14 stores in advance a data optimizing the switching pattern and the frequency division number of the variable frequency divider 13 and controls the variable frequency divider 13 so as to generate the clock with a mean frequency resulting from frequency division of M/N to the system clock from the input terminal 11. Thus, the circuit consists of a digital circuit. Then the circuit is stable against the fluctuation of power voltage and ambient temperature and the clock generator not requiring the period acquisition time till the clock is generated is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a clock generator used in digital logic circuits and the like.

Prior Art FIG. 5 shows the configuration of a conventional clock generator.

In FIG. 5, 23 is a frequency divider that divides the system clock from the input terminal 21 into 1/M (M is an integer);
25 is a phase comparator that compares the phases of the signal from the frequency divider 23 and the signal from the frequency divider 27 and outputs a signal according to the phase difference, and 25 converts the phase difference signal from the phase comparator 24 into a voltage. A low pass filter (LPF), 26, for converting into
It is a voltage controlled oscillator (VCO) that generates a clock with a frequency according to the voltage from the low-pass filter 25, and the frequency divider 27 divides the clock from the voltage controlled oscillator 26 by 1/N.
(N is an integer) and outputs it to the phase comparator 24.

That is, the clock generation device according to the above configuration uses an analog PLL (Phase Locked Loop).
A clock configured by a circuit, which is frequency-divided into M/H after acquiring synchronization with the system clock from the input terminal 21;
That is, it is possible to generate a clock that does not have an integer division relationship with the system clock and output it to the terminal 22.

Problems to be Solved by the Invention However, since the above-mentioned conventional clock generation device is configured with an analog PLL circuit, there is a problem in that the operation is unstable due to fluctuations in the power supply voltage and ambient temperature (especially the voltage controlled oscillator 26). Another problem is that it requires time to acquire synchronization before generating a clock.

In view of the above-mentioned conventional problems, an object of the present invention is to provide a clock generation device that is stable against fluctuations in power supply voltage and ambient temperature, and does not require synchronization acquisition time before generating a clock. do.

Means for Solving the Problems In order to achieve the above object, the present invention stores in advance a switching pattern of the frequency division number of a variable frequency divider according to an output clock of a desired frequency, and changes the frequency division number according to this switching pattern. The frequency division number of the frequency divider is controlled.

Effect of the Invention With the above configuration, the present invention has an integer number of divisions in the variable frequency divider, but the division number changes depending on the switching pattern, and therefore outputs a clock with an average frequency that is not in an integer relationship with the input clock. I can do it.

Furthermore, since the circuit described above can be configured as a digital circuit, it is stable against fluctuations in power supply voltage and ambient temperature, and does not require synchronization acquisition time until clock generation.

EXAMPLES Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a clock generator according to the present invention, FIG. 2 is a block diagram showing a detailed configuration of the frequency division controller shown in FIG. 1, and FIG. FIG. 4 is an explanatory diagram showing a table of the branch controller of FIG. 2. FIG.

In FIG. 1, 13 is a variable frequency divider that divides the system clock from the input terminal 11 by an arbitrary integer and outputs the clock through the terminal 12, and 14 is the variable frequency divider 13. The variable frequency divider stores data optimizing the frequency division number and switching pattern in advance, and generates a clock with an average frequency by dividing the system clock from the input terminal 11 by M/N, as described later. This is a frequency division controller that controls 13 by i11.

As shown in FIG. 2, the frequency division controller 14 includes a state counting circuit 141 that counts the phase difference between the virtual clock and the output clock.
Based on the count value of the state counting circuit 141, a lead/lag state output circuit 142 outputs data indicating the lead/lag state of the phase of the virtual clock and the output clock; The frequency dividing number setting circuit 143 is provided to set the number of divisions (an integer) of the frequency converter 13.

Next, the operation of the above embodiment will be explained with reference to FIGS. 3 and 4.

Here, to explain the case where a clock with an average frequency of 600Hz is output by a system clock of 1000Hz, a temporary clock of 600Hz and a clock of 1000Hz
The phase relationship between the system clock and the output clock with an average frequency of 600 Hz is shown in FIG.

First, at the start, as shown in FIG. 3, the phases of the system clock and the output clock match, so the lead/lag state output circuit 142 outputs data "+" in state "1" as shown in FIG. write to the table.

Next, set the frequency division number of the variable frequency divider 13 to the frequency division number '5/3.
When set to an integer “2” closer to J, the variable frequency divider 13
divides the system clock of 1000)lz with the frequency division number "2" and outputs the clock of 50011z, so the third
As shown in the figure, the rise of the output clock is delayed at the next rise of the virtual clock, and the lead/lag state output circuit 142 stores data "-" in state "2" in a table as shown in FIG. Write.

Next, when the frequency division number of the variable frequency divider 13 is set to "1", the variable frequency divider 13 divides the 1000Hz system clock with the frequency division number "1" and outputs the 1000Hz clock. As shown in FIG. 3, the rise of the output clock is ahead of the next rise of the virtual clock, and the lead/lag state output circuit 142 outputs the data "+" in state "3" to the table as shown in FIG. write to.

Next, when the frequency division number of the variable frequency divider 13 is set to "2", the variable frequency divider 13 divides the 1000Hz system clock with the frequency division number "2" and outputs a 50011z clock. As shown in FIG. 3, at the next rising edge of the virtual clock, the phase matches that of the output clock, and the state returns to "1".

That is, as shown in Fig. 3, the time of three cycles of the 600Hz virtual clock is (1/600)x3=o,005 [sl, and 10
The time of 5 periods of the system clock of 00Hz is (1/1000)X5=0.005 [sl, and the output clock has 3 rising edges during the time of 5 periods of the system clock of 1000H2. Therefore, the average frequency is 1/(0,005/3)=
600 [Hzl].

Therefore, according to the above embodiment, when a clock with an average frequency of 600 Hz is output using a system clock of 100011z, if a table as shown in FIG. The count is counted up at the rising edge of the output clock, and the lead/lag state output circuit 142 determines the lead/lag in phase between the virtual clock and the output clock based on this table, and the frequency division number setting circuit 143 uses this data to set the variable frequency divider 13. Since the frequency division number is controlled, it is possible to generate a clock that has no integer relationship with the system clock.

In this case, the circuit configuration can be configured with a digital circuit without using an analog circuit such as a voltage controlled oscillator as in the conventional example, so it is stable against fluctuations in the power supply voltage and ambient temperature, and the clock does not require synchronization acquisition time to occur.

DETAILED DESCRIPTION OF THE INVENTION As described in detail, the present invention stores in advance a switching pattern of the frequency division number of a variable frequency divider according to an output clock of a desired frequency, and changes the frequency division of the variable frequency divider according to this switching pattern. Since the frequency is controlled, it can be configured with a digital circuit, and is therefore stable against fluctuations in power supply voltage and ambient temperature, and does not require time to acquire synchronization before generating a clock. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of an O-clock generator according to the present invention, FIG. 2 is a block diagram showing a detailed configuration of the frequency division controller shown in FIG. 1, and FIG. FIG. 1 is a timing chart showing the main signals of the clock generator; FIG. 4 is an explanatory diagram showing the table of the frequency division controller shown in FIG. 2;
The figure is a block diagram showing a conventional clock generation device. 13... Variable frequency divider, 14... Frequency division controller, 141
. . . State counting circuit, 142 . . . Lead/lag status output circuit, 143 . . . Variable frequency divider frequency division number setting circuit.

Claims (2)

[Claims] (1) A variable frequency divider that outputs a clock obtained by dividing an input clock by an integer frequency division number, and a pattern for switching the frequency division number of the variable frequency divider according to the output clock of a desired frequency is stored in advance. and means for controlling the frequency division number of the variable frequency divider according to the switching pattern. (2) The clock generation device according to claim 1, wherein the control means controls the frequency division number of the variable frequency divider at a rising edge of the output clock of the variable frequency divider.