JPH0334433A - Manufacturing method of thin film transistor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a thin film transistor, and particularly to a method for manufacturing a thin film transistor suitable for an active matrix type liquid crystal display.

[Conventional technology]

In recent years, as the demand for larger screens and higher definition for active matrix liquid crystal flat displays has increased, polycrystalline silicon (PolyCrystallineSilicon)
Thin Film Transistor using a thin film transistor (abbreviated as Po1y-S i )
The development of TFT (abbreviated as TFT) is actively progressing. TP required to improve display quality
The characteristics of T are that the off-state current is small and the current on/off ratio is large.

Figure 2 shows the conventional - Po1y -S used in the shell.
i This is a cross-sectional structure of TFT. Insulating substrate (glass) 1
Po1y-S i 2 is formed thereon, and a gate insulating film 6 is formed thereon. A gate electrode 7 is formed on this gate insulating film 6, and using this as a mask, P
By introducing an impurity into o1y-S i 2 and activating it, a source electrode 3 and a drain electrode 5, which are impurity regions, are formed. However, this structure of Po1y-8i
When a TFT is in the off state, that is, when a negative gate voltage is applied to an n-channel TPT, and when a positive gate voltage is applied to a p-channel TPT, the electric field due to the applied gate voltage and drain voltage increases. is concentrated at the drain junction 10. Therefore, carriers are generated through the track level in the grain boundaries near the drain junction, and a large leakage current flows as the gate voltage and drain voltage increase, resulting in a large off-state current and a small on/off ratio. There was a problem.

Therefore, as described in Japanese Unexamined Patent Publication No. 63-204769, in order to alleviate the electric field concentrated near the drain junction, L D D [J (Light
TPT using tly-Doped Drain was considered. Figure 3 shows Po1y-S using LDD structure.
This is a cross-sectional structure of 1 TFT. Insulating substrate 1 such as glass
Po1y-S i 2 and a gate insulating film 6 are laminated thereon.

Next, a gate electrode 7 is formed on the gate insulating film 6.

Using this as a mask, impurities are introduced at a low concentration to form a region 9 with a low impurity concentration in the Po1y-S i 2. Furthermore, a resist mask larger than the gate ff1ti7 is formed on the gate electrode 7, impurities are introduced, and the source ? i! A pole 3 and a drain electrode 5 are formed.

PolySi TFT with such a structure is
Since the impurity concentration near the drain junction is low, the electric field due to the gate electrode and drain voltage is dispersed, the electric field strength at the drain junction 10 is weakened, and leakage current can be reduced.

[Problem to be solved by the invention]

However, the above-mentioned conventional technology has a problem in that the process becomes complicated because the steps of photophotography and introduction of impurities are added in addition to the normal manufacturing steps.

Therefore, in the present invention, without complicating the process,
Providing a region with low impurity concentration at the drain junction reduces off-current and turns on.

Po1y-S 1T that can increase the off ratio
An object of the present invention is to provide a method for manufacturing FT.

[Means to solve the problem]

In order to achieve the above object, the present invention provides Po1y-8i
As an activation method after introducing impurities in the process of manufacturing a TFT, this method is characterized by diagonally irradiating laser light using the gate electrode as a mask.

[Effect]

When activating impurities, when laser irradiation is performed diagonally, the gate electrode acts as a mask and the laser light is not irradiated near the drain junction, forming a region where impurities are not activated. ,
The gate electrode is activated. As a result, the concentration of activated impurities in the drain junction can be lowered, and an LDD structure in the drain can be formed without complicating normal processes.

Moreover, Po1y-S i T formed according to the present invention
Since the FT has a region where impurities are not activated, the electric field due to the gate voltage and drain voltage is dispersed, the electric field strength at the drain junction is weakened, and the electric field is As a result, fewer carriers are generated, and leakage current can be reduced.

〔Example〕

An embodiment of the present invention will be described below. FIG. 1 shows the cross-sectional structure of the entire TPT using the present invention. First, the insulating substrate l
As a substrate, glass or quartz is used, and the substrate temperature is set to 58℃.
The temperature was maintained at 0°C, and the Po
1y-S i 2 is formed.

After passing this film through island photo and etching steps, 5iOzll for the gate insulating film 6 is formed by atmospheric pressure CVD.
Deposit 1500 I. Next, P for the gate electrode 7
Deposit o1y-S i g to 1500 Å. Gate electrode7. After photo-etching the gate insulating film 6, phosphorus is ion-implanted using the gate electrode 7 as a mask, and then XeCQ pulsed excimer laser light 8 with a wavelength of 308 nm is applied diagonally at 300 mJ/a to activate the impurity.
Irradiate from an angle of 45@ with an energy of lt, and the source electrode 3. Drain electrode5. A region 4 in which impurities are not activated is created. As a result, the LDD region can be formed with a thickness of 0.3 μm or more. In addition, Phospho Sil
iconglass + PSG for short) at 400℃ for 5
000λ is deposited. After photolithography and etching processes for contact, AQ electrodes are sputtered to a thickness of 6000 Å.

FIG. 4 shows the above-mentioned Po1y-S i T F of the present invention.
FIG. 3 is a diagram showing measurement results of drain current dependence on gate voltage of a conventional Poly-8i TFT.

In this conventional Po1y-3i TFT, impurity activation is performed by vertically irradiating laser light. Measured T
The channel width and channel length of PT are 10 μm and 5 μm, respectively.
It is 0 μm. Comparing the characteristics of the present invention and the conventional technology, on,
The off-ratio has increased by more than ↓ orders of magnitude, and the off-state current has also decreased by one order of magnitude.

In the above example, the laser beam for impurity activation is 45°
However, this angle is not limited to 45 degrees as long as it can provide a region where impurities are not activated at the drain junction.

〔Effect of the invention〕

According to the present invention, since the electric field strength at the drain junction can be relaxed, leakage current of the thin film semiconductor device can be reduced. In addition, since the process is almost unchanged from the previous one,
Thin film transistors with better characteristics can be manufactured without changing costs.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of the schematic structure of an embodiment of the Po1y-5i TFT according to the present invention, and FIG. 2 is a cross-sectional view of the conventional Po1y-5i TFT.
Fig. 3 is a cross-sectional view of the schematic structure of a Si TFT, Fig. 3 is a cross-sectional view of the schematic structure of a Poly-8i TFT with a conventional LDD structure, and Fig. 4 is a cross-sectional view of the schematic structure of a Poly-8i TFT with a conventional LDD structure.
FIG. 3 is a diagram showing measurement results of drain current dependence on gate voltage of the Po1y-3i TFT of the present invention. l...Insulating substrate, 2...Polycrystalline silicon film, 3...
- Source electrode, 4...A region where impurities are not activated. 5...Drain electrode, 6...Gate insulating film, 7...
Gate electrode, 8... Laser light, 9... Low concentration impurity content 2 Figure 3 Figure 4- Figure +T = +- pressure (v)

Claims (1)

[Claims] 1. In the impurity activation step of an impurity region formed by introducing impurities into a polycrystalline silicon film formed on an insulating substrate, a laser beam is irradiated diagonally after forming a gate electrode. A method for manufacturing a thin film transistor, characterized by: 2. The method of manufacturing a thin film transistor according to claim 1, wherein the impurity region is a drain electrode. 3. A method of manufacturing a thin film transistor according to claim 2, characterized in that the laser beam is irradiated from the source electrode side, and a region where the laser beam is not irradiated is provided in a part of the drain electrode.