JPH03295295A - Formation of multilayer ceramic board via - Google Patents
Formation of multilayer ceramic board viaInfo
- Publication number
- JPH03295295A JPH03295295A JP9792890A JP9792890A JPH03295295A JP H03295295 A JPH03295295 A JP H03295295A JP 9792890 A JP9792890 A JP 9792890A JP 9792890 A JP9792890 A JP 9792890A JP H03295295 A JPH03295295 A JP H03295295A
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- copper powder
- filled
- small
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 title claims abstract description 34
- 230000015572 biosynthetic process Effects 0.000 title description 2
- 239000004020 conductor Substances 0.000 claims abstract description 52
- 239000002245 particle Substances 0.000 claims abstract description 47
- 238000000034 method Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims description 23
- 238000010304 firing Methods 0.000 claims description 3
- 238000010030 laminating Methods 0.000 claims description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 43
- 241001424392 Lucia limbaria Species 0.000 abstract 1
- 238000012856 packing Methods 0.000 description 11
- 238000005054 agglomeration Methods 0.000 description 3
- 230000002776 aggregation Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000000843 powder Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000011230 binding agent Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は多層セラミック基板のバイヤ形成方法に係り、
特に各層間の電気的接続を行うパイヤの接続性向上を図
りつる多層セラミック基板のバイヤ形成方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for forming vias in a multilayer ceramic substrate.
In particular, the present invention relates to a method for forming vias in a multilayer ceramic substrate, which improves the connectivity of the vias that make electrical connections between layers.
一般に、半導体素子を搭載する回路基板としてセラミッ
ク基板が広く用いられている。セラミック基板は耐熱性
、放熱性、電気特性2機械的強度等の面で良好な特性を
有している。このセラミック基板はグリーンシートを焼
成することにより製造される。Generally, ceramic substrates are widely used as circuit boards on which semiconductor elements are mounted. Ceramic substrates have good properties in terms of heat resistance, heat dissipation, electrical properties, mechanical strength, etc. This ceramic substrate is manufactured by firing a green sheet.
また昨今では、半導体素子の高集積化が急速に行われて
おり、これに対応するため導体パターンが形成された薄
いセラミック板を多層形成することにより導体パターン
の高密度化を図った多層セラミック基板が提供されてい
る。この多層セラミック基板では多層された各セラミッ
ク板間の電気的導通を図るためバイヤが形成されている
。このバイヤは、セラミック板に形成されたバイヤ孔(
セラミック板を上下に貫通する小径孔)に導体を充填し
た構造を有し、各セラミック板間の電気的導通を図る機
能を奏する。よって、バイヤが適正に形成されないと、
各層間の電気的導通が図れなくなりセラミック基板とし
て機能しなくなってしまう。In addition, in recent years, the integration of semiconductor devices has been rapidly increasing, and in response to this trend, multilayer ceramic substrates have been developed to increase the density of conductor patterns by forming multiple layers of thin ceramic plates on which conductor patterns are formed. is provided. In this multilayer ceramic substrate, vias are formed to provide electrical continuity between the multilayered ceramic plates. This via is a via hole (
It has a structure in which a conductor is filled in small diameter holes that penetrate the ceramic plates up and down, and functions to establish electrical continuity between each ceramic plate. Therefore, if the buyer is not formed properly,
Electrical conduction between each layer becomes impossible, and the ceramic substrate no longer functions.
そこで、高い信頼性を有するバイヤを形成し得るバイヤ
形成方法か望まれている。Therefore, a method for forming vias that can form vias with high reliability is desired.
第3図に従来におけるバイヤ(VIA)の形成方法を示
す。FIG. 3 shows a conventional method of forming a via.
従来バイヤを形成するには、先ず同図(A)に示すよう
にグリーンシート1にマスクフィルム2を配設し、続い
てこの上部よりパンチングによりグリーンシートl及び
マスクフィルム2を共に穿孔し、同図(B)に示すよう
にバイヤ孔3を形成する。Conventionally, in order to form a via, a mask film 2 is first placed on a green sheet 1 as shown in FIG. A via hole 3 is formed as shown in Figure (B).
バイヤ孔3が形成されると、同図(C)に示すようにス
キージ7を用いてバイヤ孔3に導体4を充填する。この
際、グリーンシート1の導体4の充填側と異なる面は負
圧とされており、導体4がバイヤ孔3内に充填され易い
よう構成されている。この導体4は銅粉とバインダとを
混合させたものであり、また銅粉の粒径はバイヤ孔3の
径寸法か50〜200μmに対して0.3〜10.0μ
m程度の物か選定されていた。このように、従来の導体
4は粒径の小さな、また一種類の粒径を有する銅粉から
のみ構成されていた。Once the via hole 3 is formed, the conductor 4 is filled into the via hole 3 using a squeegee 7, as shown in FIG. At this time, the side of the green sheet 1 that is different from the filling side of the conductor 4 is under negative pressure, and is configured to easily fill the via hole 3 with the conductor 4. This conductor 4 is a mixture of copper powder and a binder, and the particle size of the copper powder is 0.3 to 10.0 μm relative to the diameter of the via hole 3, which is 50 to 200 μm.
It was selected that the size was around m. In this way, the conventional conductor 4 was composed only of copper powder having a small particle size and having only one type of particle size.
上記のようにバイヤ孔3に導体4か充填されると、同図
(D)に示すようにグリーンシートlのマスクフィルム
2の配設面と異なる面にバイヤ孔3を塞ぐようにランド
5が形成され、続いて同図(E)に示すようにマスクフ
ィルム2をグリーンシート1から剥離させる。When the via hole 3 is filled with the conductor 4 as described above, a land 5 is formed on the surface of the green sheet l that is different from the surface on which the mask film 2 is disposed so as to close the via hole 3, as shown in FIG. The mask film 2 is then peeled off from the green sheet 1 as shown in FIG.
上記のようにバイヤ孔3に導体4が充填されたグリーン
シート1は同図(F)に示されるように積層された上で
焼成処理され、多層セラミック基板が形成される。尚、
同図(F’)には間隙8か発生する種々の態様を示す。The green sheets 1 in which the via holes 3 are filled with the conductors 4 as described above are stacked and fired as shown in FIG. 3(F) to form a multilayer ceramic substrate. still,
The figure (F') shows various ways in which the gap 8 is generated.
上記のように従来のバイヤ形成方法では、導体4として
粒径の小さな、また一種類の粒径のみの銅粉を用いてい
た。このように粒径か小さな粉体を細長いバイヤ孔3に
充填した場合、孔内における銅粉の流動性は悪く凝集が
発生し易くなり、第3図(D)に示すようにこの凝縮か
バイヤ孔3内に発生した場合には、バイヤ孔3内に間隙
8が形成され導体4の充填密度か低下してしまう。As described above, in the conventional via forming method, copper powder having a small particle size or having only one type of particle size is used as the conductor 4. When the elongated via hole 3 is filled with powder having a small particle size in this way, the fluidity of the copper powder in the hole is poor and agglomeration is likely to occur, and as shown in FIG. If it occurs in the hole 3, a gap 8 will be formed in the via hole 3, reducing the packing density of the conductor 4.
このように導体4の充填密度か低下すると、バイヤの電
気的導通性か劣化し、最悪の場合には電気的導通か取れ
なくなり、多層セラミック基板として機能しなくなると
いう課題かあった。If the packing density of the conductors 4 is reduced in this way, the electrical conductivity of the vias will deteriorate, and in the worst case, electrical continuity will not be established and the multilayer ceramic substrate will no longer function.
本発明は上記の点に鑑みてなされたものであり、導体の
充填密度の向上を図りうる多層セラミック基板のバイヤ
形成方法を提供することを目的とする。The present invention has been made in view of the above points, and it is an object of the present invention to provide a method for forming vias in a multilayer ceramic substrate that can improve the packing density of conductors.
上記課題を解決するために、本発明ては、グリーンシー
ト(1)に孔空は加工を行いバイヤ孔(3)を形成した
後、このバイヤ孔ぐ3)に導体(4)を充填し、続いて
このグリーンシ一ト(1)を複数枚積層して焼成するこ
とにより上記導体(4)をも焼成し各層間における電気
的導通を行うバイヤ(9)を形成する多層セラミック基
板のバイヤ形成方法において、
上記導体(4)として小粒径導体(10)と、大粒径導
体(11)との2種類用意し、小粒径導体 (10)を
上記バイヤ孔(3)に先ず充填した後に、大粒径導体(
11)を充填するようにしたことを特徴とするものであ
る。In order to solve the above-mentioned problems, the present invention processes holes in a green sheet (1) to form via holes (3), and then fills the via holes 3) with a conductor (4). Next, by laminating and firing a plurality of green sheets (1), the conductor (4) is also fired to form a via (9) for electrical continuity between each layer, forming a via of a multilayer ceramic substrate. In the method, two types of the conductor (4), a small-grain conductor (10) and a large-grain conductor (11), are prepared, and the small-grain conductor (10) is first filled into the via hole (3). Later, large-grain conductors (
11).
上記のバイヤ形成方法によれば、小粒径導体(10)を
バイヤ孔(3)に充填した後に、大粒径導体(11)を
バイヤ孔(3)に充填するため、小粒径導体(lO)の
充填時に凝集が発生し間隙か形成されたとしても、その
後に充填される大粒径導体(11)により小粒径導体(
10)は押し込まれるため、発生した間隙は押しつぶさ
れる。これにより、導体(4)の充填密度は向上しバイ
ヤ(9)の電気的導通性は良好となる。According to the above via forming method, after filling the via hole (3) with the small particle diameter conductor (10), the large particle diameter conductor (11) is filled into the via hole (3). Even if agglomeration occurs and gaps are formed during filling of the small particle conductor (11), the large particle conductor (11) filled afterwards will
10) is pushed in, so the gap that occurs is crushed. This improves the packing density of the conductor (4) and improves the electrical conductivity of the via (9).
次に本発明方法の一実施例について図面と共に説明する
。第1図は本発明の一実施例である多層セラミック基板
のバイヤ形成方法の工程図である。尚、同図(A)、(
B)、(E)〜(H)に示す工程は従来におけるバイヤ
の形成方法と全く同一である。このため、各図に示され
る工程は簡単に説明する。Next, an embodiment of the method of the present invention will be described with reference to the drawings. FIG. 1 is a process diagram of a method for forming vias in a multilayer ceramic substrate, which is an embodiment of the present invention. In addition, the same figure (A), (
The steps shown in B) and (E) to (H) are completely the same as the conventional via forming method. Therefore, the steps shown in each figure will be briefly explained.
バイヤを形成するには、先ずグリーンシート1にマスク
フィルム2を配設しく同図(A)に示す)、続いてこの
上部よりパンチングによりグリーンシート1及びマスク
フィルム2を共に穿孔してバイヤ孔3を形成する(同図
(B)に示す)。このバイヤ孔3の径寸法は50〜20
0μm程度とされている。To form a via, first place a mask film 2 on a green sheet 1 (as shown in FIG. (shown in Figure (B)). The diameter of this via hole 3 is 50 to 20
It is said to be about 0 μm.
バイヤ孔3か形成された後に行われる、同図(C)〜(
E)に示される工程は本発明方法の特徴となる工程であ
る。各図に示される工程はバイヤ孔3に導体4を充填す
る工程である。The steps (C) to (C) in the same figure are performed after the via hole 3 is formed.
The step shown in E) is a characteristic step of the method of the present invention. The process shown in each figure is the process of filling the via hole 3 with the conductor 4.
バイヤ孔3に導体4を充填するには、粒径の異なる二種
類の銅粉を用意する。この内、粒径の小さな銅粉10(
以下、小粒径銅粉という)は従来用いていた銅粉と同一
のものであり、その粒径は0.3〜10.0μm程度の
物が選定されている。また粒径の大きな銅粉11(以下
、大粒径銅粉という)は、その粒径か例えば70μmに
選定されている。この大粒径銅粉11の粒径は、少なく
とも小粒径銅粉10の粒径より大きく、かつバイヤ孔3
の径寸法よりは小さく選定する必要かある。 導体4を
バイヤ孔3に充填するには、同図(C)に示すように、
先ず小粒径銅粉lOをスキージ7を用いて充填する。こ
の際、小粒径銅粉lOは粒径か小さいため凝集か発生し
間隙8か発生する虞かあることは前述した通りである。To fill the via hole 3 with the conductor 4, two types of copper powder with different particle sizes are prepared. Of these, 10 copper powders with small particle size (
The copper powder (hereinafter referred to as small particle size copper powder) is the same as the conventionally used copper powder, and has a particle size of about 0.3 to 10.0 μm. Further, the particle size of the copper powder 11 having a large particle size (hereinafter referred to as large particle size copper powder) is selected to be, for example, 70 μm. The particle size of this large particle size copper powder 11 is at least larger than the particle size of the small particle size copper powder 10, and
Is it necessary to select a diameter smaller than that of the ? To fill the via hole 3 with the conductor 4, as shown in the same figure (C),
First, small particle size copper powder 1O is filled using a squeegee 7. At this time, as described above, since the small particle size copper powder 1O has a small particle size, there is a possibility that agglomeration may occur and the gap 8 may be generated.
小粒径銅粉lOがバイヤ孔3に充填されると、続いて同
図(D)に示すように大粒径銅粉11かバイヤ孔3に充
填される。大粒径銅粉11はその粒径か大きいため、小
粒径銅粉lOに比へてバイヤ孔3に入り難い。このため
、スキージ7による大粒径銅粉11の充填は小粒径銅粉
10の充填時に比べて強い充填力で行うと良い。When the via hole 3 is filled with the small particle size copper powder 10, the large particle size copper powder 11 is subsequently filled into the via hole 3 as shown in FIG. Since the large particle size copper powder 11 has a large particle size, it is difficult to enter the via hole 3 compared to the small particle size copper powder lO. For this reason, it is preferable that the large-particle copper powder 11 be filled with the squeegee 7 with a stronger filling force than when the small-particle copper powder 10 is filled.
上記のように、バイヤ孔3に小粒径銅粉lOか充填され
た後に、大粒径銅粉11を充填することにより、同図(
E)に示すように、小粒径銅粉IOは大粒径銅粉11に
押さえ込まれ間隙8は潰された状態となる。これにより
バイヤ孔3に対する導体4の充填密度は高くなり、これ
に伴いバイヤ9の電気的導通性は向上し、ひいては多層
セラミンク基板の信頼性を向上させることかできる。As described above, after the via holes 3 are filled with the small-particle copper powder 1O, by filling the large-particle copper powder 11, as shown in the figure (
As shown in E), the small particle size copper powder IO is pressed down by the large particle size copper powder 11, and the gap 8 is in a crushed state. This increases the packing density of the conductor 4 in the via hole 3, thereby improving the electrical conductivity of the via 9, and thus improving the reliability of the multilayer ceramic substrate.
第2図は本発明者が実験により求めた大粒径銅粉の径寸
法と導体の充填密度との関係を示している(同図では、
径寸法か90μmのバイヤ孔に対して行った実験結果を
示している)。同図に示されるように、バイヤ孔の径寸
法に対して大粒径銅粉の粒径か非常に小さい場合や同程
度の場合には、充填密度は低い。よって、大粒径銅粉1
1の粒径を選定するに際しては、バイヤ孔3の径寸法の
約半分の寸法か、或いはこれより若干大きな寸法に選定
することにより導体4の充填密度を向上させることがで
きる。Figure 2 shows the relationship between the diameter of large-particle copper powder and the packing density of the conductor, which the inventor found through experiments.
(Experimental results are shown for a via hole with a diameter of 90 μm.) As shown in the figure, when the particle size of the large-particle copper powder is very small or about the same as the diameter of the via hole, the packing density is low. Therefore, large particle diameter copper powder 1
When selecting the particle size of the conductor 1, the packing density of the conductor 4 can be improved by selecting the particle size to be approximately half the diameter of the via hole 3 or slightly larger than this.
上記のようにバイヤ孔3に導体4が充填されると、次に
グリーンシートIのマスクフィルム2の配設面と異なる
面にバイヤ孔3を塞ぐようにランド5が形成され(第1
図(F)に示す)、次にマスクフィルム2がグリーンシ
ートlから剥離される(同図(G)に示す)。続いて、
上記の如くバイヤ9が形成されたセラミック板12は同
図 (H)に示されるように、複数枚積層された上で焼
成処理が行われ、多層セラミック基板13か形成される
。When the via hole 3 is filled with the conductor 4 as described above, a land 5 is formed on a surface of the green sheet I that is different from the surface on which the mask film 2 is disposed so as to close the via hole 3 (first
(shown in Figure (F)), then the mask film 2 is peeled off from the green sheet 1 (as shown in Figure (G)). continue,
A plurality of the ceramic plates 12 on which the vias 9 are formed as described above are laminated and fired to form a multilayer ceramic substrate 13, as shown in FIG.
このセラミック板12か積層される際、セラミック板1
2に形成されたバイヤ9の導体4の充填密度は高いため
、隣接する各セラミック板12同士の電気的接続は確実
に行われ、多層セラミック基板13の信頼性を向上させ
ることかできる。When this ceramic plate 12 is laminated, the ceramic plate 1
Since the packing density of the conductors 4 in the vias 9 formed in the multilayer ceramic substrate 2 is high, the electrical connection between the adjacent ceramic plates 12 is ensured, and the reliability of the multilayer ceramic substrate 13 can be improved.
尚、上記した実施例では、導体として銅粉を充填する例
を挙げて説明したか、導体は銅粉に限るものではなく、
他の導電性金属の粉体を用いても良いことは勿論である
。Incidentally, in the above-mentioned embodiments, an example was given in which copper powder was filled as a conductor, but the conductor is not limited to copper powder.
Of course, powder of other conductive metals may also be used.
上述の如く、本発明によれば、導体の充填密度か向上す
るため、バイヤの電気的導通性は向上し、ひいては多層
セラミック基板の信頼性を向上させることができる等の
特長を有する。As described above, according to the present invention, since the packing density of the conductor is improved, the electrical conductivity of the via is improved, and the reliability of the multilayer ceramic substrate can be improved.
第1図は本発明の一実施例である多層セラミック基板の
バイヤ形成方法を形成工程順に説明するための工程図、
第2図は大粒径銅粉の径寸法と充填密度との関係を示す
図、
第3図は従来の多層セラミック基板のバイヤ形成方法の
一例を示す工程図である。
図において、
Iはグリーンシート、
3はバイヤ孔、
4は導体、
9はバイヤ、
10は小粒径銅粉、
11は大粒径銅粉、
12はセラミック板、
13は多層セラミック基板
を示す。Fig. 1 is a process diagram for explaining the via formation method for a multilayer ceramic substrate according to an embodiment of the present invention in the order of the forming steps, and Fig. 2 shows the relationship between the diameter dimension of large-particle copper powder and the packing density. FIG. 3 is a process diagram showing an example of a conventional method for forming vias in a multilayer ceramic substrate. In the figure, I is a green sheet, 3 is a via hole, 4 is a conductor, 9 is a via, 10 is a small particle diameter copper powder, 11 is a large particle diameter copper powder, 12 is a ceramic plate, and 13 is a multilayer ceramic substrate.
Claims (1)
)を形成した後、該バイヤ孔(3)に導体(4)を充填
し、続いて該グリーンシート(1)を複数枚積層して焼
成することにより該導体(4)をも焼成し各層間におけ
る電気的導通を行うバイヤ(9)を形成する多層セラミ
ック基板のバイヤ形成方法において、 該導体(4)として小粒径導体(10)と、大粒径導体
(11)との2種類用意し、該小粒径導体(10)を該
バイヤ孔(3)に先ず充填した後に、該大粒径導体(1
1)を充填することを特徴とする多層セラミック基板の
バイヤ形成方法。[Claims] The green sheet (1) is made with holes (3).
), the conductor (4) is filled into the via hole (3), and then the conductor (4) is also fired by laminating and firing a plurality of the green sheets (1), and the conductor (4) is also fired. In a method for forming vias of a multilayer ceramic substrate for forming vias (9) for electrical conduction, two types of conductors (4) are prepared: a small-grain conductor (10) and a large-grain conductor (11). , the via hole (3) is first filled with the small particle diameter conductor (10), and then the large particle diameter conductor (10) is filled into the via hole (3).
1) A method for forming vias in a multilayer ceramic substrate, characterized by filling the vias.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9792890A JPH03295295A (en) | 1990-04-13 | 1990-04-13 | Formation of multilayer ceramic board via |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9792890A JPH03295295A (en) | 1990-04-13 | 1990-04-13 | Formation of multilayer ceramic board via |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03295295A true JPH03295295A (en) | 1991-12-26 |
Family
ID=14205340
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9792890A Pending JPH03295295A (en) | 1990-04-13 | 1990-04-13 | Formation of multilayer ceramic board via |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03295295A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006310627A (en) * | 2005-04-28 | 2006-11-09 | Kyocer Slc Technologies Corp | Wiring board and its manufacturing method |
JP2011254098A (en) * | 2011-08-11 | 2011-12-15 | Kyocer Slc Technologies Corp | Wiring board |
-
1990
- 1990-04-13 JP JP9792890A patent/JPH03295295A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006310627A (en) * | 2005-04-28 | 2006-11-09 | Kyocer Slc Technologies Corp | Wiring board and its manufacturing method |
JP2011254098A (en) * | 2011-08-11 | 2011-12-15 | Kyocer Slc Technologies Corp | Wiring board |
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