JPH03259499A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To decrease time required for accessing to all memory transistors (TRs) more than that of normal readout by detecting whether or not all the memory TRs are erased at the erasure verify read mode. CONSTITUTION:Output data Da-Dc of sense amplifiers 8a-8c are given respectively to AND gates 21a-21c at the erasure verify read mode and outputs of the AND gates 21a-21c are given to inputs of an AND gate 23 and the output of the AND gate 23 is given to a write/read control circuit 24. Then the control circuit 24 detects simultaneously whether or not all 3-byte memory TRs (24 TRs) are set to be in the erasure state by detecting a level '1', '0' of the output of the AND gate 23. Thus, the time required for the access to all the memory TRs is decreased more than that of the usual read.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a non-volatile semiconductor memory device having a floating gate and an electrically programmable and erasable memory transistor.

[Conventional technology]

Figure 3 shows the conventional flash (-batch erase type) EEPRO.
It is a block diagram showing M. As shown in the figure, memory transistors 1 (only one is shown in the figure) arranged in a matrix in a memory array 10 are connected to bit lines 2 and 3, respectively.
and word line 3. One end of the bit line 2 is connected to a Y gate 4, and one end of the word line 3 is connected to an X decoder 5. The Y gate 4 is controlled on/off by the Y decoder 6 in units of 1 byte, which is the transfer data length of the human output buffer 9, during writing and reading, and
The activation/inactivation of is controlled by the X decoder 5 during writing and reading. The control by the X decoder 5 and Y decoder 6 described above is performed based on the address output of the address buffer 7. On the other hand, the Y gate 4 is also connected to a sense amplifier/write buffer 8 , and the sense amplifier/write buffer 8 is connected to a human output buffer 9 .

FIG. 4 is a sectional view showing the memory transistor shown in FIG. 3. In the figure, 11 is a P-type semiconductor substrate, 12 is an N-type drain diffusion region, and 13 is an N-type source diffusion region. These drain diffusion regions 12. The surface portion of P-type semiconductor substrate 11 between source diffusion regions 13 is defined as channel region 18 . A floating gate 14 is formed from a portion of the drain diffusion region 12 to a portion of the source diffusion region 13 via a gate oxide film 15 having a thickness that allows tunneling.

Furthermore, a control gate 16 is formed on the floating gate 14 via a gate oxide M17. Although not shown in FIG. 4, the bit line 2 is electrically connected to the drain diffusion region 12, and the word line 3 is electrically connected to the control gate 16.

In such a configuration, nonvolatile writing to the memory transistor 1 is performed as follows.

First, a high voltage is applied by a high voltage generating means (not shown) to the control gate 16 and drain diffusion region 12 of the memory transistor 1 connected to the word line 3 and bit line 2 selected by the X decoder 5 and Y decoder 6. , the source diffusion region 13 is set to ground level.

With this setting, electrons flowing through the channel region 18 of the memory transistor are accelerated by the voltage between the drain and the source in the pinch-off region near the drain diffusion region 12, and become hot electrons due to avalanche collapse. By injecting into the floating gate 14 across the energy gap of 15, the threshold of the memory transistor becomes high (above 7V).

On the other hand, erasing is performed on all memory transistors 1 in the memory array 10 by applying a high voltage to the source diffusion region 13 of the memory transistor 1 by high voltage generating means and setting the control gate 16 to the ground level. (drain region 12 may be floating). With this setting, a high electric field is applied to the gate oxide film 15 and the floating gate 1 is
As the electrons stored in the memory transistor 4 are extracted to the source diffusion region 13, the threshold value of the memory transistor becomes low (about IV). In other words, the state is the same as that of an EFROM erased by ultraviolet rays.

In this way, when a write operation is performed, memory transistor 1
The zero threshold value becomes 7V or more, and when the erase operation is performed, the threshold value of the memory transistor 1 becomes about 1V. On the other hand, reading
When a voltage of approximately the power supply voltage Vcc (5V) is applied to the control gate 16 by the activated word line 3, the memory transistor 1 is turned on and a current flows from the bit line 2 (that is, the drain diffusion region 12) to the source diffusion region 13. This is done by using the sense amplifier 8 to detect whether the current flows or whether the memory transistor 1 remains off and no current flows.

Note that the above writing, erasing, and reading are performed under the control of a write/read control circuit (not shown).

By the way, when the electrons accumulated in the floating gate are excited by ultraviolet rays and removed from the floating gate, as in ultraviolet erasing in EPROM, the emission of electrons ends when the floating gate becomes electrically neutral. On the other hand, in the case of a flash EEPROM that utilizes tunneling for erasing operation, if the erasing time is long, the electrons accumulated in the floating gate 14 may be extracted excessively and the floating gate 14 may become positively charged. . If the floating gate 14 is positively charged, the threshold voltage of the memory transistor 1 becomes negative. Such an over-erased memory transistor is always on, and a leak current flows through the over-erased memory transistor, making it impossible to read or write to the memory transistor that shares the bit line 2 with the over-erased memory transistor. .

Therefore, by shortening the width of the erase pulse that applies a high voltage to the source diffusion region 13, the data stored in all memory transistors 1 is read each time one erase pulse is applied, and all memory transistors 1 are brought into the erased state. Erase verification is executed one after another to check whether the data has been erased or not. Thereafter, the application of the erase pulse and the erase verify read are repeated, and once the erase state of all memory transistors 1 is confirmed by the erase verify read, the erase operation is immediately terminated. In this way, by applying the erase pulse and executing erase verify read, over-erased memory transistors are prevented from being generated.

[Problem to be solved by the invention]

As described above, in the conventional flash EEFROM, in order to prevent the occurrence of over-erased memory transistors, an erase verify read is always executed after applying an erase pulse during erasing.

However, like normal read operations, the erase verify read operation is an operation that sequentially reads data stored in memory transistors in units of the number of transferable bits of the human output buffer, so it takes a long time to detect the erased state of all memory transistors. It takes time. Therefore, there is a problem in that the erase operation using the erase verify read operation takes too much time.

This invention was made to solve the above-mentioned problems.
It is an object of the present invention to obtain an electrically writable and erasable nonvolatile semiconductor memory device that allows memory transistors to be erased all at once in a relatively short period of time.

[Means to solve the problem]

A nonvolatile semiconductor memory device according to the present invention includes a memory transistor having a floating gate and being electrically programmable and erasable, and during normal reading, data stored in the memory transistor is read out in units of a first predetermined number. Then, when performing erase verification one after another, by sequentially detecting the AND of the data stored in the memory transistors in units of a second predetermined number exceeding the first predetermined number, it is determined whether or not all the memory transistors are in the erased state. It is equipped with an erase verify read means for detecting.

[Effect]

The erase verify reading means in the present invention checks whether all memory transistors are in the erased state by sequentially detecting the AND of the memory data stored in the memory transistors in a second predetermined number of units larger than normal reading when performing erase verify sequentially. The time required to access all memory transistors is shorter than that required for normal reading.

〔Example〕

FIG. 1 shows a flash EEPR which is an embodiment of this invention.
FIG. 2 is a block diagram showing the configuration of OM. As shown in the figure, the memory arrays 10a to 10c are divided into three, and Y gates 4 are connected to each memory array 10a to 10c, respectively.
The on/off of a to 4c is selectively controlled by the Y decoder 6 in units of 1 byte, which is the number of data transfer bits of the output buffer 25. The control of the Y decoder 6 described above is performed based on the address output from the address buffer 7. That is, based on the address output from the address buffer 7, the Y decoder 6 controls on/off of the Y gates 4a to 4c in units of 3 bytes in total. Each Y gate 4a to 4c has a 1-byte long sense amplifier 8.
8 to 8c are connected, and these sense amplifiers 8a to 8c
Each output D −D is connected to the AND gate 21a~
21ca C and is also provided to the multiplexer 22.

Each output of the AND gates 21a to 21c is commonly AND
It becomes an input to the gate 23, and the output of the AND gate 23 is given to the write/read control circuit 24. On the other hand, the multiplexer 22 takes in a partial address ad which is a part of the output of the address buffer 7, and based on this partial address ad, only one output a C of the outputs D - D of the sense amplifiers 8a to 8C is sent to the output buffer 25. Output. Note that the X decoder 5 is the same as the conventional example shown in FIG. Also,
The configurations of the write buffer, input buffer, etc. used during writing are not shown because they are not related to the features of the invention.

In such a configuration, a normal read operation is performed as shown below. First, the X decoder 5 activates one word line (not shown) common to the memory arrays 10a to 10c, and the Y decoder 6 activates each of the Y gates 4a to 10c.
By turning on the gate of 1 byte (3 bytes in total) in each of sense amplifiers 4c, 1 byte of data is read to each of sense amplifiers 8a to 8C. Then, output data D-Da of each sense amplifier 8a to 8c
C is taken into multiplexer 22. multiplexer 2
2 outputs one of the data Da to Do to the output buffer 25 based on the partial address ad, and the output buffer 25 outputs it to the outside as read data D, thereby performing normal sequential output.

On the other hand, the erase verify read operation is as shown below.
It will be done. First, as in normal reading, the X decoder 5
, one word line is activated, and the Y decoder 6 turns on the gates for one byte in each of the Y gates 4 a to 4 c, so that the sense amplifiers 8 a to 8 are activated.
One byte of data is read to each of the bits c.

Then, output data Da- of each sense amplifier 8a to 8c
Do is given as the human power of the AND gates 21a to 21C, respectively, and the outputs of the AND gates 21a to 21c are given as the human power of the AND gate 23, and this AN
The output of D gate 23 is applied to write/read control circuit 24.

By the way, since information "1" is stored in the memory cell in the erased state, if all the memory transistors to be verified and read are in the erased state, the output data D a - D c will be (11111111)2, respectively. At this time, A
The output of each of the ND gates 21a to 21c is “1”
As a result, the output of the AND gate 23 also becomes "1".

On the other hand, if even 1 bit of data from a memory cell storing non-erased information '0' is read during erase verify reading, the output data D of the sense amplifiers 88 to 8c
Since at least one of a-Dc contains bit data of "0", AND gates 21a to 21
At least one output of c becomes "02", and the output of AND gate 23 becomes "0".

Therefore, at the time of erase verify reading, the write/read control circuit 24 outputs "1" from the AND gate 23.
, by detecting “0”, 3 bytes (24 pieces)
It is possible to simultaneously detect whether or not all of the memory transistors are set to the erased state. As a result, compared to the conventional method of performing erase verify read in 1-byte units,
Erase verify read can be performed at three times the execution speed,
Even if the erase operation is performed by repeating the application of a relatively short erase pulse and the erase verify read, the erase operation can be performed in a relatively short time.

FIG. 2 shows a flash EE which is another embodiment of the present invention.
FIG. 2 is a block diagram showing a PROM. As shown in the figure,
In addition to the configuration of the embodiment shown in FIG. 1, an address counter 26 and a selection circuit 27 for erase verification are newly provided. Then, the selection circuit 27 disables the address buffer 7 and enables the address counter 26 only during erase verify reading. Therefore, when erase verification is continued, X decoder 5 activates the word lines of memory arrays 10a to 10c based on the address output from address counter 26 rather than the address output from address buffer 7, and Y decoder 6 also Based on the address output from the counter 26, the gates of the Y gates 4a to 4c are controlled on/off in units of bytes.

The other configurations are the same as those of the embodiment shown in FIG. 1, so the explanation will be omitted. The operation is also the same as that of the embodiment shown in FIG. 1, except that the selection circuit 27 replaces the address output from the address buffer 7 with the address output from the address counter 26 during erase verify reading. The same effects as the embodiment shown in the figures are achieved.

In addition, by providing the address counter 26, the CPU (not shown) that accesses the flash EEFROM does not need to have an internal address counter for executing the erase verify sequence operation, thereby reducing the burden on the CPH. There is.

Note that even in the configuration of the embodiment shown in FIG. 1, since the output of the partial address ad to be output to the multiplexer 22 at the time of erase verify reading can be omitted, the CP is lower than that of the conventional configuration.
Since the number of count bits of the address counter for executing the erase verification continuous operation built in the U can be reduced, the CP
This has the effect of reducing the burden on U.

In this embodiment, a flash EEFROM is shown in which normal reading is performed in 1-byte units and erase-verify reading is performed in 3-byte units; however, the present invention is not limited to this. Erase-verifying reading is performed in bit units exceeding the number of bits normally read All you need is an EEPROM that can do this.

〔Effect of the invention〕

As described above, according to the present invention, the erase verify reading means sequentially detects the AND of the data stored in the memory transistors in the second predetermined number of units, which is larger than the normal read, when performing the erase verify sequentially. Since it is detected whether all memory transistors are in the erased state, the time required to access all memory transistors is shorter than normal reading.

As a result, even if the erase operation is performed by repeating the application of an erase pulse with a short pulse width and the above-mentioned erase verify read to avoid over-erasing, it is possible to erase the memory transistors all at once in a relatively short time. effective.

[Brief explanation of drawings]

FIG. 1 shows a flash EEPR which is an embodiment of this invention.
2 is a block diagram showing the structure of a flash EEPROM which is another embodiment of the present invention, FIG. 3 is a block diagram showing the structure of a conventional flash EEFROM, and FIG. 4 is a block diagram showing the structure of a flash EEPROM according to another embodiment of the present invention. FIG. 2 is a cross-sectional view showing the structure of a memory transistor of an EEFROM. In the figure, 4a to 4c are Y gates, 5 is an X decoder,
6 is a Y decoder, 8a to 8c are sense amplifiers, 21a
21c, 23 are AND gates, 24 is a write/read control circuit, and 25 is an output buffer. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) Equipped with a memory transistor that has a floating gate and is electrically programmable and erasable, and when normally read, the first
In a non-volatile semiconductor memory device in which data stored in the memory transistor is read out in units of a predetermined number, when erasure verification is performed successively, the logic of the data stored in the memory transistor is read out in units of a second predetermined number exceeding the first predetermined number. 1. A nonvolatile semiconductor memory device comprising erase verify reading means for detecting whether all memory transistors are in an erased state by sequentially detecting the product.