JPH03211880A - Forming method for schottky junction - Google Patents
Forming method for schottky junctionInfo
- Publication number
- JPH03211880A JPH03211880A JP772190A JP772190A JPH03211880A JP H03211880 A JPH03211880 A JP H03211880A JP 772190 A JP772190 A JP 772190A JP 772190 A JP772190 A JP 772190A JP H03211880 A JPH03211880 A JP H03211880A
- Authority
- JP
- Japan
- Prior art keywords
- metal
- metal layer
- schottky
- junction
- heat
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 38
- 239000002184 metal Substances 0.000 claims abstract description 38
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 20
- 230000004888 barrier function Effects 0.000 claims abstract description 17
- 150000004767 nitrides Chemical class 0.000 claims abstract description 6
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 20
- 238000010438 heat treatment Methods 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 4
- 238000010030 laminating Methods 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 239000007789 gas Substances 0.000 abstract description 6
- 238000009792 diffusion process Methods 0.000 abstract description 3
- 239000011261 inert gas Substances 0.000 abstract description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 6
- 230000007423 decrease Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 241000238557 Decapoda Species 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- -1 TaN Chemical class 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010406 interfacial reaction Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
(産業上の利用分野)
本発明は半導体装置の製造における金属と砒化ガリウム
(GaAs)とのショットキー接合の形成方法に関する
。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for forming a Schottky junction between metal and gallium arsenide (GaAs) in the manufacture of semiconductor devices.
(従来の技術)
最近、 FETの高性能化、高信頼化を0指してGa
As、InP等のデバイス関連技術の研究、開発が活発
に進められている。それらのデバイス関連技術の一つに
良好なショットキー接合の形成技術がある。ショットキ
ー接合形成技術は特にGaAsデバイスの開発に関連し
て進められてきた。(Conventional technology) Recently, Ga
Research and development of device-related technologies such as As and InP are actively underway. One of these device-related technologies is a technique for forming a good Schottky junction. Schottky junction formation techniques have been advanced particularly in connection with the development of GaAs devices.
従来GaAsデバイス、例えばFETのショットキーゲ
ート電極金属として、その接合特性が良好なこと、加工
性、電気伝導性が良いこと、廉価なこと等の理由で、主
として八〇が使用されてきた。Conventionally, 80 has been mainly used as a Schottky gate electrode metal for GaAs devices, such as FETs, because of its good bonding properties, good processability, good electrical conductivity, and low cost.
しかし、最近のFETへの高性能化、高信頼化の要求に
伴って、AQ/GaAsショットキー接合において種々
の欠点が見出され、その接合特性の改良。However, with recent demands for higher performance and higher reliability for FETs, various drawbacks have been discovered in AQ/GaAs Schottky junctions, and improvements in the junction characteristics have been made.
改善が求められている。例えばAQは融点が660℃で
低く、反応性が強いため、200℃程度の比較的低温で
もAQ −GaAs間で反応が進行し、例えばAl2G
aAsの如き不安定な化合物が形成される。それによっ
てショットキーバリア高さφBが低下してリーク電流の
増加或いは整流性の良否の指標であるn値の増大等が起
きる。φBやn値の変化はFET特性におけるドレイン
飽和電流、順方向立ち上り電圧、ピンチオフ電圧等の変
動として現われる。Improvement is required. For example, AQ has a low melting point of 660°C and is highly reactive, so the reaction between AQ and GaAs proceeds even at a relatively low temperature of about 200°C, for example, Al2G
Unstable compounds such as aAs are formed. As a result, the Schottky barrier height φB decreases, resulting in an increase in leakage current or an increase in the n value, which is an indicator of the quality of rectification. Changes in φB and n value appear as changes in drain saturation current, forward rising voltage, pinch-off voltage, etc. in FET characteristics.
上記の欠点を改善するため種々の対策がとられている。Various measures have been taken to improve the above drawbacks.
例えば、Al2に替えてAQ/Tiを使用することが試
みられているが、この場合でもTiとGaAs間に反応
が起り、 FET特性の変動を避けることができない
。For example, attempts have been made to use AQ/Ti in place of Al2, but even in this case a reaction occurs between Ti and GaAs, and fluctuations in FET characteristics cannot be avoided.
発明者らはAQ / Ta / GaAs接合について
、その安定性について検討を行なったが、この接合にお
いても、TaとGaAs間の相互拡散その他によるφB
の変動を抑えることはできなかった。一般に金属と半導
体間の相互拡散はショットキーバリア劣化の要因と考え
られている。The inventors have investigated the stability of AQ/Ta/GaAs junctions, but even in this junction, φB due to interdiffusion between Ta and GaAs and other factors
It was not possible to suppress the fluctuations. Generally, interdiffusion between metal and semiconductor is considered to be a cause of Schottky barrier deterioration.
(発明が解決しようとする課題)
以上述べたように、Aρ/GaAsをはじめとする従来
のショットキー接合では一般に界面反応の進行のためシ
ョットキーバリア特性が劣化し易く、それに伴ってバリ
ア高さφBの低下やn値の増大が起こるというデバイス
適用上好ましがらざる欠点を持つ場合が多い。(Problems to be Solved by the Invention) As mentioned above, in conventional Schottky junctions such as Aρ/GaAs, the Schottky barrier properties tend to deteriorate due to the progress of interfacial reactions, and the barrier height increases accordingly. This often has drawbacks that are undesirable for device applications, such as a decrease in φB and an increase in the n value.
本発明は上記のような欠点を改良し、熱的に安定な特性
を示すショットキー接合の形成方法を提供することを目
的とする。An object of the present invention is to provide a method for forming a Schottky junction that improves the above-mentioned drawbacks and exhibits thermally stable characteristics.
(課題を解決するための手段)
本発明にかかるショットキー接合の形成方法は、砒化ガ
リウム基板の主面上にショットキーバリアを形成する耐
熱性の第1金属層、耐熱性金属の窒化物でなる中間金属
層、高導電性の第2金属層を順次積層し形成する工程と
、ついで非酸化性ガスの雰囲気中で500℃以上の熱処
理を施す工程を含むことを特徴とする。(Means for Solving the Problems) A method for forming a Schottky junction according to the present invention includes a heat-resistant first metal layer that forms a Schottky barrier on the main surface of a gallium arsenide substrate, and a heat-resistant metal nitride. The method is characterized by comprising a step of sequentially laminating and forming an intermediate metal layer and a highly conductive second metal layer, and then a step of performing heat treatment at 500° C. or higher in a non-oxidizing gas atmosphere.
(作 用)
本発明に依るショットキー接合ではショットキー金属が
、ショットキーバリアを形成する耐熱性金属例えばTa
から成る第1の金属層とその伝導性の良好な金属例えば
AQから成る第2の金属層との間に耐熱性金属の窒化物
例えばTaNから成る中間層で構成されている結果、T
aとGaAsとの相互拡散が界面のみに限定され、この
結果拡散が従来に比べて著しく抑制され、熱的に安定な
ショットキーバリアが実現されることになる。(Function) In the Schottky junction according to the present invention, the Schottky metal is a heat-resistant metal such as Ta that forms the Schottky barrier.
As a result, an intermediate layer made of a heat-resistant metal nitride, such as TaN, is formed between the first metal layer made of a highly conductive metal such as AQ, and the second metal layer made of a highly conductive metal such as AQ.
The interdiffusion between a and GaAs is limited only to the interface, and as a result, diffusion is significantly suppressed compared to the conventional method, and a thermally stable Schottky barrier is realized.
(実施例)
以下、本発明の一実施例につき図面を参照して説明する
。(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.
キャリア濃度2 X 10” tyi−3のn−GaA
s基体上にキャリア濃度が5 X 10”cm−” 、
厚さ0.5Iaのエピタキシャル層(以下エビ層と略記
)を成長させたGaAsウェハにHCR中で煮沸を施し
た後、水洗、乾燥を施す。前記GaAsウェハを蒸着装
置のペルジャー内に収容し、ペルジャー内背圧5 X
1O−7Torrで、電子ビーム法によってエビ層上に
Ta層を厚さ〜2000人形成する。次に、前記GaA
sウェハをDCスパッタ装置内に収容し5反応性スパッ
タ法で前記Ta層上にTaN層を層厚〜tooo人に形
成する。TaN層のスパッタ条件は、窒素とアルゴンと
の混合ガスを使用し、窒素ガス分圧/アルゴンガス分圧
!0.03゜全ガス圧〜3 X 10−”Torr、印
加直流電圧3にν、イオン電流−0,2■Aで施した0
次いで、前記TaN層上に一3000人のAQ層を背圧
I X 10”’Torrの下で抵抗加熱法で蒸着し、
ショットキー接合を形成した。n-GaA with carrier concentration 2 x 10” tyi-3
The carrier concentration on the s substrate is 5 x 10"cm-",
A GaAs wafer on which an epitaxial layer (hereinafter abbreviated as shrimp layer) with a thickness of 0.5 Ia was grown was boiled in HCR, washed with water, and dried. The GaAs wafer was housed in a Pelger of a vapor deposition device, and a back pressure inside the Pelger was set to 5×
A Ta layer with a thickness of ~2,000 layers is formed on the shrimp layer by an electron beam method at 10-7 Torr. Next, the GaA
The S wafer is housed in a DC sputtering apparatus, and a TaN layer is formed on the Ta layer to a thickness of 100 to 300 ml by a 5-reactive sputtering method. The sputtering conditions for the TaN layer are to use a mixed gas of nitrogen and argon, and the partial pressure of nitrogen gas/partial pressure of argon gas! 0.03゜ total gas pressure ~ 3 x 10-'' Torr, applied DC voltage 3 ν, ion current -0.2 ■A 0
Then, 13,000 AQ layers were deposited on the TaN layer using a resistance heating method under a back pressure of I x 10''Torr;
A Schottky junction was formed.
このようにして形成したショットキー接合を具備したG
aAsウェハを熱処理炉内に収容し、アルゴンガスの気
流中で、m度、時間をパラメータとして熱処理を施した
。G with Schottky junction formed in this way
The aAs wafer was housed in a heat treatment furnace and heat treated in an argon gas stream using m degrees and time as parameters.
第1図は上記方法で製作したAQ / TaN / T
a /GaAsショットキー接合の接合特性値(φB、
n)と熱処理温度との関係を示す図である。熱処理時間
は10分である。参考のため、 TaN層形成工程を除
いて、他は本発明の方法を同一の工程で製作した従来法
によるAll/ Ta層 GaAs接合の特性を示す、
第1図から判るように、本発明のAQ層 TaN層 T
a/GaAs接合のφBおよびn値は500〜600’
Cでの熱処理に対して夫々はとんど一定の値〜0.86
eVおよび−1,08を示し、しかもこのφBの値は熱
処理を施さない場合より〜0,03V増加している。φ
Bが増加することは接合のリーク電流の減少につながる
。このことは本発明のAQ/TaN/Ta/GaAs接
合が熱的に安定で、しかもリーク電流の低減に有効であ
ることを示している。これに対して、従来のAQ/Ta
/GaAs接合ではφBおよびn値とも熱処理温度が一
500℃以上の温度に対し変化しており安定とは言い難
い。本発明の効果はφB、 n値の熱処理時間依存性を
説明する第2図の結果からも明らかである。尚、第3図
に示すように、熱処理温度500℃以下例えば400℃
での熱処理では本発明による接合、従来の接合とも、
φBは時間と共に漸減しており、この温度での熱処理で
は接合の安定化は期待できないことを示している。Figure 1 shows AQ/TaN/T fabricated using the above method.
a /GaAs Schottky junction junction characteristic values (φB,
It is a figure showing the relationship between n) and heat treatment temperature. The heat treatment time is 10 minutes. For reference, the characteristics of an All/Ta layer GaAs junction manufactured using the conventional method using the same process as the present invention except for the TaN layer formation process are shown below.
As can be seen from FIG. 1, the AQ layer of the present invention, the TaN layer T
The φB and n values of the a/GaAs junction are 500-600'
For heat treatment at C, each has a nearly constant value ~0.86
eV and −1.08, and the value of φB is increased by ~0.03 V compared to the case without heat treatment. φ
An increase in B leads to a decrease in junction leakage current. This shows that the AQ/TaN/Ta/GaAs junction of the present invention is thermally stable and effective in reducing leakage current. In contrast, the conventional AQ/Ta
In the /GaAs junction, both the φB and n values vary with respect to temperatures of 1500° C. or higher, and cannot be said to be stable. The effects of the present invention are also clear from the results shown in FIG. 2, which explains the dependence of φB and n values on heat treatment time. As shown in Figure 3, the heat treatment temperature is 500°C or less, for example 400°C.
In the heat treatment, both the bonding according to the present invention and the conventional bonding,
φB gradually decreases with time, indicating that stabilization of the bond cannot be expected with heat treatment at this temperature.
なお、熱処理時間は10分程度が好ましく、それ以北に
なるとデバイス製造の他の工程に悪い影響を与える可能
性がある。また、あまりに短時間の場合は熱処理の効果
が有効に働かない。Note that the heat treatment time is preferably about 10 minutes; if the heat treatment time is longer than that, it may adversely affect other steps of device manufacturing. Furthermore, if the heat treatment is too short, the effect of heat treatment will not be effective.
また、実施例においては第1の金属層としてTa。Further, in the embodiment, Ta is used as the first metal layer.
第2の金属層としてAQ、中間層としてTaNの組合せ
について説明したが、第1の金属層として、■、Nb、
Mo、 Zr等、第2の金属層として、Au、 Ag
、 Cu等、中間層トシテ、WN、VN、 NbN、
ZrN等も使用した場合も同様の効果が期待できる。Although the combination of AQ as the second metal layer and TaN as the intermediate layer has been described, as the first metal layer,
Mo, Zr, etc., as the second metal layer, Au, Ag
, Cu, etc., intermediate layer, WN, VN, NbN,
Similar effects can be expected when ZrN or the like is also used.
以上述べたように本発明によれば、GaAs基板上に金
属を被着して金属/半導体ショットキー接合を形成する
にあたり、ショットキーバリアを形成する耐熱金属から
成る第1の金属層とその上に積層する第2の金属層との
間に耐熱金属の窒化物から成る電気伝導性の中間層を介
在させて構成し、前記ショットキー接合に不活性ガス中
で、500℃以上の温度で熱処理を施すことにより、前
記熱処理を施さない場合に較べて、熱的に安定で、がっ
、バリア高さが大きく、したがってリーク電流の小さな
ショットキー接合を形成できる。As described above, according to the present invention, when depositing metal on a GaAs substrate to form a metal/semiconductor Schottky junction, the first metal layer made of a heat-resistant metal forming a Schottky barrier and the An electrically conductive intermediate layer made of a heat-resistant metal nitride is interposed between the second metal layer laminated on the Schottky junction, and the Schottky junction is heat-treated at a temperature of 500°C or higher in an inert gas. By performing this, it is possible to form a Schottky junction that is thermally stable, has a large barrier height, and therefore has a small leakage current, compared to the case where the heat treatment is not performed.
第1図はショットキー接合について熱処理温度とバリア
高さ φBおよびn値の関係を示す線図、第2図はショ
ットキー接合について熱処理時間とバリア高さ φBお
よびn値の関係を示す線図、第3図はショットキー接合
の熱処理時間とバリア高さφBの関係を示す線図である
。
各回においてOは本発明、Xは従来例の各ショットキー
接合に係る。Figure 1 is a diagram showing the relationship between heat treatment temperature and barrier height φB and n value for Schottky junctions, Figure 2 is a diagram showing the relationship between heat treatment time, barrier height φB and n value for Schottky junctions, FIG. 3 is a diagram showing the relationship between Schottky junction heat treatment time and barrier height φB. In each case, O relates to the present invention and X relates to each Schottky junction of the conventional example.
Claims (1)
する耐熱性の第1金属層、耐熱性金属の窒化物でなる中
間金属層、高導電性の第2金属層を順次積層し形成する
工程と、ついで非酸化性ガスの雰囲気中で500℃以上
の熱処理を施す工程を含むショットキー接合の形成方法
。A step of sequentially laminating and forming a heat-resistant first metal layer forming a Schottky barrier, an intermediate metal layer made of a heat-resistant metal nitride, and a highly conductive second metal layer on the main surface of the gallium arsenide substrate; , and then heat treatment at 500° C. or higher in a non-oxidizing gas atmosphere.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP772190A JPH03211880A (en) | 1990-01-17 | 1990-01-17 | Forming method for schottky junction |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP772190A JPH03211880A (en) | 1990-01-17 | 1990-01-17 | Forming method for schottky junction |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03211880A true JPH03211880A (en) | 1991-09-17 |
Family
ID=11673591
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP772190A Pending JPH03211880A (en) | 1990-01-17 | 1990-01-17 | Forming method for schottky junction |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03211880A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0875924A2 (en) * | 1997-04-29 | 1998-11-04 | Applied Materials, Inc. | Improved tantalum-containing barrier layers for copper |
JP2006302999A (en) * | 2005-04-18 | 2006-11-02 | Mitsubishi Electric Corp | Semiconductor device |
-
1990
- 1990-01-17 JP JP772190A patent/JPH03211880A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0875924A2 (en) * | 1997-04-29 | 1998-11-04 | Applied Materials, Inc. | Improved tantalum-containing barrier layers for copper |
EP0875924A3 (en) * | 1997-04-29 | 2000-05-10 | Applied Materials, Inc. | Improved tantalum-containing barrier layers for copper |
JP2006302999A (en) * | 2005-04-18 | 2006-11-02 | Mitsubishi Electric Corp | Semiconductor device |
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