JPH03211739A - Junction type field effect transistor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain high transfer coefficient by providing a high concentration first conductivity type epitaxial semiconductor region connected to a second gate electrode on a second conductivity type epitaxial semiconductor layer and high concentration second conductivity type epitaxial semiconductor region connected to source, drain electrodes on a region for surrounding it and at both sides. CONSTITUTION:After an insulating film 2 is formed on a substrate 1, an n-type impurity-doped non-single crystalline silicon film 3, and a surface protective film 4 made of silicon oxide are formed. In this state, a laser beam 5 is emitted to convert the film 3 into a single crystalline silicon film 6. After the film 4 is removed, the film 6 is formed in a desired shape single crystalline silicon film 6'. Then a p-type impurity-doped single crystalline silicon film 7 is epitaxially grown only on the film 6'. On the film 7, an n-type region 8 and a high concentration p-type region 9, 10 are formed by ion implantation and the like. An p-type single crystalline silicon film 7 is partly etched until it arrives at the film 6', and high concentration n-type regions 11, 12 are formed partly on the film 6', n-type region 8.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application This invention relates to a junction field effect transistor. For more information, see S OI (Semiconductor
The present invention relates to a junction field effect transistor (J-FET) device using onInsulator technology.

(b) Conventional technology Conventionally, horizontal J-FETs formed on bulk substrates
As shown in the figure, a P-type region 44 forming a channel is provided on the surface of a single-crystal silicon substrate 43, and a source 46 is provided in this region.
The source II
Extreme 50. A drain electrode 5I and a gate electrode 52 are formed in openings formed by etching predetermined positions of the insulating layer 49, and the source 46, the drain 47, and the gate 45, respectively, are located in the high j@a'n type region 48 where ζ is -. Connected and fabricated. Horizontal JP E using Sol technology
As shown in FIG. 8, a P-type wheel crystal silicon film 55 is laminated on a substrate 53 on which an insulating layer 54 is grown, and a similar layer as described above is formed in and on this P-type wheel crystal silicon film 55. A device is formed and surrounded by an insulating film 56.

(c) Problems to be Solved by the Invention The above-mentioned prior art had the following problems. That is, in a horizontal J-PET formed on a bulk substrate, gates can be formed on the front and back sides by connecting the gate 1ii52 and the substrate 43 as shown in FIG. Since the junction area becomes larger, the junction capacitance and junction leakage will increase. On the other hand, S.O.
In a horizontal J-FET formed on one substrate, the junction between the channel region and the substrate can be eliminated, as shown in FIG. 8, but it can only be formed on the gate surface side, and a high transmission coefficient cannot be obtained.

This invention was made to solve the above problems, and its purpose is to provide a J-FE'r having a high transmission coefficient.

(d) Improving means for solving the problem According to the present invention, there is provided a first conductivity type single crystal semiconductor layer having an insulating layer underneath, and a narrow second conductivity type epitaxial semiconductor layer epitaxially laminated thereon. The first conductivity type single crystal semiconductor layer has a highly concentrated first conductivity type semiconductor region connected to an I gate electrode, and the second conductivity type epitaxial semiconductor layer has a high concentration first conductivity type semiconductor region connected to a second gate electrode. a highly doped epitaxial semiconductor region of a first conductivity type, a first conductivity type epitaxial semiconductor region surrounding the first conductivity type epitaxial semiconductor region, and a highly doped epitaxial semiconductor region of a second conductivity type connected to each of the source and drain electrodes on both sides of the first conductivity type epitaxial semiconductor region; A junction field effect transistor device is provided in which a first gate electrode and a second gate electrode are connected.

The junction field effect transistor device of the present invention includes a first conductivity type single crystal semiconductor layer, a first conductivity type single crystal semiconductor layer on which a first conductivity type single crystal semiconductor layer is formed, and a first conductivity type single crystal semiconductor layer. 111 type single crystal semiconductor layer: A layer for forming the first gate, for example silicon semiconductor single crystal, compound semiconductor (gallium arsenide, indium phosphide, etc.) single crystal on the insulator. It can also be formed by arranging and forming layers of these semiconductor mixtures. This first conductive type single crystal semiconductor layer is formed by forming a first conductive type T on the surface or on an insulating substrate, for example.
Although it can be formed by laminating type 4 non-single crystal semiconductors and performing a crystallization process, it is possible to form an oxide or nitride insulating layer by ion-implanting oxygen or nitrogen into the first conductivity type single crystal semiconductor substrate. A first layer is formed on this insulating layer.
The conductive type single crystal semiconductor layer may be left in place. As the substrate whose surface is insulating, for example, a semiconductor substrate having an insulating film on its surface, an insulating substrate, or the like can be used. A semiconductor substrate having an insulating film on its surface is an insulating film such as silicon oxide, silicon nitride, single crystal sapphire, single crystal magnesia spinel, or single crystal alkaline earth metal fluoride on the surface of a semiconductor substrate such as single crystal silicon. The insulating substrate can be manufactured by forming a film, for example, from single crystal sapphire, single crystal magnesia spinel, single crystal alkaline earth metal fluoride, or the like. The first conductivity type non-single crystal semiconductor is for forming a first conductivity type single crystal semiconductor layer, and the first conductivity type non-single crystal semiconductor layer is formed on the substrate.
For example, amorphous or polycrystalline materials such as silicon semiconductors, gallium arsenide semiconductors, indium phosphide semiconductors, and mixtures thereof can be stacked and used. This first conductivity type non-single crystal semiconductor can be converted into a first conductivity type single crystal semiconductor layer by crystallization treatment.

This crystallization process can be carried out in liquid phase or solid phase.

The crystallization treatment performed with a liquid can be performed by melting the first conductivity type non-single crystal semiconductor by irradiating it with an energy beam such as a laser beam or an electron beam, and then cooling it to form a single crystal.

The crystallization treatment performed in a solid phase can be performed by heating the first conductivity type non-single crystal semiconductor to a temperature below the melting point to cause solid phase growth and single crystallization. For the reproduction of this first conductivity type single semiconductor layer, it is usually suitable to have a thickness of 0.1 to 1 μm.

The second conductivity type epitaxial semiconductor layer is for forming a second gate, channel, source, and drain, and is formed on the first conductivity type single crystal semiconductor layer, such as a silicon semiconductor, a compound semiconductor ( (gallium arsenide, indium phosphide, etc.) and mixed semiconductors thereof, etc. can be formed by stacking them in an erectile manner. Also, this second
The conductivity type epitaxial semiconductor layer is narrowly disposed on the first conductivity type single crystal semiconductor layer except over the first gate electrode formation region, and for example, the conductivity type epitaxial semiconductor layer is arranged narrowly over the entire main surface of the first conductivity type single crystal semiconductor layer. The second conductivity type epitaxial semiconductor layer may be formed by etching the portion of the second conductivity type epitaxial semiconductor layer disposed on the region where the first gate electrode is intended to be formed after epitaxial growth of the second conductivity type semiconductor. In advance, in a region on the crystalline semiconductor layer where the first gate 1iti is intended to be formed,
For example, after forming a covering layer such as an insulating film, a second conductive type semiconductor may be formed by stacking the second conductive type semiconductor on the surface of the first conductive type single crystal semiconductor layer. The thickness of this second conductivity type epicyclic semiconductor is usually suitably 0.5 to 20 μm. The second gate may be manufactured by doping a first conductivity type impurity into a predetermined position of the second conductivity type epitaxial semiconductor layer to form a first conductivity type epitaxial semiconductor region. Also, this second gate (
A first conductivity type semiconductor region surrounded by a first conductivity type semiconductor region is formed by doping a first conductivity type impurity at a predetermined position in a first conductivity type semiconductor region. A contact area for two gate electrodes can be created.

The channel is a second gate of the second conductivity type epitaxial semiconductor layer (first conductivity type epitaxial semiconductor layer).
and the first gate (first conductivity type single crystal semiconductor layer). The above source and drain are
Preparing a second conductivity type epitaxial semiconductor region by doping a second conductivity type impurity to a high a concentration at predetermined positions on both sides of the second gate of the second conductivity type epitaxial semiconductor layer. I can do it.

In this invention, the first conductivity type solid semiconductor layer and the second
A first gate, a second gate, a source, and a drain electrode are formed by opening a predetermined position of the insulating film that rigidly bends the conductive epitaxial semiconductor layer, and forming the first gate I! A junction field effect transistor device can be manufactured by connecting the pot and the second gate II pole. This junction field effect transistor device can control the source-drain channel current using the first gate electrode and the second gate electrode.

(e) Since the junction between the lower gate and the channel, which is formed only on the bottom surface of the active element, suppresses an increase in unnecessary junction area, the gate can be formed on the front and back sides of the J-FET, and the junction capacitance and junction Reduce leakage and increase transmission coefficient.

(f) Example Embodiments of the present invention will be described below based on the drawings.

Embodiment 1 FIG. 1 shows a process diagram of a J-FET according to an embodiment of the second invention. As shown in FIG. 1(a), an insulating film 2 is formed on a substrate 1.
After forming, a non-single crystal silicon film 3 doped with an n-type impurity is formed to a thickness of 0.5 μm, and a surface protective film 4 made of silicon oxide is formed to a thickness of 0.2 μm.

In this state, as shown in FIG. 1(b), the laser beam 5
By irradiating and melting and recrystallizing non-single crystal silicon! I3 is converted into a single crystal silicon film 6. At this time, when performing single crystallization using the substrate 1 as a seed, a single crystal substrate is used as the substrate 1. Further, in a method using another seed crystal or without using a seed crystal, the substrate l does not have to be a single crystal. After removing the surface protective film 4, as shown in FIG. 1(c), six single-crystal silicon films are formed into a desired shape [6°] using a normal patterning process. Next, as shown in FIG. 1(d), a single crystal silicon film 7 doped with a p-type impurity is grown only on 6° of the single crystal silicon film using selective epitaxy.

As shown in FIG. 1(e), a nyM region 8 and a heavily doped p-type region 9.10 are formed on the main surface of this single crystal silicon film 7 by ion implantation or the like. Further, as shown in FIG. 1(r), a part of the p-type crystalline silicon film 7 is etched until it reaches 6° of the n-type crystalline silicon film, and a part of the n-type crystalline silicon film 6' exposed on the surface is etched. A highly concentrated n-type region It, 12 is formed in a part of the n-type region 8. Next, as shown in FIG. 1(g), after forming an insulator 13, a contact portion is opened and an aluminum film is formed and patterned to form a source electrode 14, a drain electrode 15, a lower gate electrode 16, and an upper gate electrode. 17. A junction field effect transistor device is manufactured by connecting the lower gate electrode I6 and the upper gate electrode 17, and using the n-type conductor crystal silicon film 6° and the n-type region 8 as the lower gate and the upper gate, respectively.

Example 2 FIG. 2 is a process diagram showing an embodiment of this invention.

First, in the same manner as in Example 1, a single crystal silicon film @6° is formed as shown in FIGS. 1(a) to (c), and then a single crystal silicon film @6° is formed as shown in FIG. An insulating film i8 is formed in a region where the lower gate is intended to be formed.3 Note that the same numbers are used for two locations f corresponding to those in FIG. Next, as shown in FIG. 2(b), monocrystalline silicon H19 doped with p-type impurities is grown by epitaxy only on the exposed portion of the monocrystalline silicon film 6° using the selective epitaxial method. This single crystal silicon film! 9 on the main surface
As shown in figure (c), an n-type region 20 and a high concentration p-type region 2
1.22 is formed by ion implantation or the like. Next, after removing the insulating film 18 covering a part of the n-type nested crystalline silicon film 6°, a part of the n-type nested crystalline silicon film 6° exposed on the surface is shown in FIG. 2(d). Then, a heavily doped n-type region 2324 is formed in a part of the n-type region 20 . Next, Figure 2(e)
After forming the insulation@25 as shown in FIG. 2, the contact portion is opened and an aluminum film is formed and patterned to form a source electrode 26, a drain electrode 27, a lower gate electrode 28,
This is referred to as an upper gate electrode 29. A junction field effect transistor device is manufactured by connecting the lower gate electrode 28 and the upper gate electrode 29, and using the n-type single crystal silicon film 6' and the n-type region 20 as the lower gate and upper gate, respectively.

Example 3 FIG. 3 is a process diagram showing another example of the present invention. n
Oxygen ions (or nitrogen ions) 31 are implanted at a high concentration into the mold wheel crystal silicon substrate 30, a silicon oxide film (or silicon nitride film) 32 is formed inside the single crystal silicon substrate 30, and a single crystal silicon film is formed on the surface. Leaving 33. The rest is the same as in Example 1 or 2, and J-FE is
Form a T.

Example 4 FIG. 4 is a process diagram showing another example of the present invention. After forming an insulating film 35 and a non-single crystal silicon film 36 doped with an n-type impurity to a thickness of 0.5 μm on a substrate 34,
A heat treatment is performed at 0 to 900° C. for a long time to form a single crystal silicon film 37 through solid phase growth. However, when the substrate 34 is used as a seed, a single crystal substrate is used as the substrate 34. The substrate 34 does not have to be a single crystal, either using a seed crystal or not using a seed crystal. The rest is shown in Figure 1 of Example 1 (
c) to (g) J-FET is formed as shown in FIG. 2 of Example 2.

Example 5 FIG. 5 is a process diagram showing an example of a pond according to the present invention. As shown in FIG. 5(a), a single crystal sapphire film (or magnesia spinel film or alkaline earth metal fluoride film) 39 is epitaxially grown on a single crystal silicon substrate 38 to a thickness of 0.5 μm. Next, as shown in FIG. 5(b), a single crystal silicon film 40 doped with n-type impurities
Epitaxially grow to a thickness of 0.5 μm. After that, a J-FET is formed as shown in FIGS. 1(c) to 1(g) of Example 1 or FIG. 2 of Example 2.

Example 6 FIG. 6 is an explanatory diagram showing another embodiment of the present invention.

On the sapphire substrate 11, an N-type impurity is doped to form an L single crystal silicon layer 42 with a thickness of 0.5 μm. After that, a J-FET is formed as shown in FIGS. 1(c) to 1(g) of Example 1 or FIG. 2 of Example 2. however,
Instead of the sapphire substrate, single crystal magnesia spinel or alkaline earth metal fluoride may be used as the substrate.

(G) Effects of the Invention According to the present invention, it is possible to provide a junction field effect transistor device having low junction capacitance and low junction leakage, and a high transmission coefficient, and a method for manufacturing the same.

[Brief explanation of drawings]

1 to 6 are explanatory diagrams of the manufacturing process of a junction field effect transistor device manufactured in an embodiment of the present invention, and FIGS. 7 to 8 are explanatory diagrams of a conventional junction field effect transistor. 1.34... Substrate, 2.18, 25.35... Insulating film, 3.36.
...N-type impurity doped f-co non-single crystal silicon film, 4...Surface protection film, 5...Energy beam, 6.6', 37, 40.42・・・・・・n
Type single crystal silicon film, 7.19...p type single crystal silicon film, 8.20...n type region, 9.10, 21.22...high concentration p-type chain region, 1
1j2, 23.24...High concentration n-type region, 13
...Insulating film, 14.26...Source electrode, 15.27...Drain electrode, 16.28
...Lower gate electrode. (a) Diagram noodles (a) (b) (C) Part (d) (e)

Claims (1)

[Claims] 1. An insulator, a first conductivity type single crystal semiconductor layer formed on the insulator, a narrow second conductivity type epitaxial semiconductor layer epitaxially laminated thereon, and comprising an insulating layer surrounding a semiconductor layer, having a high concentration first conductivity type semiconductor region connected to a first gate electrode in the first conductivity type single crystal semiconductor layer, and the second conductivity type epitaxial semiconductor layer. A highly doped epitaxial semiconductor region of the first conductivity type connected to the second gate electrode, an epitaxial semiconductor region of the first conductivity type surrounding this, and a highly doped second conductivity type epitaxial semiconductor region connected to the source and drain electrodes on both sides of the first conductivity type epitaxial semiconductor region. A junction field effect transistor device having an epitaxial semiconductor region and having a first gate and a second gate electrode connected. 2. The device according to claim 1, wherein the first conductivity type single crystal semiconductor layer and the second conductivity type epitaxial semiconductor layer are made of silicon single crystal. 3. The apparatus of claim 1, wherein said insulator is formed on a substrate and comprises either silicon oxide or silicon nitride. 4. The device of claim 1, wherein said insulator comprises one of single crystal sapphire, single crystal magnesia spinel, or single crystal alkaline earth metal fluoride. 5. A second conductivity type epitaxial semiconductor layer is epitaxially laminated on the first conductivity type single crystal semiconductor layer having an insulator below, and a highly concentrated first conductivity type semiconductor is formed on the exposed surface of the first conductivity type single crystal semiconductor layer. A first conductivity type epitaxial semiconductor region is formed in the second conductivity type epitaxial semiconductor layer, a highly doped first conductivity type epitaxial semiconductor region is formed therein, and a highly doped second conductivity type epitaxial semiconductor region is formed on both sides of the first conductivity type epitaxial semiconductor region. After covering the surface with an insulating layer, a predetermined region of the insulating layer is etched to form a high concentration first conductivity type semiconductor region of the first conductivity type single crystal semiconductor layer and a high concentration first conductivity of the second conductivity type epitaxial semiconductor layer. A contact region is opened in the type epitaxial semiconductor region and a pair of highly doped second conductivity type epitaxial semiconductor regions, and a first gate, a second gate,
A method for manufacturing a junction field effect transistor device, comprising forming source and drain electrodes and connecting a first gate electrode and a second gate electrode. 6. The first conductivity type single crystal semiconductor layer is converted into a single crystal semiconductor film by melting the non-single crystal semiconductor film by irradiating the non-single crystal semiconductor film with an energy beam, particularly a laser beam or an electron beam, and growing crystals in the liquid phase. 6. The method of claim 5, wherein the method is made by: 7. The method according to claim 5, wherein the first conductivity type single crystal semiconductor layer is produced by heating a non-single crystal semiconductor film to a temperature below its melting point to cause crystal growth in a solid phase and converting it into a single crystal semiconductor film. . 8. The method according to claim 5, wherein the insulator under the first conductivity type single crystal semiconductor layer is manufactured by forming silicon oxide or silicon nitride by ion-implanting oxygen or nitrogen ions into the silicon single crystal substrate. 9. The first conductivity type single crystal semiconductor layer is single crystal sapphire,
6. The method of claim 5, wherein the method is formed on an insulating substrate comprising either single crystal magnesia spinel or single crystal alkaline earth metal fluoride.