JPH03181119A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03181119A JPH03181119A JP32082289A JP32082289A JPH03181119A JP H03181119 A JPH03181119 A JP H03181119A JP 32082289 A JP32082289 A JP 32082289A JP 32082289 A JP32082289 A JP 32082289A JP H03181119 A JPH03181119 A JP H03181119A
- Authority
- JP
- Japan
- Prior art keywords
- film
- hydrogen
- thin film
- semiconductor device
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 41
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 71
- 239000001257 hydrogen Substances 0.000 claims abstract description 71
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 41
- 238000009792 diffusion process Methods 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 30
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 28
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 27
- 230000004888 barrier function Effects 0.000 claims abstract description 22
- 238000009826 distribution Methods 0.000 claims abstract description 16
- 238000002513 implantation Methods 0.000 claims abstract description 14
- 238000005468 ion implantation Methods 0.000 claims abstract description 9
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 9
- 239000010703 silicon Substances 0.000 claims abstract description 9
- 239000010409 thin film Substances 0.000 claims description 71
- 239000010408 film Substances 0.000 claims description 58
- 150000002431 hydrogen Chemical class 0.000 claims description 30
- 238000010438 heat treatment Methods 0.000 claims description 21
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims description 14
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 8
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 4
- 230000000694 effects Effects 0.000 abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 239000007789 gas Substances 0.000 abstract description 6
- 239000013078 crystal Substances 0.000 abstract description 5
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 43
- 239000011521 glass Substances 0.000 description 10
- 150000002500 ions Chemical class 0.000 description 10
- 230000007547 defect Effects 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 239000003513 alkali Substances 0.000 description 6
- 238000002161 passivation Methods 0.000 description 6
- 230000001133 acceleration Effects 0.000 description 5
- 239000002585 base Substances 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 4
- 239000000969 carrier Substances 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 229910000039 hydrogen halide Inorganic materials 0.000 description 2
- 239000012433 hydrogen halide Substances 0.000 description 2
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000011109 contamination Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は、絶縁基体上に形成した半導体装置の製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device formed on an insulating substrate.
[従来の技術]
従来、絶縁基板上の薄膜トランジスタ(以下TPTと称
す)は第6図に示すように、ガラスなどの絶縁基板61
上に、半導体薄膜62を形成し、そこに素子を作り込ん
で構成されていた。[Prior Art] Conventionally, a thin film transistor on an insulating substrate (hereinafter referred to as TPT) has an insulating substrate 61 made of glass or the like, as shown in FIG.
A semiconductor thin film 62 was formed thereon, and elements were built therein.
また、近年、TPTの特性向上のため、半導体薄膜とし
て、結晶性半導体薄膜を用いることがよく見られる。こ
こで言う結晶性半導体とは、通常使用されている単結晶
ウェハーに比べると、欠陥が数多く存在している単結晶
半導体や、内部に1個以上の結晶粒界をもつ多結晶半導
体を言う。Furthermore, in recent years, crystalline semiconductor thin films are often used as semiconductor thin films in order to improve the characteristics of TPT. The term "crystalline semiconductor" as used herein refers to a single-crystal semiconductor that has more defects than a normally used single-crystal wafer, or a polycrystalline semiconductor that has one or more internal crystal grain boundaries.
[発明が解決しようとする課題]
しかしながら、上記従来例では、結晶性半導体薄膜62
と基板61との界面や結晶性半導体薄膜62とゲート絶
縁@63との界面に、数多くの界面準位66.64が存
在し、この界面準位の影響で、例えば、MOS F E
Tを形成した場合、チャネル部でキャリアが準位にトラ
ップされ、いわゆるバックチャネルを形威し、しきい値
電圧の変動や、o n / o f f比の低下など、
素子特性の劣化をもたらしていた。[Problems to be Solved by the Invention] However, in the above conventional example, the crystalline semiconductor thin film 62
A large number of interface states 66, 64 exist at the interface between the crystalline semiconductor thin film 62 and the gate insulator 63, and at the interface between the crystalline semiconductor thin film 62 and the gate insulation @63.
When a T is formed, carriers are trapped in the level in the channel part, forming a so-called back channel, causing fluctuations in threshold voltage, decrease in on/off ratio, etc.
This resulted in deterioration of device characteristics.
また、結晶性半導体薄膜として、多結晶シリコンを用い
ることがよく見られるが、多結晶シリコン内に存在する
結晶粒界には、数多くの界面準位65が存在し、これら
が、キャリアをトラップすることにより、チャネル部で
のキャリアの移動度を低下させる。Furthermore, although polycrystalline silicon is often used as a crystalline semiconductor thin film, there are many interface states 65 at the grain boundaries that exist in polycrystalline silicon, and these trap carriers. This reduces carrier mobility in the channel portion.
また、基板にガラスなどの安価な材料を用いると、基板
材料中に含まれるNa’″などのアルカリイオンがプロ
セス中の熱処理によって移動し、基板との界面やシリコ
ン薄膜中に可動イオンとした存在し、素子特性の劣化や
、信頼性に問題を生じさせていた。In addition, if an inexpensive material such as glass is used for the substrate, alkali ions such as Na''' contained in the substrate material will move during heat treatment during the process, and exist as mobile ions at the interface with the substrate or in the silicon thin film. However, this has caused problems with deterioration of device characteristics and reliability.
これらの問題にたいして、例えば、素子形成後、素子の
保護膜として、プラズマCVD法による窒化シリコン膜
による水素パッシベーションを用いて、シリコン薄膜内
の準位を減らし、移動度を高くすることが行なわれてき
た。また、アルカリイオン汚染防止のために、高純度石
英や無アルカリガラスなどを基板として用いる場合もあ
る。To solve these problems, for example, hydrogen passivation using a silicon nitride film by plasma CVD is used as a protective film for the device after the device is formed, thereby reducing the levels in the silicon thin film and increasing the mobility. Ta. Further, in order to prevent alkali ion contamination, high-purity quartz, alkali-free glass, or the like may be used as the substrate.
しかしながら、上記の方法によっても、基板との界面の
問題は、解決されていない。これは、水素パッシベーシ
ョン後の結晶性半導体薄膜中の水素濃度分布が、第7図
に示されるように、比較的結晶性半導体薄膜表面にピー
クを持つような分布となり、薄膜内部および、薄膜と下
地界面の準位をパッシベートするのに十分でないためで
ある。However, even with the above method, the problem of the interface with the substrate has not been solved. This is because the hydrogen concentration distribution in the crystalline semiconductor thin film after hydrogen passivation has a peak relatively on the surface of the crystalline semiconductor thin film, as shown in Figure 7, and the hydrogen concentration distribution in the thin film and the underlying layer. This is because it is not sufficient to passivate the levels at the interface.
また、高純度石英や無アルカリガラスなどの基板は、高
価で、大面積の基板に安価でTPTを形成するには問題
があった。Further, substrates made of high-purity quartz or alkali-free glass are expensive, and there is a problem in forming TPT on a large-area substrate at low cost.
[課題を解決するための手段]
本発明の半導体装置の製造方法は、絶縁基体上に、結晶
性半導体薄膜を形成して成る半導体装置の製造方法にお
いて、前記結晶性半導体薄膜の両面に、水素の拡散にた
いしてバリアとなる第1、第2の絶縁膜をそれぞれ形成
する工程と、前記半導体薄膜中に、膜厚方向に複数のピ
ークを有する濃度分布をもつように水素を導入する工程
と、その後熱処理を行なう工程とを含むことを特徴とす
る。[Means for Solving the Problems] A method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device comprising forming a crystalline semiconductor thin film on an insulating substrate. a step of forming first and second insulating films that act as barriers against the diffusion of hydrogen; a step of introducing hydrogen into the semiconductor thin film so as to have a concentration distribution having multiple peaks in the film thickness direction; The method is characterized by including a step of performing heat treatment.
[作用]
本発明では、水素を導入した結晶性半導体isシ蔀帆理
することにより、水素が蒲隔中を拡散し、結晶性半導体
薄膜と基板との界面に存在する界面準位が水素によって
トラップされ、界面準位の数を減らし、TFTなどの半
導体装置の電気特性を向上させることができる。[Function] In the present invention, hydrogen is diffused in the gap between the crystalline semiconductors into which hydrogen is introduced, and the interface states existing at the interface between the crystalline semiconductor thin film and the substrate are affected by the hydrogen. It is possible to reduce the number of trapped interface states and improve the electrical characteristics of semiconductor devices such as TFTs.
また、薄膜中定拡散した水素は、薄膜中の欠陥準位や、
結晶粒界の界面準位にトラップされることにより、TP
Tなどの半導体装置の電気特性を向上させることができ
る。In addition, the hydrogen that has diffused in the thin film is absorbed by the defect levels in the thin film,
By being trapped in the interface states of grain boundaries, TP
The electrical characteristics of semiconductor devices such as T can be improved.
また、水素の導入を、膜厚方向に複数のピークを有する
濃度分布をもつように行ない、例えば、1つは、結晶性
半導体薄膜表面に分布のピークが来るように導入し、1
つは、結晶性半導体薄膜下地界面にそのピークが来るよ
うに導入することにより、半導体薄膜全体をパッシベー
トすることが可能となり、上述の効果をさらに高めるこ
とができる。Further, hydrogen is introduced so as to have a concentration distribution having multiple peaks in the film thickness direction.For example, one is introduced so that the peak of the distribution is on the surface of the crystalline semiconductor thin film, and one is
First, by introducing the material so that its peak is at the interface between the base of the crystalline semiconductor thin film, it becomes possible to passivate the entire semiconductor thin film, and the above-mentioned effect can be further enhanced.
なお、水素の拡散にたいしてバリアとなる絶縁膜として
、窒化シリコン膜を基板と半導体isとの間に形成する
ことにより、ガラスなどの基板からのNaゝなどのアル
カリイオンに対するプロッキングの効果が生じ、信頼性
の向上ができる。Note that by forming a silicon nitride film between the substrate and the semiconductor as an insulating film that acts as a barrier against hydrogen diffusion, a blocking effect is produced against alkali ions such as Na from the substrate such as glass. Reliability can be improved.
また、半導体薄膜上下面に、水素の拡散にたいしてバリ
アとなる絶縁膜を形成することにより、薄膜中に拡散し
た水素のout−diffusionを防止し、上述の
効果をさらに安定して得ることができる。Further, by forming an insulating film that acts as a barrier against hydrogen diffusion on the upper and lower surfaces of the semiconductor thin film, out-diffusion of hydrogen diffused into the thin film can be prevented, and the above-mentioned effects can be obtained more stably.
[実施態様]
第1図は、本発明を特徴づける半導体装置の断面図であ
る。[Embodiment] FIG. 1 is a cross-sectional view of a semiconductor device that characterizes the present invention.
本発明の第1の実施態様としては、まず、ガラス等の絶
縁基板ll上に、水素の拡散に対してバリアとなる第1
の絶縁膜として、例えば、プラズマCV D ?1や減
圧CVD法で、窒化シリコン膜12を形成する。In the first embodiment of the present invention, first, a first layer is placed on an insulating substrate such as glass, which serves as a barrier to hydrogen diffusion.
For example, as an insulating film of plasma CVD? A silicon nitride film 12 is formed by the method 1 or low pressure CVD method.
その後、結晶性シリコン薄膜13を形成する。Thereafter, a crystalline silicon thin film 13 is formed.
結晶性シリコン薄膜としては、減圧CVD法、プラズマ
CVD法により形成された多結晶シリコレや、非晶質シ
リコンをアニールし、再結晶化したものや、プラズマC
VD法において、成膜雰囲気中へのMCI等のハロゲン
化水素ガスの添加効果によってえられた大粒径多結晶シ
リコン(特願昭62−73630号)や、本出願人が特
願昭62−73629号で提案しているところの大粒径
多結晶シリコンや、本出願人が特開昭63−10701
6号で提案しているところの非晶質基板上に形成した単
結晶シリコンなどが用いられる。Crystalline silicon thin films include polycrystalline silicon formed by low pressure CVD or plasma CVD, amorphous silicon that is annealed and recrystallized, and plasma CVD.
In the VD method, large-grain polycrystalline silicon (Japanese Patent Application No. 1983-73630) obtained by adding hydrogen halide gas such as MCI to the film-forming atmosphere, and Large-grain polycrystalline silicon proposed in No. 73629, and
Single-crystal silicon formed on an amorphous substrate, as proposed in No. 6, is used.
次に、水素の拡散にたいしてバリアとなるような第2の
絶縁11j14を結晶性シリコン薄膜13上に形成する
。水素の拡散にたいしてバリアとなるような絶縁膜とし
ては、減圧CVD法で形成した窒化シリコン膜や、プラ
ズマCVD法で形成した窒化シリコン膜や窒化酸化シリ
コン膜を用いることができる。Next, a second insulator 11j14 that acts as a barrier against hydrogen diffusion is formed on the crystalline silicon thin film 13. As an insulating film that acts as a barrier against hydrogen diffusion, a silicon nitride film formed by a low pressure CVD method, a silicon nitride film or a silicon nitride oxide film formed by a plasma CVD method can be used.
次に、水素を、通常のイオン注入方法、或は、イオンシ
ャワー注入方法により、結晶性シリコン薄膜中に導入す
る(第1図15)。Next, hydrogen is introduced into the crystalline silicon thin film by a normal ion implantation method or an ion shower implantation method (FIG. 15).
これらの方法によれば、注入の加速電圧を適切な値に選
ぶことにより、注入領域のピークの深さを所望の値に選
ぶことができる。表1にLSS理論に基づく水素イオン
の加速電圧とシリコン中の注入飛程の関係を示す。According to these methods, by selecting an appropriate value for accelerating the implantation, the depth of the peak of the implanted region can be selected to a desired value. Table 1 shows the relationship between hydrogen ion acceleration voltage and implantation range in silicon based on the LSS theory.
表 1
水素イオンの注入飛程を、例えば、結晶性シリコン薄膜
表面近傍、結晶性シリコン薄膜下地界面近傍、結晶性シ
リコン薄膜中央近傍など、適当な位置にくるように加速
電圧を選んで、複数回に分けて注入を行なう。Table 1 The hydrogen ion implantation range was determined multiple times by selecting an accelerating voltage so that the implantation range was at an appropriate position, for example, near the surface of the crystalline silicon thin film, near the base interface of the crystalline silicon thin film, or near the center of the crystalline silicon thin film. The injection is divided into two parts.
これにより、シリコン薄膜中に分布する界面準位や、欠
陥準位にトラップされるのに十分な水素を導入すること
ができ、パッシベーション効果をより高めることができ
る。Thereby, sufficient hydrogen can be introduced to be trapped in the interface levels and defect levels distributed in the silicon thin film, and the passivation effect can be further enhanced.
第2図に、注入後の水素濃度分布を示す。低加速電圧、
高加速電圧による注入を適当に組み合わせることにより
、第2図16.17に示すように、結晶性シリコン薄膜
中の表面近傍、及び、下地界面近傍定分布をもつように
注入ができる。注入の加速電圧は、その濃度分布のピー
クが結晶性シリコン薄膜中に数多く存在するように、出
来るだけ細分化したほうが良いが、スルーブツトを考慮
すれば、2〜3種類程度の注入で十分その効果を示すこ
とが可能である。FIG. 2 shows the hydrogen concentration distribution after injection. low acceleration voltage,
By appropriately combining implantation with a high acceleration voltage, it is possible to implant with a constant distribution near the surface of the crystalline silicon thin film and near the base interface, as shown in FIG. 2, 16.17. The accelerating voltage for implantation should be divided as finely as possible so that there are many peaks in the concentration distribution in the crystalline silicon thin film, but if throughput is taken into account, two to three types of implantation are sufficient to achieve the desired effect. It is possible to show that
次に、N、、Ar%H2、あるいは、それらの混合ガス
の雰囲気下で、熱処理を行なう。Next, heat treatment is performed in an atmosphere of N, Ar%H2, or a mixed gas thereof.
第2図に、熱処理後の結晶性シリコン薄膜中の水素濃度
分布18を示す。熱処理により水素が結晶性シリコン薄
膜中を拡散し、再分布するが、そのとき、結晶性シリコ
ン薄膜上下面は、水素の拡散にたいしてバリアとなる第
1、第2の絶縁膜が形成されており、導入された水素は
、注入された絶対量が変化することなく、シリコン薄膜
13内でのみ拡散、再分布する。FIG. 2 shows the hydrogen concentration distribution 18 in the crystalline silicon thin film after heat treatment. Hydrogen diffuses and redistributes in the crystalline silicon thin film through heat treatment, but at this time, first and second insulating films are formed on the upper and lower surfaces of the crystalline silicon thin film to act as a barrier against hydrogen diffusion. The introduced hydrogen diffuses and redistributes only within the silicon thin film 13 without changing the absolute amount of hydrogen introduced.
さらに、薄膜中の水素は、拡散、再分布する過程におい
て、表面や下地界面に存在する界面準位や、結晶性シリ
コン薄膜中の欠陥準位や、結晶性シリコン薄膜の粒界に
存在する界面準位にトラップされ、下地界面でのバック
チャネルの発生を抑制し、かつ、粒界のポテンシャルを
小さくし、移動度を大きくする。In addition, during the process of diffusion and redistribution, hydrogen in the thin film forms interface states that exist at the surface and underlying interface, defect levels in the crystalline silicon thin film, and interfaces that exist at the grain boundaries of the crystalline silicon thin film. It is trapped in the level, suppresses the generation of back channels at the base interface, reduces the potential of grain boundaries, and increases mobility.
なお、熱処理の温度は、水素の拡散が起り始める300
℃より高く、結晶性シリコンに拡散した水素が再び外へ
拡散しない600℃よりも低い温度で行なえばよい。Note that the temperature of the heat treatment is 300°C, at which hydrogen diffusion begins to occur.
The temperature may be higher than 600° C. and lower than 600° C., at which hydrogen diffused into crystalline silicon will not diffuse out again.
また、基板と結晶性シリコン薄膜との間に窒化シリコン
膜を形成することで、基板からのNa’″等のアルカリ
イオンに対してブロッキングの効果を持たせ、信頼性が
向上する。Furthermore, by forming a silicon nitride film between the substrate and the crystalline silicon thin film, a blocking effect is imparted to alkali ions such as Na''' from the substrate, thereby improving reliability.
また、結晶性シリコン薄膜両面に、水素の拡散に対して
バリアとなる絶縁膜を形成することにより、熱処理によ
って水素が拡散する際、結晶性シリコン薄膜表面からの
外部拡散(out−diffusion)を防止でき、
水素によるパッシベーション効果をざらに高めることが
できる。In addition, by forming an insulating film on both sides of the crystalline silicon thin film that acts as a barrier against hydrogen diffusion, out-diffusion from the surface of the crystalline silicon thin film is prevented when hydrogen diffuses during heat treatment. I can do it,
The passivation effect of hydrogen can be roughly enhanced.
第3図に、本発明の第2の実施態様の概略を示す。FIG. 3 schematically shows a second embodiment of the invention.
本発明の第2の実施態様としては、まず、ガラス等の絶
縁基板11上に、水素の拡散にたいしてバリアとなる第
1の絶縁膜として、例えば、プラズマCVD法で、基板
温度200℃〜300℃で窒化シリコン膜12を形成す
る。この窒化シリコン膜12中には、数%〜数10%の
水素が含まれている。In the second embodiment of the present invention, first, a first insulating film that serves as a barrier against hydrogen diffusion is formed on an insulating substrate 11 made of glass or the like by, for example, plasma CVD, at a substrate temperature of 200° C. to 300° C. A silicon nitride film 12 is formed. This silicon nitride film 12 contains several percent to several tens of percent of hydrogen.
その後、窒化シリコン@12を形成した温度と同程度か
それ以下の温度で結晶性シリコン薄膜13を形成する。Thereafter, a crystalline silicon thin film 13 is formed at a temperature comparable to or lower than the temperature at which silicon nitride@12 was formed.
結晶性シリコン薄膜としては、減圧CVD法、プラズマ
CVD法により形成された多結晶シリコンや、我々の提
案しているプラズマCVD法において、成膜雰囲気中へ
のMCI等のハロゲン化水素ガスの添加効果によってえ
られた大粒径多結晶シリコンを用いることができる(特
願昭62−73630号)。プロセス温度の低温化およ
び電気特性上の観点から我々の提案している大粒径多結
晶シリコン薄膜が本実施例に最も適当である。Crystalline silicon thin films include polycrystalline silicon formed by low-pressure CVD and plasma CVD, and the effect of adding hydrogen halide gas such as MCI to the film-forming atmosphere in our proposed plasma CVD method. (Japanese Patent Application No. 73630/1982) can be used. The large-grain polycrystalline silicon thin film proposed by us is most suitable for this example from the viewpoint of lowering the process temperature and electrical properties.
次に、水素の拡散にたいしてバリアとなるような第2の
絶縁膜14を結晶性シリコン上に形成する。水素の拡散
にたいしてバリアとなるような絶縁膜としては、減圧C
VD法で形成した窒化シリコン膜や、第1の絶縁膜と同
様にして、プラズマCVD法で形成した窒化シリコン膜
や窒化酸化シリコン膜を用いることができる。Next, a second insulating film 14 that acts as a barrier against hydrogen diffusion is formed on the crystalline silicon. As an insulating film that acts as a barrier against hydrogen diffusion, low pressure C
A silicon nitride film formed by a VD method or a silicon nitride film or a silicon nitride oxide film formed by a plasma CVD method can be used in the same manner as the first insulating film.
次に、イオン注入方法、あるいは、イオンシャワー注入
方法を用いて、第2の絶縁膜を通して結晶性シリコン薄
膜中に水素を注入する(第1図15)、その際、例えば
、注入後の水素の濃度分布のピークが、第2の絶縁膜と
結晶性シリコン薄膜との界面に来るように注入時の加速
電圧を選択する。Next, using an ion implantation method or an ion shower implantation method, hydrogen is implanted into the crystalline silicon thin film through the second insulating film (FIG. 15). The acceleration voltage during implantation is selected so that the peak of the concentration distribution is at the interface between the second insulating film and the crystalline silicon thin film.
次に、N2.Ar、N2.あるいは、それらの混合ガス
の雰囲気下で、水素の拡散にたいしてバ+I=pL、+
、x笛+zntaf!L[ff1nd子l→relしS
/I+”’j〜)膜、を形成した温度より高い温度(3
00℃〜600℃)で熱処理を行なう。Next, N2. Ar, N2. Alternatively, in an atmosphere of these mixed gases, for hydrogen diffusion, +I = pL, +
, x whistle + zntaf! L [ff1nd child l → rel S
/I+"'j~) film, at a temperature higher than the temperature at which the film was formed (3
Heat treatment is performed at a temperature of 00°C to 600°C.
熱処理後の水素の濃度分布を第4図18に示す。The hydrogen concentration distribution after heat treatment is shown in FIG. 418.
この熱処理中に、窒化シリコン膜中に存在する水素が、
結晶性シリコン薄膜中に拡散することにより、特に、下
地界面に存在する界面準位や、さらには、結晶性シリコ
ン薄膜中の欠陥準位や、結晶性シリコンの粒界に存在す
る界面準位にトラップされ、また、イオン注入により導
入された水素が、特に、結晶性シリコン薄膜と第2の絶
縁膜との界面や、さらには、結晶性シリコン薄膜中の欠
陥単位や、結晶性シリコン薄膜中の粒界に存在する界面
準位にトラップされ、下地界面でのバックチャネルの発
生を抑制し、かつ、粒界のポテンシャルを小さくし、移
動度を大きくする。During this heat treatment, the hydrogen present in the silicon nitride film is
By diffusing into the crystalline silicon thin film, it particularly affects the interface states existing at the underlying interface, defect levels in the crystalline silicon thin film, and interface states existing at the grain boundaries of the crystalline silicon. Hydrogen that is trapped and introduced by ion implantation is trapped, especially at the interface between the crystalline silicon thin film and the second insulating film, and furthermore, at the defect units in the crystalline silicon thin film and the hydrogen introduced by ion implantation. It is trapped in the interface states existing at the grain boundaries, suppresses the generation of back channels at the underlying interface, reduces the potential at the grain boundaries, and increases mobility.
また、熱処理の温度は、水素の拡散が起り始める300
℃より高く、結晶性シリコンに拡散した水素が再び外へ
拡散しない600℃よりも低い温I ヅタ;六P ^
また、基板と結晶性シリコン薄膜との間に窒化シリコン
膜を形成することで、ガラスなどの基板からのNa“等
のアルカリイオンに対してブロッキングの効果を持たせ
、信頼性が向上する。In addition, the temperature of the heat treatment is 300°C, at which hydrogen diffusion begins to occur.
℃ and lower than 600℃ at which hydrogen diffused into crystalline silicon does not diffuse out again. It has a blocking effect against alkali ions such as Na'' from substrates such as glass, improving reliability.
また、結晶性シリコン薄膜両面に、水素の拡散に対して
バリアとなる絶縁膜を形成することにより、熱処理によ
って水素が拡散する際、結晶性シリコン薄膜表面からの
out−diffusionを防止でき、水素によるパ
ッシベーション効果をさらに高めることができる。In addition, by forming an insulating film that acts as a barrier against hydrogen diffusion on both sides of the crystalline silicon thin film, it is possible to prevent out-diffusion from the surface of the crystalline silicon thin film when hydrogen diffuses through heat treatment. The passivation effect can be further enhanced.
第3図に、本発明の第3の実施態様の概略を示す。FIG. 3 schematically shows a third embodiment of the invention.
本発明の第3の実施態様としては、まず、ガラス等の絶
縁基板11上に、水素の拡散にたいしてバリアとなる第
1の含む絶縁膜として、例えば、プラズマCVD法で、
基板温度200℃〜300℃で窒化シリコン膜12を形
成する。この窒化シリコン膜12中には、数%〜数10
%の水素が含まれている。As a third embodiment of the present invention, first, a first containing insulating film that serves as a barrier against hydrogen diffusion is formed on an insulating substrate 11 such as glass by, for example, a plasma CVD method.
A silicon nitride film 12 is formed at a substrate temperature of 200°C to 300°C. This silicon nitride film 12 contains several percent to several tens of
Contains % hydrogen.
その後、窒化シリコン膜12を形成した温度と同程度か
それ以下の温度で非晶質シリコン薄膜13を形成する。Thereafter, an amorphous silicon thin film 13 is formed at a temperature comparable to or lower than the temperature at which the silicon nitride film 12 was formed.
非晶質シリコン薄膜としては、減圧CVD法、プラズマ
CVD法により形成された非晶質シリコンや、多結晶シ
リコンにS、+をイオン注入して非晶質化したもの等が
用いられる。As the amorphous silicon thin film, amorphous silicon formed by low pressure CVD or plasma CVD, or polycrystalline silicon made amorphous by ion-implanting S and + is used.
次に、水素の拡散にたいしてバリアとなるような絶縁膜
14を非晶質シリコン上に形成する。水素の拡散にたい
してバリアとなるような絶縁膜としては、減圧CVD法
で形成した窒化シリコン膜や、第1の絶縁膜と同様にし
て、プラズマCVD法で形成した窒化シリコン膜や窒化
酸化シリコン膜を用いることができる。Next, an insulating film 14 that acts as a barrier against hydrogen diffusion is formed on the amorphous silicon. As an insulating film that acts as a barrier against hydrogen diffusion, a silicon nitride film formed by a low pressure CVD method, or a silicon nitride film or a silicon nitride oxide film formed by a plasma CVD method in the same way as the first insulating film is used. Can be used.
次に、イオン注入方法、あるいは、イオンシャワー注入
方法を用いて、第2の絶縁膜を通して結晶性シリコン薄
膜中に水素を注入する(第1図15)。その際、例えば
、注入後の水素の濃度分布のピークが、第2の絶縁膜と
結晶性シリコン薄膜との界面に来るように注入時の加速
電圧を選択する。Next, hydrogen is implanted into the crystalline silicon thin film through the second insulating film using an ion implantation method or an ion shower implantation method (FIG. 15). At this time, for example, the acceleration voltage at the time of implantation is selected so that the peak of the hydrogen concentration distribution after implantation is at the interface between the second insulating film and the crystalline silicon thin film.
次に、N2、Ar、N2 、あるいは、それらの温合ガ
スの雰囲気下で、水素を含む絶縁膜12、例えば、窒化
シリコン膜、を形成した温度より高い温度(300℃〜
600℃)で熱処理を行なう。Next, in an atmosphere of N2, Ar, N2, or a hot gas mixture thereof, the insulating film 12 containing hydrogen, for example, a silicon nitride film, is formed at a temperature higher than the temperature (300°C to 300°C).
600°C).
この熱処理の温度については、形成した非晶質シリコン
が、固相結晶成長し、結晶化する温度に設定することが
、より高性能なTPTを作るうえで望ましい。したがっ
て、上記熱処理の温度は、より望ましくは、500℃〜
600℃に設定することが、より高性能なTPTを作る
うえで望ましい。Regarding the temperature of this heat treatment, it is desirable to set the temperature at which the formed amorphous silicon undergoes solid phase crystal growth and crystallization, in order to produce a higher performance TPT. Therefore, the temperature of the heat treatment is more preferably 500°C to
It is desirable to set the temperature to 600°C in order to make a higher performance TPT.
熱処理後の水素の濃度分布を第4図18にボす。The hydrogen concentration distribution after heat treatment is shown in FIG. 418.
この熱処理中に、窒化シリコン膜中に存在する水素が、
結晶性シリコン薄膜中に拡散することにより、特に、下
地界面に存在する界面準位や、さらには、結晶性シリコ
ン薄膜中の欠陥準位や、結晶性シリコンの粒界に存在す
る界面準位にトラップされ、また、イオン注入により導
入された水素が、特に、結晶性シリコン薄膜と第2の絶
縁膜との界面や、さらには、結晶性シリコン薄膜中の欠
陥準位や、結晶性シリコン薄膜中の粒界に存在する界面
準位にトラップされ、下地界面でのバックチャネルの発
生を抑制し、かつ、粒界のポテンシャルを小さくし、移
動度を大きくする。During this heat treatment, the hydrogen present in the silicon nitride film is
By diffusing into the crystalline silicon thin film, it particularly affects the interface states existing at the underlying interface, defect levels in the crystalline silicon thin film, and interface states existing at the grain boundaries of the crystalline silicon. Hydrogen that is trapped and introduced by ion implantation is trapped, especially at the interface between the crystalline silicon thin film and the second insulating film, and furthermore, at the defect levels in the crystalline silicon thin film and at the interface between the crystalline silicon thin film and the second insulating film. is trapped by the interface states existing at the grain boundaries, suppressing the generation of back channels at the underlying interface, reducing the potential at the grain boundaries, and increasing mobility.
また、熱処理の温度は、水素の拡散が起り始める300
℃より高く、結晶性シリコンに拡散した水素が再び外へ
拡散しない600℃よりも低い温度で行なう。In addition, the temperature of the heat treatment is 300°C, at which hydrogen diffusion begins to occur.
The temperature is higher than 600° C. and lower than 600° C., at which hydrogen that has diffused into crystalline silicon does not diffuse out again.
また、基板と結晶性シリコン薄膜との間に窒化シリコン
膜を形成することで、ガラスなどの基板からのNa”等
のアルカリイオンに対してブロッキングの効果を持たせ
、信頼性が向上する。Further, by forming a silicon nitride film between the substrate and the crystalline silicon thin film, a blocking effect is provided to alkali ions such as Na'' from the substrate such as glass, and reliability is improved.
また、非晶質シリコン薄膜両面に水素の拡散にたいして
バリアとなる絶、i![を形成することにより、熱処理
によって水素が拡散する際、結晶性シリコン表面からの
out−diffusionを防止でき、水素によるパ
ッシベーション効果をさらに高めることができる。In addition, both sides of the amorphous silicon thin film act as a barrier to hydrogen diffusion, i! By forming [, when hydrogen is diffused by heat treatment, out-diffusion from the crystalline silicon surface can be prevented, and the passivation effect by hydrogen can be further enhanced.
第3図に、本発明の第4の実施態様の概略を示す。FIG. 3 schematically shows a fourth embodiment of the present invention.
本発明の第4の実施態様としては、まず、絶縁基板11
上に、水素の拡散にたいしてバリアとなる第1の絶縁膜
として、例えば、プラズマCVD法や減圧CVD法で、
窒化シリコン膜12を形成する。As the fourth embodiment of the present invention, first, the insulating substrate 11
As a first insulating film that acts as a barrier against hydrogen diffusion, for example, a plasma CVD method or a low pressure CVD method is applied to
A silicon nitride film 12 is formed.
その後、結晶性シリコン薄膜13を形成する。Thereafter, a crystalline silicon thin film 13 is formed.
Claims (7)
半導体装置の製造方法において、前記結晶性半導体薄膜
の両面に、水素の拡散にたいしてバリアとなる第1、第
2の絶縁膜をそれぞれ形成する工程と、前記半導体薄膜
中に、膜厚方向に複数のピークを有する濃度分布をもつ
ように水素を導入する工程と、その後熱処理を行なう工
程とを含むことを特徴とする半導体装置の製造方法。(1) In a method for manufacturing a semiconductor device in which a crystalline semiconductor thin film is formed on an insulating substrate, first and second insulating films are respectively provided on both sides of the crystalline semiconductor thin film to serve as a barrier against hydrogen diffusion. manufacturing a semiconductor device, comprising the steps of: forming a semiconductor thin film; introducing hydrogen into the semiconductor thin film so as to have a concentration distribution having a plurality of peaks in the film thickness direction; and then performing heat treatment. Method.
合わせによって成されることを特徴とする請求項1記載
の半導体装置の製造方法。(2) The method for manufacturing a semiconductor device according to claim 1, wherein the step of introducing hydrogen is performed by a combination of two or more types of methods.
とも1つが、イオン注入、或は、イオンシャワー注入方
法であることを特徴とする請求項2記載の半導体装置の
製造方法。(3) The method for manufacturing a semiconductor device according to claim 2, wherein at least one of the two or more types of hydrogen introduction methods is ion implantation or ion shower implantation.
、減圧CVD法、あるいは、プラズマCVD法で形成し
た窒化シリコン膜、あるいは、窒化酸化シリコン膜を用
いることを特徴とする請求項1乃至3記載の半導体装置
の製造方法。(4) A silicon nitride film formed by a low pressure CVD method or a plasma CVD method, or a silicon nitride oxide film is used as the insulating film serving as a barrier against hydrogen diffusion. A method for manufacturing a semiconductor device.
とを特徴とする請求項1乃至4記載の半導体装置の製造
方法。(5) The method of manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the crystalline semiconductor thin film material is silicon.
する温度であることを特徴とする請求項1乃至5記載の
半導体装置の製造方法。(6) The method of manufacturing a semiconductor device according to any one of claims 1 to 5, wherein the temperature of the heat treatment is a temperature at which amorphous silicon becomes polycrystalline.
ことを特徴とする請求項6記載の半導体装置の製造方法
。(7) The method of manufacturing a semiconductor device according to claim 6, wherein the temperature of the heat treatment is 300°C to 600°C.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32082289A JPH03181119A (en) | 1989-12-11 | 1989-12-11 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32082289A JPH03181119A (en) | 1989-12-11 | 1989-12-11 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03181119A true JPH03181119A (en) | 1991-08-07 |
Family
ID=18125623
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP32082289A Pending JPH03181119A (en) | 1989-12-11 | 1989-12-11 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03181119A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6534832B2 (en) | 1993-09-07 | 2003-03-18 | Semiconductor Energy Laboratory Co., Ltd. | Display device and glass member and substrate member having film comprising aluminum, nitrogen and oxygen |
US6709906B2 (en) | 1994-02-28 | 2004-03-23 | Semiconductor Energy Laboratory Co., Ltd. | Method for producing semiconductor device |
US7038302B2 (en) | 1993-10-12 | 2006-05-02 | Semiconductor Energy Laboratory Co., Ltd. | Glass substrate assembly, semiconductor device and method of heat-treating glass substrate |
-
1989
- 1989-12-11 JP JP32082289A patent/JPH03181119A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6534832B2 (en) | 1993-09-07 | 2003-03-18 | Semiconductor Energy Laboratory Co., Ltd. | Display device and glass member and substrate member having film comprising aluminum, nitrogen and oxygen |
US7038302B2 (en) | 1993-10-12 | 2006-05-02 | Semiconductor Energy Laboratory Co., Ltd. | Glass substrate assembly, semiconductor device and method of heat-treating glass substrate |
US6709906B2 (en) | 1994-02-28 | 2004-03-23 | Semiconductor Energy Laboratory Co., Ltd. | Method for producing semiconductor device |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2752799B2 (en) | Method for manufacturing SOI substrate | |
JPH08203842A (en) | Manufacture of semiconductor device | |
US7208360B2 (en) | Semiconductor device and method of manufacturing the same | |
US20010030333A1 (en) | Process of forming an ultra-shallow junction dopant layer having a peak concentration within a dielectric layer | |
JPS62130522A (en) | Manufacture of semiconductor device | |
US7345329B2 (en) | Method for reduced N+ diffusion in strained Si on SiGe substrate | |
US20050037596A1 (en) | Internal gettering in SIMOX SOI silicon substrates | |
US6326274B2 (en) | Method for improving performance and reliability of MOS technologies and data retention characteristics of flash memory cells | |
JPH0395939A (en) | Manufacture of semiconductor device | |
JPH03181119A (en) | Manufacture of semiconductor device | |
US5830802A (en) | Process for reducing halogen concentration in a material layer during semiconductor device fabrication | |
JPH0395938A (en) | Manufacture of semiconductor device | |
US20020068407A1 (en) | MOS transistor fabrication method | |
RU2235388C2 (en) | Method for manufacturing mis transistor with local sections of buried insulator | |
JP3578345B2 (en) | Semiconductor device manufacturing method and semiconductor device | |
US20020048917A1 (en) | Semiconductor device and method of fabricating same | |
KR101068135B1 (en) | Method for fabricating semiconductor device | |
JPH06283421A (en) | Soi substrate and manufacturing method thereof | |
JP3384439B2 (en) | Method for manufacturing semiconductor device | |
JPH06244203A (en) | Manufacture of thin film transistor | |
KR100724146B1 (en) | method for manufacturing a semiconductor device | |
JPH03185736A (en) | Manufacture of semiconductor device | |
KR20040037847A (en) | Method for fabricating semiconductor device | |
JPH04100238A (en) | Manufacture of semiconductor device | |
JPH03265131A (en) | Manufacture of semiconductor device |