JPH03170886A - Control circuit for test start interrupt signal from measuring table - Google Patents

Abstract

PURPOSE:To execute the test of respective measuring tables in the order of the interruption signals from the measuring tables by setting the data of the multitest mode from a CPU to FF input and setting FF output to the lower rank address of an ROM and encoding the test start interruption signal of each of the measuring tables to set the higher rank address of the ROM. CONSTITUTION:An FF 2 inputs the data of the multitest mode from a CPU 1 and an encoder 3 encodes the test start interruption signals of measuring tables 11 - 13. An ROM 4 sets the output data of the FF 2 to the input of a lower rank address and the output of the encoder 3 is set to the input of a higher rank address and the output of the ROM 4 is sent to the CPU 1 as the test start interruption signals of the measuring tables 11 - 13. That is, when the test start interruption signal 12A is issued from the measuring table 12 during the test of the measuring table 11, the measuring table 12 becomes a standby state until the test of the measuring table 11 is completed and the interruption signal 12A is stored in the CPU 1. Further, when the test start interruption signal 13A is issued from the measuring table 13, the measuring table 13 also becomes a standby state and a test is executed in a measuring table unit in interruption applied order.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an IC tester that tests an IC using one IC tester tree controlled by a CPU and a plurality of measuring stands connected to one IC tester tree. , regarding the circuit that controls the test start interrupt signal from the measurement stand.

[11 (Previous technology) Next, the row 1 diagram according to the conventional technology when there are 24 measuring tables will be explained with reference to FIG. 4. In FIG. 12 is a measurement stand 6 The measurement stands 11 and 12 are electrically connected to each terminal of the IC to be measured, and send the measurement data of each IC to the main body 10. The main body 10 is controlled by the CPL II program, The data from the measurement tables 11 and 12 are used to determine whether each IC is good or bad.

It! Interrupt 1 word from II fixed stand 11 and 12 to main body 10
When the main body 10 issues an interrupt to the CPU 1, the CPU outputs an interrupted measuring table selection signal, and in the single measuring table mode, only that measuring table executes the test.

Next, the test start interrupt control circuit shown in FIG. 4 will be explained with reference to FIG. 21 and 22 in Figure 5 are AND game 1, 23 and 24 are O
This is R game 1.

11A is the interrupt signal of the measuring table 11, 12A is the measuring table 12
, 20 is a multi-mode signal, 23A is a test start interrupt signal for the measuring table 11, and 24A is a test start interrupt signal for the measuring table 12. For example, when the test start interrupt signal lIA from the measurement stand 11 is IQ, the test start interrupt signal 23A of the measurement stand 11 is sent from the OR gate 23 to the standby state, and the test start interrupt signal 24A of the measurement white 12 is sent from the OR gate 24. The system enters a standby state, and the test starts on both measurement tables 11 and 12 at the same time. The test on the measuring tables 1l and 12 is started from the measuring table 12 side in the same way as before when a test start interrupt is issued. [Problem to be solved by the invention] When the number of measuring tables increases beyond two, in addition to simultaneous multi-testing, it is necessary to divide the measuring tables into several groups and perform each It became necessary to conduct tests for each group.

It's coming! The maximum number of resetting tables was two, and the multi-test mode meant testing two at the same time.

However, when the number of measurement tables increases beyond two, many types of multi-mode division methods can be considered, and the conventional circuit concept no longer applies.

This invention allows a test start interrupt to be generated from any measurement stand.
The purpose of the present invention is to provide a test start interrupt signal control circuit which performs tests in the order of the test start interrupt shield numbers from the a+++ fixed stand after the test @ ends.

[Means for Solving 1 Problem] In order to achieve this object, the present invention includes an IC tester main body 10 controlled by a CPU 1 and an IC tester that tests an IC with a measuring stand connected to the main body 10. , C
FF 2 inputs the multi-test 1 mode data from PU 1, encoder 3 encodes the test start interrupt 1 word of each measurement stand, and encoder 3 inputs the output data of FF 2 as the lower address input. The output of the ROM4 is used as a test start interrupt signal for the Pr measuring stand and is sent to the CPUI. Next, the operation of the test start interrupt signal control circuit from the measuring stand according to the present invention will be explained with reference to FIG. 2 and 3 in FIG. 1 are FFs, 3 is an encoder, and 4 is a ROM.

FF2 inputs the multi-test mode data from CPLJ 1, and encoder 3 encodes the test start interrupt signal of measurement tables 11 to 13. 1” {OM4 is FF
The output data of 2 is used as the input of the lower address, the output of the encoder 3 is used as the input of the upper address, and the output of ROM 4 is used as the test start interrupt signal for the measurement tables 11 to 13.
Send to CPU1. [Function] The input address of R OM 4 will be explained with reference to FIG.

2A in Fig. 2 is the output signal of FF2, and 3A? This is the output of encoder 3.

Multitest I-mode data from CPIJI is FF2
If it is stored in , the output signal 2A of FF2 is R
The output word 4A of the ROM 4 at this time, which becomes the input to the lower bit 1 of the address of the OM4, is set so that it is all r■ when the logic is positive.

Therefore, no test start interrupt is generated from any measurement stand.

Next, for example, when an interrupt is issued from the measuring table 11, the signal 3A encoded as the test start interrupt signal is 110 M
4 is supplied with lj-, and the address of ROM 4 changes. As a result, an interrupt signal 4A is output from all measurement tables in the group in which the 11t1 fixed table 11 is separated. Next, the measuring table 11
The state when the test rmIft interrupt signal is output from the measuring tables 12 and 13 during the test will be explained with reference to FIG. Figure 3A shows the test start interrupt signal 11A from the measuring table 11.
FIG. 3A is a waveform diagram from when the measuring table 11 starts the test until the test ends.

FIG. 3C is a waveform diagram when the test start interrupt 1 word 12A is output from the measurement table 12 while the measurement table 11 is testing.
The diagram is a waveform diagram in which the test on the measuring table 12 is started after the test on the measuring table 11 is finished. Figure 3 O is a waveform diagram when the test start interrupt signal 13A is output from the measuring table 13 later than the test@start interrupt signal 12A of the measuring table 12 while the measuring table 11 is being tested. is a waveform diagram in which the test on the measuring table 13 is started after the test on the measuring table 12 is finished. That is, when the test start interrupt signal 12A is output from the measuring table 12 while the measuring table 11 is being tested, the measuring white 12 is turned off by the measuring table l.
The CPU is in a standby state until the test No. 1 is completed, and an interrupt signal 12A is stored in the CPU. Furthermore, when the test start interrupt signal 13A is output from the measuring stand 13, the measuring stand 13 also enters a standby state, and the test is executed for each measuring stand in the order in which the interrupt is applied. [Effects of the Invention] According to the present invention, the multi-test mode data from the CPU is input to the FF, and the FF output is input to the R. Since the lower address of OM is encoded and the test start interrupt signal of each measuring stand is encoded as the upper address of ROM, the test of each measuring stand can be executed in response to the interrupt signal Jlli from each measuring stand.

[Brief explanation of the drawing]

FIG. 1 is a diagram of the test start interrupt signal control circuit from the measuring stand according to the present invention, FIG. 2 is an explanatory diagram of the input address of the ROM 4, and FIG.
An explanatory diagram of the state when the test start interrupt signal is issued from 13,
Figure 3 is a configuration diagram of the conventional technology when the measuring table is 2-light.
FIG. 4 is a block diagram of the test start interrupt control circuit of FIG. 5. 1...CPU, 2...FF, 3...
・-・Encoder, 4...ROM, ■0・-・
...One IC tester, ■1 to 13...Measurement stand.

Claims (1)

[Claims] 1. IC tester main body (10) controlled by CPU (1)
In an IC tester that tests ICs with multiple measuring stands connected to the main body (10), start testing on each measuring stand. An encoder (3) that encodes the interrupt signal, and an RO that uses the output data of the FF (2) as the input for the lower address and the output of the encoder (3) as the input for the upper address.
A test start interrupt signal control circuit from a measuring stand, comprising: M(4), and sending the output of the ROM (4) to the CPU(1) as a test start interrupt signal for each measuring stand.