JPH03129522A - Digital signal processor - Google Patents

Abstract

PURPOSE:To execute efficient limit processing by directly inputting computed result data outputted from a data computing part to a limit processing part and allowing the limit processing part to execute the limit processing of the optional number of significant fits instructed from an instruction execution control part. CONSTITUTION:The instruction execution control part 2 informs an address instructed through an address bus 101 to an instruction memory 1, decodes the instruction word concerned and informs a control signal to an address forming part 6 through a data bus 104. Data or the like are sent to a data input bus 3 through a data bus when necessary and the number of significant bits is informed to the limit processing part 8 through a data bus 110. The data computing part 5 inputs the 2-input data sent to the data input bus 3 through a data bus 106, executes the prescribed two-term operation processing instructed from the control part 2 through the data bus 103 and directly outputs the operated result data to the limit processing part 8 through a data bus 108. Consequently, both the operation and limit processing can be executed only by one instruction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital signal processing device that performs limit processing on calculation result data.

[Conventional technology]

Figure 3 shows, for example, Tea Murakami Etoal.

``AzoESP Architecture-Four 64 Kilometers Motion Video Coachtsuk'', International Symposium on Circuits and Systems (Inissininis 88) t
pp, 227-230.1988 (T, Muraka
mi etal, “A DSP ARCHITECT
URE FOR64Kbps MOTION VIDE
OC0DEC'', INTERNATIONALSYM
PO8IUM ON CIRCUIT AND SYS
TEM (ISCAS 88).

(pp, 227-230, 1988) is a block diagram showing a simplified configuration of a conventional digital signal processing device, in which 1 is an instruction memory that stores instruction words of a microprogram, and 2 is an instruction memory that stores the instruction words of a microprogram. An instruction execution control unit reads command words from memory 1, decodes them, and controls operations such as calculations, 3 is a data input bus for mainly transferring data and control signals, and 4 is a plurality of input/outputs for storing calculation data. 5 is a data calculation unit that performs various calculations on the data transferred from the data memory 4 via the data input bus 3, and 6 is a data calculation unit of the data calculation unit 5; There are two address generators that independently generate addresses for output data, and 7 a data output bus that transfers the data operation result data.

Next, the operation will be explained using the flowchart shown in FIG. Here, after performing some binary arithmetic processing on the two-person data of n (an integer of Q) bits in the data arithmetic unit 5, m
A case will be described in which limit processing is performed in which the number of effective bits is (an integer where m≦n) bits.

First, the instruction execution control unit 2 notifies the instruction memory 1 of the designated address via the address bus 101, and reads the corresponding instruction word from the instruction memory 1 via the data bus 102. Further, the instruction execution control unit 2 decodes the read instruction word, notifies the address generation unit 6 of a control signal via the data bus 104, and inputs data etc. via the data bus 103 as necessary. Send to bus 3.

This control signal causes the address generation section 6 to
7, the data memory 4 is notified of the address of the two-person data (n bits each) necessary for the calculation, and the data memory 4 sends the corresponding two-person data to the data input bus 3 via the data bus 105. . The data calculation unit 5 inputs the two-person data sent to the data input bus 3 via the data bus 106, and performs a predetermined binary calculation process instructed by the instruction execution control unit 2 via the data bus 103. , operation result data (n bits) is transferred to the data bus 108
The data is sent to the output bus through the . The calculation result data sent to the data output bus is input to the data memory 4 via the data bus 109, and stored at the address given via the data bus 107 by the address generator 6 (step 5TI). . Next, the data calculation unit 5 again uses the data bus 1 by the above-described input operation.
It inputs the operation result data stored in the data memory 4 via 06, and executes a MAX instruction (effective bit number m bits), which is one of the instruction sets instructed by the instruction execution control section 2. This MAX instruction is an instruction that outputs the larger of the operation result data and the maximum value that can be expressed using m effective bits, and determines whether or not the operation result data exceeds the maximum value. If so, limit processing is performed, and the calculation result data obtained by executing the MAX instruction is stored in the data memory 4 by the above-described output operation (step ST2). Furthermore, by the input operation described above, the data calculation unit 5 again inputs the calculation result data obtained by executing the MAX instruction stored in the data memory 4 via the data bus 106, and inputs the calculation result data obtained by executing the MAX instruction stored in the data memory 4.
Executes an instruction (effective bit number m bits). This MIN
The instruction outputs the smaller of the operation result data and the minimum value that can be expressed using m effective bits.
It is determined whether or not the calculation result data is smaller than the minimum value, and if it is smaller, +J mit processing is performed, and the calculation result data for which the MIN instruction has been executed is stored in the data memory 4 by the output operation described above. (Step 5T3), the process ends.

Next, the limit processing will be explained using FIG. 5. First, n-bit operation result data (MSB is the most significant bit,
LSB is the least significant bit) (Fig. 5(a)). When performing limit processing to the effective number of bits m (m(n) bits, the upper (n-m) bits are the same data as the MSB,
If the value of the operation result data is within the range that can be expressed with m bits, the remaining m bits will be used as m-bit data, and if it exceeds the maximum value that can be expressed with m bits, then the maximum value will be changed to the minimum value that can be expressed with m bits. If it is smaller than the value, the minimum value is used as m-bit data (FIG. 5(b)).

Note that limit processing in which the number of effective bits is m=n has the same effect as when no limit processing is performed.

[Problem to be solved by the invention]

Conventional digital signal processing devices are configured as described above, so in order to perform limit processing on calculation result data, it is necessary to execute three instructions including calculation, which reduces processing efficiency. There was an issue.

The present invention has been made to solve the above-mentioned five fx problems, and an object of the present invention is to obtain a digital signal processing device that performs efficient limit processing.

[Means to solve the problem]

The digital signal processing device according to the present invention directly inputs operation result data after some operation has been performed in the data operation section, and performs limit processing on an arbitrary number of effective bits instructed by the instruction execution control section according to the contents of the microprogram. The present invention is equipped with a limit processing section that performs the following.

[For production]

In the digital signal processing device according to the present invention, the output of the data calculation section is directly input to the limit processing section, so that calculation and limit processing can be performed with one instruction.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram showing the configuration of a digital signal processing device according to an embodiment of the present invention, and the same or equivalent parts as in the conventional digital signal processing device (FIG. 3) are given the same reference numerals and explanations are omitted. do.

In FIG. 1, 8 directly inputs the operation result data output from the data operation section 5 via the data bus 108;
This is a +7 limit processing unit that performs limit processing to the number of effective bits instructed by the instruction execution control unit 2 via the data bus 110.

Next, the operation will be explained using the flowchart shown in FIG. Here, after performing some binary arithmetic processing on the two-bit manual data of n (an integer of Q) in the data calculation unit 5, m
A case will be described in which limit processing is performed in which the number of effective bits is (an integer where m≦n) bits.

First, the instruction execution control unit 2 notifies the instruction memory 1 of the specified address via the address bus 101, decodes the corresponding instruction word, and notifies the address generation unit 6 of a control signal via the data bus 104. At the same time, data etc. are sent to the data input bus 3 via the data bus 103 as needed, and the effective bit number is notified to the limit processing section 8 via the data bus 110.

This control signal causes the address generation section 6 to
7, the data memory 4 is notified of the address of the two-manpower data (n bits each) necessary for the calculation, and the data memory 4 sends the corresponding two-manpower data to the data input bus 3 via the data bus 105. . The data calculation unit 5 inputs the binary data sent to the data input bus 3 via the data bus 106, and performs a predetermined binary calculation process instructed by the instruction execution control unit 2 via the data bus 103. (Step 5T4), operation result data (n bits)
is output directly to the limit processing unit 8 via the data bus 10B. The limit processing unit 8 then limits the operation result data to m bits, the effective number of bits specified by the instruction execution control unit 2 via the data bus 110, and transfers the limited operation result data via the data bus 111. and sends it to the data output bus. Furthermore, the calculation result packet sent to the data output bus is
9 to the data memory 4, and is stored again at the address given from the address generation unit 6 via the data bus 107 (step 5T5), and the process ends. With the above operations, calculation and limit processing can be executed with one instruction.

〔Effect of the invention〕

As described above, according to the present invention, the calculation result data output from the data calculation section is directly input to the limit processing section,
Since the limit processing unit is configured to perform limit processing to an arbitrary number of effective bits instructed by the instruction execution control unit, calculation and limit processing can be performed with the - instruction, and the digital signal processing device can perform efficient limit processing. This has the effect of providing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a digital signal processing device according to an embodiment of the present invention, and FIG. 2 is a flowchart explaining the operation of the digital signal processing device of the present invention.
FIG. 3 is a block diagram showing the configuration of a conventional digital signal processing device, FIG. 4 is a flowchart explaining the operation of the conventional digital signal processing device, and FIG. 5 is an explanatory diagram of limit processing. In the figure, 1 is an instruction memory, 2 is an instruction execution control unit, and 3 is an instruction memory.
4 is a data input bus, 4 is a data memory, 5 is a data calculation section, 6 is an address generation section, 7 is a data output bus, and 8 is a limit processing section. In addition, the same symbols in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] Built-in microprogram fetching, decoding,
reading data according to the contents of the microprogram;
In a digital signal processing device whose basic operations are calculation and writing of calculation result data, the calculation result data is directly input and the calculation result data is limited to the number of effective bits arbitrarily specified by the microprogram. A digital signal processing device comprising a processing section.