JPH0310556U - - Google Patents
Info
- Publication number
- JPH0310556U JPH0310556U JP7133289U JP7133289U JPH0310556U JP H0310556 U JPH0310556 U JP H0310556U JP 7133289 U JP7133289 U JP 7133289U JP 7133289 U JP7133289 U JP 7133289U JP H0310556 U JPH0310556 U JP H0310556U
- Authority
- JP
- Japan
- Prior art keywords
- region
- conductivity type
- guard ring
- impurity region
- parallel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000012535 impurity Substances 0.000 claims 4
- 238000009792 diffusion process Methods 0.000 claims 3
- 230000015572 biosynthetic process Effects 0.000 claims 2
- 239000004065 semiconductor Substances 0.000 claims 2
- 239000000758 substrate Substances 0.000 claims 2
- 238000000034 method Methods 0.000 claims 1
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
第1図と第2図は本考案を説明する為の断面図
、第3図は従来例を説明する為の断面図である。
1 and 2 are sectional views for explaining the present invention, and FIG. 3 is a sectional view for explaining a conventional example.
Claims (1)
半導体基体の一部に第2導電型不純物領域を形成
し、この第2導電型不純物領域表面の一部に第1
導電型不純物領域を設けてソースとし、ソース・
ドレイン間の第2導電型表面領域をチヤンネル部
としてこの上に絶縁膜を介してゲート電極を設け
たMOSFETセルを多数並列接続し、前記セル
を並設した素子形成領域の周囲を複数本の第2導
電型のガードリング領域で囲んだ縦型MOSFE
Tにおいて、 前記素子形成領域は周囲より掘り下げた平坦面
とし、該平坦面の周囲は緩やかなテーパー面とし
、前記ガードリング領域を互いの拡散深さが同じ
になるように前記テーパー面の表面に形成したこ
とを特徴とする縦型MOSFET。 (2) 前記第2導電型拡散領域の一部と前記ガー
ドリング領域とが同一工程で形成された拡散領域
であることを特徴とする請求項第1項に記載の縦
型MOSFET。[Claims for Utility Model Registration] (1) A first conductivity type semiconductor substrate is used as a drain, a second conductivity type impurity region is formed in a part of the semiconductor substrate, and a second conductivity type impurity region is formed in a part of the surface of the second conductivity type impurity region. 1st
A conductive impurity region is provided to serve as a source, and
A large number of MOSFET cells each having a gate electrode provided thereon via an insulating film are connected in parallel, using the surface region of the second conductivity type between the drains as a channel part, and a plurality of MOSFET cells are connected in parallel around the element formation region where the cells are arranged in parallel. Vertical MOSFE surrounded by two conductivity type guard ring regions
In T, the element formation region is a flat surface dug deeper than the surroundings, the periphery of the flat surface is a gently tapered surface, and the guard ring region is formed on the surface of the tapered surface so that the diffusion depths of each region are the same. A vertical MOSFET characterized by the following: (2) The vertical MOSFET according to claim 1, wherein a portion of the second conductivity type diffusion region and the guard ring region are diffusion regions formed in the same process.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7133289U JPH0310556U (en) | 1989-06-19 | 1989-06-19 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7133289U JPH0310556U (en) | 1989-06-19 | 1989-06-19 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0310556U true JPH0310556U (en) | 1991-01-31 |
Family
ID=31608263
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7133289U Pending JPH0310556U (en) | 1989-06-19 | 1989-06-19 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0310556U (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000183350A (en) * | 1998-12-09 | 2000-06-30 | Stmicroelectronics Srl | Method of manufacturing integrated edge structure for high voltage semiconductor device and integrated edge structure |
JP2009187994A (en) * | 2008-02-04 | 2009-08-20 | Fuji Electric Device Technology Co Ltd | Semiconductor device and manufacturing method thereof |
JP2011029393A (en) * | 2009-07-24 | 2011-02-10 | Sanken Electric Co Ltd | Semiconductor device |
-
1989
- 1989-06-19 JP JP7133289U patent/JPH0310556U/ja active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000183350A (en) * | 1998-12-09 | 2000-06-30 | Stmicroelectronics Srl | Method of manufacturing integrated edge structure for high voltage semiconductor device and integrated edge structure |
JP4597293B2 (en) * | 1998-12-09 | 2010-12-15 | エスティーマイクロエレクトロニクス エス.アール.エル. | Method for manufacturing integrated edge structure for high voltage semiconductor device and integrated edge structure |
JP2009187994A (en) * | 2008-02-04 | 2009-08-20 | Fuji Electric Device Technology Co Ltd | Semiconductor device and manufacturing method thereof |
JP2011029393A (en) * | 2009-07-24 | 2011-02-10 | Sanken Electric Co Ltd | Semiconductor device |
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