JPH03104227A - Etchant for amorphous silicon and etching method using same - Google Patents

Abstract

PURPOSE:To simplify the control of etching conditions by etching an n<+>-type amorphous silicon film using an etchant consisting of HNO3, HF, CH3COOH, H2O with particular volume ratio. CONSTITUTION:An etchant consists of 70-100 pts.vol. of nitric acid (HNO3), 0.1-1 pts.vol. of hydrofluoric acid (HF), 40-200 pts.vol. of acetic acid (CH3COOH), the rest of water (H2O). This etchant for amorphous silicon is used to etch an n<+>-type amorphous silicon film formed on an n<->-type or intrinsic amorphous silicon film. Therefore, the selection ratio of the etching for the n<->a-Si film and the n<+>a-Si film is made higher, and moreover, the etching rate for the n<->a-Si film is made not more than 100Angstrom /min.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a manufacturing technology for amorphous silicon transistors, and in particular to an etching solution and an etching method.

BACKGROUND OF THE INVENTION Amorphous silicon thin film transistors are typically constructed using amorphous silicon, particularly hydrogenated amorphous silicon, as a channel type or layer. This channel forming layer is an amorphous silicon (including hydrogenated amorphous silicon) film of intrinsic (i) or n-conductivity type, and has a structure in which a source electrode and a train electrode are provided on the upper side. In the following description, hydrogenated amorphous silicon (a-Si) will be simply referred to as amorphous silicon (a-Si), and amorphous silicon of intrinsic (i) or n-type conductivity will be referred to as n-type amorphous silicon.
It is included in one conductivity type amorphous silicon and is called 口-a-Si, and also includes n+ conductivity type amorphous silicon! n”
It is sometimes called a-Si. The source and train electrodes of this a-Si thin film transistor (TFT) are generally formed on a na-Si film.
It uses an n"a-Si/metal structure consisting of an n"a-Si film and a metal film. This metal is chromium (C
r), aluminum (An, etc.) is used.
When the ``a-Si film is interposed, the contact between the source and train electrodes and the rMa-Si film can obtain good uniformity characteristics for electrons.On the other hand, when the n''a- n-a-Si film and A without using Si film
If an electrode structure is adopted in which the A2 and n-a-Si are in direct contact with each other, since Au is trivalent, the contact between A2 and n-a-Si due to thermal history will result in ohmic contact even with holes. As a result, the TPT comes to operate even in the hole accumulation mode, which undesirably reduces the off-state margin of the TPT. For the above reasons, in a-SiTPT, in order to obtain good contact only with electrons, na-SiTPT is
An n"a-Si film was interposed between the film and the metal that is the source and drain electrode material. However, the n"a-
In order to use Si film, in the conventional TPT manufacturing process,
It was necessary to remove the portion of the n''a-Si film that was shaped like IIi above the channel part of the n-a-Si film between the source and drain electrodes (for example, JP-A-58 112365).The first method for manufacturing TPT according to the prior art disclosed in this publication will be described below.Figure 2 shows each process step in order to explain the method for manufacturing a thin film transistor according to the prior art. This is a cross section of the main part of the semiconductor.

First, in the process step shown in FIG. 2(A), a gate electrode 12 is formed on a glass substrate 11, and then a gate isolation film (Si○2, SiNx, or a composite film thereof) 1 is formed.
3 to a thickness of 1000 to 3000, and then n-
Amorphous silicon (n-a-Si) film 14, etching stopper layer 15 made of SiNx or Si
Form an O2 film in sequence. These three types of films 13, 14
and 15 are formed by conventional techniques, and Si○2
, SiNx and a-Si. and N20 mixed gas, Si port. A mixed gas of and N days, S i H
Only a (from here, plasma chemical vapor deposition (PCVD)
From this point on, each of them has a powerful shape. Then, using photolithography techniques, the source train electrode shape FIi. A portion of the etching stopper layer 15 corresponding to the region indicated by a in the figure is selectively removed by etching to form an etching stopper layer portion of the region indicated by b above the channel portion of the na-Si film 14. 15a remains in its remaining form (FIG. 2(B)). Furthermore, this remaining portion 15
a is the electrode portion M region.

Thereafter, the n''a-Si films 16a, 16b, and 16cl are formed to a thickness of several hundreds of liters by the PCVD method or the ion-mass battering method.
It is formed by a mixed gas of x H a and Pth (Figure 2 (C)). Thereafter, by a lift-off method, the source electrode 17a and the drain electrode +7b! After that, a source electrode 17a and a drain electrode +7b are formed.
As a t mask, n of the region indicated by b above the channel part
” a-Si film portion 16c 'jj: G F a and 0
A thin film transistor is formed by etching and removing using a plasma etching method using a mixed gas with 2 and the like (
Figure 2 (D)).

Further, FIG. 3 is a cross-sectional view of the main part of the semiconductor at each process step for explaining a second manufacturing method of TPT according to another conventional technique disclosed in the above-mentioned document. In this conventional method, a gate electrode 12 is formed on a glass substrate 11, and then a gate insulating film 13 and a na-Si film 14 are formed using the same steps as the method shown in FIG. (FIG. 3(A)) & on this n-a-Si film 14
CM3 (B)) in which the "a-Si film 16 is continuously formed by the PCVD method".Then, this n" a-Si film 1 is
For example, A℃ is deposited on the entire surface of the source/drain electrode material on the source electrode 1 using photolithography technology.
7a, drain electrode +7b is formed (Fig. 3(C))
．． Next, a portion +6A of the n''a-Si film 16 located above the channel portion of the na-Si film 14 is removed by dry etching to form a thin film transistor (FIG. 2(D)).

(Problem to be solved by the invention) However, because the first manufacturing method of the prior art described above (FIG. 2) takes the step of providing an etching stopper layer 15 on the na-Si film 14, , the number of photolithography increases accordingly, which increases the number of manufacturing steps, resulting in a problem of poor yield and high manufacturing costs. In addition, the second manufacturing method CM of the conventional technology
3), the n”a-Si film part above the channel part +
Since the etching removal of 6A was carried out by the dry etching method, the n'' a-Si film 16 and the n-a-Si
The etching rate ratio (selectivity) with respect to the film 14 is small. Therefore, as shown in part A indicated by the dotted line in FIG. 2(D), n''
When etching the a-Si film 16A, the na-Si film 14
In extreme cases, the etching of the n''a-Si film 16A may completely remove the n''a-Si film 14. There was a problem that the etching was not removed, and the TPT could no longer function as a switching element.Also, when using dry etching, it is difficult to control the etching rate of the n''a-Si film, so it is not possible to remove it with good reproducibility. , n” a-
The problem was that it was difficult to remove the Si film by etching. This invention solves the conventional problems of reduced yield and increased manufacturing cost due to the provision of an etching stopper layer as described above, and the n''
This invention was made in order to eliminate the conventional problems of TPT characteristic differences between substrates, poor etching reproducibility, and reduced yield caused by removing the a-Si film by dry etching. The purpose of is r
The object of the present invention is to provide an etching solution (etchant) with a high etching selectivity between the r a-Si film and n"a-Si #, and an etching method using this etching solution. (Means for solving the problem) In order to achieve this objective, according to the etching solution for amorphous silicon of the present invention, nitric acid (N
H03) 70-100, hydrofluoric acid (F) 0.1-1
, acetic acid (C,83C○○}-1)% 40-200% and the balance water (}-120). Furthermore, according to the etching method of the present invention, an n+ type formed on an n-type or intrinsic amorphous silicon thin film
The method is characterized in that the amorphous silicon thin film is etched using the amorphous silicon etching solution described above. (Function) According to the etching solution for amorphous silicon according to the present invention, as is clear from the experimental data described below,
The etching selectivity ratio between the n-a-Si film and the n''a-Si film is about 15 or more at room temperature. Therefore, using this etching solution, a pattern can be formed on the n-a-Si film by a wet process. aru n” a-S
By etching the i-film, the upper n''a-Si film can be etched as desired without substantially etching the lower n-a-Si film. (Example) The drawings are shown below. An etching solution for amorphous silicon of the present invention and an etching method using this solution will be explained with reference to the following. First, an etching solution for amorphous silicon of the present invention (hereinafter simply referred to as an etchant) will be explained.

Generally, crystalline silicon (S
What is the etching mechanism of i)? Si◆4HN03 →3S
iO■+4NO◆2H20 ・-(1
)? iO■◆6HF-+H 25 IF e◆2H20
-(2) It is thought that the process proceeds through the two elementary reactions of equations (1) and (2) above. Considering these elementary reactions,
In a high-concentration HF etchant, the oxidation reaction shown in equation (1) is rate-limiting, so the HNO3 concentration determines the etching rate.
In the case of the 3-etchant, the decomposition reaction shown in equation (2) is rate-determining, so the etching rate is a function of F. From this, it is possible to control the etching rate of silicon (Si) by changing the concentrations of HF and N3. In this sense, acetic acid (C) is usually used as an inhibitor to reduce the reaction rate (etching rate). Similar to such crystalline Si, a-Si also has a similar mechanism {thus HNO
It is thought that the 3rd F/C opening and C○○ are etched with the solution.

Therefore, the inventors of this application determined that the etching rate of the n-a-Si film and the n''a-Si film was
Measurements were made by changing the composition ratio of the F/CH3C○○ day etchant. The results of this experiment are shown in FIG.

The n-a-Si film used in this experiment had a substrate temperature of 30
0″C, the pressure of the film forming chamber was 80Pa, the high frequency power density was 0.02W/cm2, and the reaction gas Si inlet I1i.
The film was formed by PCVD with a flow rate of 408 CCM to the membrane chamber. In addition, n'' a-SiIII is determined by the substrate temperature Iv
300' C, the pressure in the film forming chamber was 80 Pa, and the high frequency power density was 0.02 W/am2, which were the same as those for the na-Si film, but the phosphorus (P) dove Il7aP
It was formed by the PCVD method while changing the flow rate ratio of H 3 and SiH 4 .

The etchant used here was HNO3,
Mix it with water, and adjust the ratio so that the daily N○3 concentration is 59%.
Glacial acetic acid was added to this A acid to change the composition ratio of the etchant as a solution tA acid with a concentration of 0.5% and a balance of 20%. In Figure 1, the horizontal axis shows glacial acetic acid (C.
When the composition ratio is changed by changing the mixture of
3 C○○'s etchant composition ratio [[CH3COO
] / ([A acid] + [Cth, COO day])], and the vertical axis shows the etching rate at room temperature (A/m i
n) Shown as %. In addition, in the figure, the curved line is for an na-Si film that is not doped with phosphorus (P),
Each sample shown by curves II to ■ is on day P when it flows into the film forming chamber.
From the reaction gas flow rates of SiHa and [Pth, ]/[SiHa. ] Phosphorus (P) by the value (%) calculated by the flow rate ratio! This is the case of an n'' a-Si film obtained by coating with a mixed reaction gas containing 0.5% phosphorus dope and curve I1.
is an n''a-Si film with 1% phosphorus dope, curve (2) with 3% phosphorus dope, and curve V with 5% phosphorus dope.

As is clear from this experimental data, the etching rate of the na-Si film without phosphorus doping (curve I) is C. Etchant without C○○ day mixed in was about 5,300 people/min. C○
○When the amount of grains mixed in is about 0.33 in terms of composition ratio, the etching speed becomes 100 people/min, and the roughness (about 0.33) is reached.
At around 40, the number of people per minute has decreased by 100 people/min. On the other hand, the etching rate of the phosphorus-doped n''a-Si film shown by curves ■ to V is approximately 2
500 people/min, 3800A/min, 5000 people/
min and 5600λ/min, roughly about 0.
About 40 C days. The amount of contamination at the COO port is approximately 1500 A/min and 2700 A/min, respectively.
, 4200 people/min and 4800 people/min.

From this experimental data, when the amount of CH3COO is 0.5 or more, phosphorus-free a-Si
In other words, it can be seen that na-Si is substantially not etched. Even for n"a-Si films, depending on the amount of phosphorus doped, some films are not etched substantially and others are etched at a sufficient etching rate. The membrane has more CH3
It can be seen that etching occurs even if the amount of C○○ increases.

From this experimental data, it can be seen that n-a- without phosphorus (P) dobe
The etching rate of the Si film (curved) is [C day 3 Co
oth] / C [A acid] + [CH3C○○H])
It is approximately 0.4 and has an extremely small value of less than 100 people/min. On the other hand, both n"a-Si films doped with phosphorus (CP) (curve II-V) are exposed to the same concentration of etchant. , has an etching rate of about 1500/min or higher, and therefore has a
It can be seen that the etching selectivity with respect to the -Si film is a value of 15 or more. Similarly, [CH3C○○day]/
It can be seen that when ([A acid + [CH3C○○]) is about 0.33, the etching selectivity becomes a value of 25 or more.

Apart from the above-mentioned experiment, we experimentally determined the concentration of the stock solution of HNO3 (
If the concentration before mixing) is too low, e.g. lower than 50%,
It was found that the etching rate of the n''a-Si film became smaller, bubbles were generated violently, and the etching was unevenly etched.
If the concentration of the stock solution of 03 is higher than 60%, in the case of etching using a resist, the resist will be damaged. If no resist is used, the concentration of the stock solution may be higher than 60%. As a result, the concentration of the stock solution of NO3 according to the present invention is preferably within the range of 50 to 60%,
And HNO3, HF, CH3 C○○ day and H20
The range of HNO3 concentration in the mixed etchant is 20
~40% (mixed volume ratio of etchant 70-100)
is preferable. In addition, regarding the HF concentration in the etchant of this invention, there is a problem with the surface roughness of the etched surface of the channel (as the HF concentration increases, the surface of the channel part tends to become uneven).
There is an appropriate HF concentration from the viewpoint of not causing secondary problems such as an increase in off-current due to surface leakage and the effect on the film contribution of the passivation film, and experimentally it is 0.01 to 0. It was found that 0.5% (0.1 to 1 etchant mixing volume ratio) is suitable.

From the above-mentioned preferred amounts of HNO3 and day F and the experimental data (Fig. 1) of the amount of contamination on day C, ○○, as described above, the preferred amount of contamination on day C, 000 mouths is determined as follows. The mixing volume ratio of etchant on C○○ day was 70 to 200.
(concentration is about 30-70%). Next, an etching method using the etchant of this invention will be explained. In this embodiment, a case will be explained in which this etchant is used in the manufacturing process of TPT, which forms a two-layer structure of an rr a-Si film and an n''a-Si film.

FIG. 4 shows an example of a TPT manufacturing process using the etchant according to the present invention. In the same figure, the same components as those shown in FIGS. 2 and 3 are designated by the same reference numerals, and each component is shown in the size to the extent that this invention can be understood. , the shape and arrangement relationship are schematically shown. Each figure shows a cross-sectional view of the structure obtained at the manufacturing process stage. First, a chromium (Cr) gate electrode 12 is placed on a glass substrate 11.
is formed to a thickness of 1,000 to 1,500 nm, and then a SiNx film is formed as the gate insulating film 13, and a SiH. Approximately 2,000 to 4,000
The rra-Si film 14, S
PCVD method using IHa gas {approximately 200 ~
Formed with a thickness of 1,500 μm, the n”a-Si film is roughly 16
Wow, SiH. By PCVD method using and PH3 gas,
Figure 4 (A)
Obtain the vm structure shown in . For some of these films, the film formation by the PCVD method is performed at a substrate temperature of 150 to 350''C in total.Furthermore, some of the n'' a-Si films 16 are formed by the Pth. The flow rate lfr[P day. ] and the flow jl of S I H a is [SiH4], Si day . It is preferable to set the gas flow rate ratio ([PH3/[Si]) within the range of 0.5 to 5%, preferably 3%. Next, chromium (Cr) and aluminum (Alli20) are placed on the n''a-Si film 16 as electrode materials Iil20.
The resist patterns 22 for the source electrode and train electrode patterns are formed by photolithography (see FIG. 4(B)).
)).

After that, the A exposed between the resist patterns 22 is
Look at the n part. P○4 first glance NO3C eyes. C○○ glance 2
Etching with 0 series etchant and Cr%NiM second
The underlying n''a-Si film 16 is partially exposed by sequential etching using a cerium ammonium etchant, and the source electrode portion 22a and the train electrode portion 20b are shaped respectively. ) is obtained. Then, source and train electrodes 20a and 20b are obtained.
n”a-S on the upper side of the channel exposed to Iffi
i membrane part +6A t, H which is the etchant of this invention
NO3-HF-C day. HNO3 with 20 solutions at a glance
, HF, and a solution with a volume mixing ratio of 30%, 0.25%, and 50%, respectively, are used to remove n''a as the lower layer of the source electrode 20a at room temperature. A source electrode portion 16a of the -Si layer and a train electrode portion +6b of the n'' a-Si layer as a lower layer of the drain electrode 20b are formed to obtain the structure shown in FIG. 4(D). Using this etchant, na-a-
When the n"a-Si film 16 formed on the Si film 14 is etched, the n"a-Si film 14 and the n"a-S
Since the etching rate ratio (selectivity) with respect to the i film 16 is significantly higher than that of conventional dry etching, the lower n
-a-Si film 14 is etched without etching, n
"Only the a-Si film 16 can be removed by etching. For example, if the film thickness of the a-Si film 16 is 500 mm thick, etching is performed for 30 seconds using this etchant to form an amorphous silicon thin film transistor (a-S
iTFT)! were manufactured and various properties were measured. As a result, the TPT characteristics are gate width W/gate length L = 1 0
0/10 element, threshold voltage vt = 2.5 to 3 ports, turn-off ratio (■.o/■.ff) = 105 to 108
It was good. Furthermore, the n”a-Si film 1 with the same thickness
TP manufactured by soaking in the same etchant for 60 seconds as compared to 6
As a result of measuring the TPT characteristics, the threshold voltage vT
The results showed that there was almost no change in both the on-off ratio (mm../.ff), and it was confirmed that a large etching margin could be obtained.

The thickness of the na-Si film 14 is an off-current factor that provides an on-off ratio. It is desirable that it be as thin as possible, depending on the size of ff. In that sense as well, the n-a-Si film 14 and n-a-Si film 14
It is desirable that the etching selectivity with respect to the a-Si film 16 be large.
Even for 00λ, using the above etchant, n
” TP manufactured by etching away the a-Si film 16
When we measured the TPT characteristics of T, we found that the above-mentioned TP
Similar to the T characteristics, the TPT characteristics were good. It is clear that the invention is not limited only to the embodiments described above, but can be subjected to many variations and modifications.

For example, etching the upper layer + a-Si film of the two-layer structure of the n-a-Si film and the n+a-Si film described above {at this time, the etching method of the N○3 Ichimoku ``1C H 3C O O H H
Etchant, which is a mixed solution of 20
3, eyes F and C. The content of C○○ is preferably 70 to 100:0.1 to 1:40 by volume, under conditions such that the concentration of HNO3 stock solution (in the case of HNO3 + H20) is in the range of 50 to 60%. ~200, the concentration is 30%, 0.25% and 5, respectively.
There may be a concentration relationship other than 0%.

The etchant with the above volume ratio is pure water, commercially available HNO3 with a concentration of 60%, and HF with a concentration of 50%.
and CH3 C○○ with a concentration of 99.9% can be easily mixed and harvested using a mortar. Furthermore, due to the characteristics of TPT, the above-mentioned n-a-Si film has Si order. The film is preferably formed by a PCVD method using gas, and has a specific resistance of 10 8 Ω·cm or more. In addition, as the n'' a-Si film, TP
Due to the characteristics of T, Pth and Si days. PCV using gas
It is formed by the D method and its flow rate ratio is [Pth, ]/[S
i day. ] or 0.5 to 5%, and the specific resistance is 103Ω・
It is preferable that it is less than cm. In addition, the above-mentioned a-SiT
When manufacturing FT, Cr is used as the source/drain electrode layer.
Although two layers of AJ and AJ were provided, either Cr or Al may be used as the only layer. (Effect of the invention) As is clear from the above explanation, according to the etching solution for amorphous silicon of the present invention, n-a
-The etching selectivity between the Si film and the n"a-Si film is high, and the etching rate for the n-a-Si order is less than 100λ/mi. Therefore, etching using this etching solution According to the method, rMa
- Etching the n”a-Si film formed on the Si film,
without substantially etching the underlying n-a-Si film.
Therefore, the etching margin of the n'' a-Si film can be increased, and since this etching method is wet etching, the etching conditions can be easily controlled. The etching method using this etching solution is suitable for manufacturing amorphous silicon thin film transistors, and when manufacturing amorphous silicon thin film transistors using this etching solution, the manufacturing yield is improved and the manufacturing cost is low compared to conventional methods. Can be manufactured with good reproducibility.

[Brief explanation of drawings]

Figure 1 shows the relationship between the composition ratio of acetic acid in the etching solution and the etching rate, in order to explain the characteristics of the etching solution for amorphous silicon of the present invention. Characteristic curve diagrams showing experimental data for phosphorus-doped amorphous silicon containing
Manufacturing process diagrams for explaining the first and second manufacturing methods of conventional amorphous silicon thin film transistors, and FIGS. 4(A) to (D) are for explaining the etching method of the present invention. FIG. 11... Glass substrate, 12... Gate electrode 1
3... Gate insulating film, 14... n-a-Si
Film 16-n"a-Si film 16a, 16b-n"a-Si film portion 20...electrode material layer, 20a...source electrode portion 20b.
...Train electrode portion 22...Resist pattern.

Claims (2)

[Claims] (1) Volume ratio: HNO_3 is 70-100, HF is 0
．． 1 to 1, an etching solution for amorphous silicon characterized by comprising 40 to 200 of CH_3COOH and the balance of H_2O. (2) Using the etching solution according to claim 1, n^-
An etching method characterized by etching an n^+ type amorphous silicon thin film formed on a type or intrinsic amorphous silicon thin film.