JPH029372B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a storage unit (hereinafter referred to as key-in storage) that stores key data that controls storage protection etc. for access to a main storage device by a computer central processing unit. ) related to key buffer storage that buffers and stores data from files.

(b) Background of the technology In modern electronic computers, control programs and user programs are multi-processed, and it is necessary to prevent errors in one program from interrupting the execution of other programs or outputting erroneous results. It is necessary to provide computers with a memory protection function to prevent important data from being intentionally retrieved or referenced.

There are several methods for memory protection, but the key method is generally used. The key method divides the main storage (or main storage, hereinafter referred to as MS) into blocks of, for example, 2048 bytes.
A key-in storage (hereinafter referred to as KS) is provided for each block to store key data that controls the storage protection of the main memory and records references and changes, and the central processing unit (hereinafter referred to as CPU) accesses the MS according to the program. At this time, by reading the KS and comparing it with a protection key provided in a program status word (hereinafter referred to as PSW) that controls the order of instruction execution and displays the status of the computer system related to the program, This method allows or prohibits access to the block and, if access is permitted, stores in the KS whether the access to the block is for reading or storing.

In order to speed up CPU program processing,
program and operands prior to processing
The so-called buffer memory method, in which key data is transferred from the MS to a high-speed buffer memory, is widely used, but the key buffer storage (hereinafter referred to as KBS) according to the present invention is also used in the key data of the KS. By holding data that is relatively likely to be lost in a buffer, it is possible to execute memory protection processing by the CPU at high speed.

(c) Prior art and problems Below, an example of a method for correcting an error when an error is detected in data read from the KBS is to use a redundant code (errorcorrecting code: hereinafter referred to as ECC) for error correction added to the data. However, if the number of bits per word is small, the ratio of the number of bits required for ECC is large, and it is not only uneconomical as it requires a large amount of high-speed and expensive memory elements and correction circuits. Since it takes time to correct the problem, the machine cycle becomes longer.
There was a problem that the processing power of the CPU decreased. Another example is to configure a KBS that stores key data for multiple MS blocks and an alternative KBS that stores a copy of the data in separate memory elements, and switch between them when an error occurs. In this case as well, there was a problem in that the duplex configuration increased the number of memory elements and peripheral circuits.

(d) Object of the Invention In view of the above-mentioned problems, an object of the present invention is to reduce the number of memory elements and realize a high-speed and efficient KBS.

(e) Structure of the Invention Key-in storage that stores access control information and access type information corresponding to a predetermined capacity block of the main storage device, and a part of the key-in storage that stores it as a buffer for the central processing unit. In a device that has a key buffer storage and controls access and records by reading the key buffer storage when accessing the main memory, an error control bit is included in the access control and type information from the key buffer storage. is added and stored twice in an area divided into lower and upper areas in the depth direction of the address, and access control and type information are read from the corresponding lower area when accessing the main storage device. the key buffer storage; means for updating the access type information of the lower area according to the access type at the time of the access; and means for updating the error control bit and the corresponding upper area when a read error is detected during the access. A key buffer storage characterized by controlling access to a main storage device and storing data by correcting errors based on the contents and storing the errors in the lower area. The invention satisfactorily achieves the above objectives.

(f) Embodiments of the Invention FIG. 1 is a diagram showing an example of the configuration of duplication of KBS for a memory element, FIG. 2 is a diagram of an example of the data configuration of KBS, and FIG. 3 is a block diagram showing an embodiment of the invention.

In FIG. 3, KS1 is an MS (not shown).
For example, it is a key-in storage (KS) that stores key data that controls protection (memory protection) against attacks by the CPU on 2048-byte blocks.
acc is used to determine permission or prohibition of access to the relevant MS block by comparing it with a PSW protection key (not shown), and f is used to determine whether access to the relevant MS block is permitted or prohibited, and f is used to perform read operations in addition to storage operations for the relevant MS block. r indicates that a memory protection test be performed even if the
This indicates that a read or store reference has been made to the MS block, and c indicates that a store has been made.

In Figure 1, the KBS consists of 256 words of random access memory (hereinafter referred to as RAM), and is divided into an area from addresses 0 to 127 (hereinafter referred to as primary) and an area from addresses 128 to 255 (hereinafter referred to as alternative). Each section stores 128 key data. Normally, the primary is used, and the alternative is used for backing up the primary.

Figure 2 shows the data structure of KBS, and ADRS is the address of KS where the key data is stored.
The upper 8 bits of the 15 bits are stored and used to determine whether the key data is the desired data by comparing it with the MS addresses PA6 to PA13 designated by the CPU. ACC, F, and R
correspond to acc, f, r of KS. C, C′, C″ are
The error correction code corresponds to c of KS, and all “0”
Alternatively, by setting it to "1" and using it, when a 1-bit read error is detected, it can be corrected using 3-bit majority logic. KV indicates that this key data is valid. The bits with P appended to the codes indicate parity bits for the respective codes.

Further, in FIG. 3, KS1 is a 32K (K=1024) word memory having the data structure described above, and has an MS address PA6 specified by the CPU.
(MSB) ~ PA6 ~ PA2 in PA31 (LSB)
Addressed by 0. KBS2 consists of a RAM with a capacity of 256 bits, and has two primary (PRM) and alternative (ALT) areas that each store 128 words of key data.
PRM or ALT is selected by a 1-bit latch L, and one word of key data is specified by addresses PA14 to PA20 at which the CPU specifies MS. The key buffer register (hereinafter referred to as KBR) 4 has a data configuration similar to that of KBS2, and stores data read from KBS2,
Holds data etc. to be written to KBS2. Therefore, when loading key data from KS to KBS2: The key data of KS addressed and read by PA6 to PA20 has acc, f, and r as they are, c is expanded to 3 bits, and each parity bit is It is added and set in the corresponding bit position of KBR4. Also address PA6
~PA13 also adds parity bit and does the same
KBR4 is set, and then the latch L and
Addressed by PA14-PA20 and stored in both the PRM and ALT areas of KBS2 by switching latch L to 0 and then to 1.

During normal operation, key data is read from KBS2 when the CPU accesses the MS block: Set latch L to 0 and read PRM's PA14 to
Reads the key data from the address specified by PA20 and sets it in KBR4,
A comparison circuit (hereinafter referred to as
(referred to as COMP) 3, and if they match, the key data is determined to be the target data and is output from the KBR 4 to a memory protection inspection unit (not shown) for memory protection inspection. Also MS
R, C, C',
C″ is updated on KBR4 and stored in the original position of PRM. If there is a mismatch in the above verification, it indicates that the target key data does not exist in KBS2,
KBR4 ACC, F, R and C from PA14 to PA
At the same time, the key data is stored in the storage location of KS1 specified by the address configured by adding the value of ADRS to the upper part of 20 and deleted, and the key data is read from the storage location of KS1 specified by addresses PA6 to PA20. Similarly, store it in both the PRM and ALT areas of KBS2.

In the above read operation, when an error is detected by the parity check circuit (hereinafter referred to as PC) 6: The latch L is switched from 0 to 1 and the key data is read from the corresponding storage location on the ALT side to KBR4 instead. and outputs it to the memory protection inspection unit. Next, the correction unit 7 performs ADRS,
ACC and F read data from ALT,
R is 1 (assuming there is a reference to MS of course)
, and C, C', and C'' are the values corrected by majority logic from the data previously read from PRM.
Repair the error by storing the PRM in its original location.

(g) Effects of the Invention As explained above, according to the present invention, error data can be repaired by the error correction code added to the access type data section updated by the alternative provided for backup and MS reference. Therefore, when reading the KBS in normal operation, it is possible to use only the primary to perform processing, and storage protection and access type data update processing can be executed at high speed. Furthermore, since the memory element is divided in the address depth direction, the number of memory elements and peripheral circuits can be halved, and the present invention has the effect that a low-cost and highly efficient key buffer storage can be realized.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a configuration example of duplication of KBS for a memory element, FIG. 2 is a diagram showing an example data configuration of KBS, and FIG. 3 is a block diagram showing an embodiment of the present invention. In Figure 3, 1 is key-in storage, 2
is a key buffer storage, 3 is a comparison circuit, 4 is a key buffer register, 5 is an update circuit,
6 is a parity check circuit, 7 is a correction section, and L is a latch.

Claims (1)

[Scope of Claims] 1. A key-in storage that stores access control information and access type information corresponding to a predetermined capacity block of the main storage device, and a buffer memory for a part of the access control information for the central processing unit. In a device that has a key buffer storage and controls access and records by reading the key buffer storage when accessing the main memory, the apparatus includes error control for controlling access from the key buffer storage and for type information. Bits are added to the address to store it twice in an area divided into lower and upper areas in the depth direction, and access control and type information are read from the corresponding lower area when accessing the main memory. means for updating the access type information of the lower area according to the access type at the time of the access; and means for updating the error control bit and the corresponding upper area when a read error is detected during the access. A key buffer storage device comprising means for correcting an error based on the content of the data and storing it in the lower area to correct the error, and controlling access to and recording the main storage device.