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JPH0281448A - Method of mounting semiconductor integrated circuit - Google Patents

Method of mounting semiconductor integrated circuit

Info

Publication number
JPH0281448A
JPH0281448A JP23310988A JP23310988A JPH0281448A JP H0281448 A JPH0281448 A JP H0281448A JP 23310988 A JP23310988 A JP 23310988A JP 23310988 A JP23310988 A JP 23310988A JP H0281448 A JPH0281448 A JP H0281448A
Authority
JP
Japan
Prior art keywords
resin
electrodes
wiring
wiring electrodes
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP23310988A
Other languages
Japanese (ja)
Other versions
JP2546351B2 (en
Inventor
Harutaka Taniguchi
谷口 春隆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP23310988A priority Critical patent/JP2546351B2/en
Publication of JPH0281448A publication Critical patent/JPH0281448A/en
Application granted granted Critical
Publication of JP2546351B2 publication Critical patent/JP2546351B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

PURPOSE:To apply bonding material with a predetermined film thickness and ensure the connection between an IC chip and wiring electrodes close to a step part by a method wherein a stamping jig is used for applying the bonding material to the wiring electrodes on a board and, after the tips of the jig are dipped into a bonding material layer having a certain thickness, the material is vertically stamped onto the wiring electrodes. CONSTITUTION:A square resin sink 11 is filled with paste resin 2 and a sqeegee 12 is moved to form a flat surface. A stamping jig 13 is composed of a metal plate 14 in which holes having a diameter of 0.2 mm are drilled and metal rods 15 inserted into the holes so as to form a lattice having the same pitch as wiring electrodes and to protrude less than 1mm. The tips of the metal rods 15 are dipped into the resin 2 and then lifted with the resin 2 adhering to them. The wiring electrodes 1 of a glass substrate 21 are visually aligned by using an X-Y-theta table so as to place the wiring electrodes 1 directly under the metal rods 15 and the resin 2 is transcripted onto the wiring electrodes 1. Separately, the protruding electrodes 4 of an IC chip 3 are coated with the paste resin. After the IC chip 3 is fixed by a vacuum chuck and aligned visually with the wiring electrodes 1, the resin adhering to both the electrodes is bonded to each other and cured.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、例えば半導体集積回路(以下tCと記す)で
駆動される液晶表示値!におけるように、ICチップの
突起電極を基板上の配線電極にフェースダウンで位置合
わせし、両電極に塗布したペースト状接続材により両電
極を接着させ電気的に接続するICの実装方法に関する
[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to, for example, a liquid crystal display device driven by a semiconductor integrated circuit (hereinafter referred to as tC). The present invention relates to an IC mounting method in which protruding electrodes of an IC chip are aligned face-down with wiring electrodes on a substrate, and both electrodes are bonded and electrically connected using a paste-like connecting material applied to both electrodes.

〔従来の技術〕[Conventional technology]

近年、小型、低消費電力である液晶表示による画像表示
が多方面で検討されている。これに伴い、薄型化、より
小型化の気運が高まり、液晶表示体と駆動IC等の電子
部品との接続は、微細化、かつ多端子化の傾向が強まっ
ていて、その一つの方法として、液晶表示体の透明ガラ
ス基板上に駆動IC等の電子部品を直接接続する方法が
採られて来ている。この方法は、直接接続する方法とい
う事で、Chip On Glass(略して、C0G
)とよばれる、その構成手段は、スペース効率が高く、
薄型で、より小型になるため、将来的に有望視されてい
る。しかし、この接続は、液晶表示体の画像表示電極数
が多く、例えば一画面が約240本×約480本であり
、このため配線電極も、例えば0.3Mピンチ×0.4
鶴ピンチの微細ピンチパターン化および、例えばIC1
個当たり約120本の多端子パターン化しており、直接
接続のための接続材料の塗布方法も種々検討されている
。従来技術の接続材塗布方法としては、スクリーン印刷
によるもの、デイスペンサによる等の方法が採られてい
る。
In recent years, image display using liquid crystal displays, which are small and consume low power, have been studied in many fields. Along with this, there is an increasing trend toward thinner and more compact designs, and the connection between liquid crystal displays and electronic components such as drive ICs is becoming increasingly finer and has more terminals. A method has been adopted in which electronic components such as drive ICs are directly connected onto a transparent glass substrate of a liquid crystal display. This method is a direct connection method and is called Chip On Glass (abbreviated as C0G).
), its construction means are highly space-efficient;
Because it is thinner and more compact, it is seen as promising for the future. However, in this connection, the number of image display electrodes of the liquid crystal display is large, for example, one screen is about 240 x about 480, and therefore the wiring electrodes are also 0.3M pinch x 0.4
Fine pinch patterning of Tsuru pinch and, for example, IC1
Each device has a multi-terminal pattern of approximately 120 terminals, and various methods of applying connection materials for direct connection are also being studied. Conventional methods for applying a connecting material include methods such as screen printing and a dispenser.

まず、スクリーン印刷による方法を第2図ta)(bl
を用いて説明する。すなわち、液晶表示体の透明ガラス
基板上21に、配線電極lが駆動ICの突起電極と対応
するようにパターン化されている。
First, the screen printing method is shown in Figure 2 (ta) (bl).
Explain using. That is, the wiring electrodes 1 are patterned on the transparent glass substrate 21 of the liquid crystal display so as to correspond to the protruding electrodes of the drive IC.

印刷スクリーン22には、配線電極と同一間隔のパター
ンが形成されている。このスクリーン22を配線電極パ
ターンとあらかじめ位1合わせして基板21の上方に配
!し、塗布すゐ導電性ペースト樹脂2をスクリーン上に
載せ (図a)、スクリーン22の下面が配線電極1に
付着するように荷重を加えて矢印方向にスキージ23を
移動する事により、ペースト樹脂を押出して配線電極1
上に塗布する (図b)、一方、第3図に示すように駆
動IC3の突起電極4の上にもスクリーン22を置き、
矢印方向にスキージ13を移動することにより樹脂2を
塗布する。この駆動IC3を第4図のように裏返しにし
、ガラス基板21の配線電極1に突起電極2と位置合わ
せして接着させ、樹脂2を硬化処理することにより接続
する。第5図はデイスペンサによる塗布方法を示し、図
示のようにデイスペンサ24は注射器のような構造で、
容器の内側にペースト樹脂2を充填して、図示していな
いが外から空気圧でもって、中の材料であるペースト樹
脂2を所定の場所にごく少量の所定量を押出す。
A pattern with the same spacing as the wiring electrodes is formed on the printing screen 22. This screen 22 is placed above the substrate 21, aligned in advance with the wiring electrode pattern! Then, place the conductive paste resin 2 on the screen (Figure a) and move the squeegee 23 in the direction of the arrow while applying a load so that the bottom surface of the screen 22 adheres to the wiring electrode 1. Extrude and wire electrode 1
On the other hand, as shown in FIG. 3, a screen 22 is placed also on the protruding electrode 4 of the drive IC 3,
The resin 2 is applied by moving the squeegee 13 in the direction of the arrow. This drive IC 3 is turned over as shown in FIG. 4, and is bonded to the wiring electrode 1 of the glass substrate 21 in alignment with the protruding electrode 2, and the resin 2 is hardened to connect it. FIG. 5 shows the application method using a dispenser, and as shown in the figure, the dispenser 24 has a syringe-like structure.
The inside of the container is filled with paste resin 2, and a very small amount of the paste resin 2, which is the material inside, is extruded to a predetermined place using air pressure from the outside (not shown).

ICチップ3の突起電極としては一般に/s、jンプ電
極が用いられる。第6図!allに示したのは金7sl
ンブで、表面に酸化膜32を有するシリコン基板31に
下層M配線33と上層M配線34からなる多層配線が眉
間絶縁膜35を介して形成され、上層M配線34を被覆
するパフシベーシツン膜36の開口部においてA7−N
lからなる下地金属層42を介してAuバンプ41が接
触している。 Auバンプ41の表面は中央に凹部が生
じている。第6図(blに示したのは銅43でめっきさ
れた金バンプ4で、81基板31に5lsNaの膜37
開ロ部で接触するりパッド38の上にポリイミド膜39
を介してkl−Cr−Cu構造の下地金属層44が設け
られ、レジストWA40の開口部でAuバンプ41がこ
の下地金属層44に接触している。第6図tc+に示し
たのははんだバンプで、SI基板31の上の510!膜
32の上に形成されたM配置33に、ガラスなどの絶縁
膜35の開口部において接触する下層Cr45.上層C
u46の下地金属層が設けられており、この下地金属層
の上にはんだバンプ47が形成される。第6回申)およ
びfolに示したバンプは半球状である。
As the protruding electrodes of the IC chip 3, /s and j pump electrodes are generally used. Figure 6! All shown is gold 7sl
A multilayer wiring consisting of a lower layer M wiring 33 and an upper layer M wiring 34 is formed on a silicon substrate 31 having an oxide film 32 on the surface with a glabella insulating film 35 interposed therebetween, and an opening in a puffed substrate film 36 covering the upper layer M wiring 34 is formed. A7-N in the section
The Au bumps 41 are in contact with each other through a base metal layer 42 made of l. A recess is formed in the center of the surface of the Au bump 41. Figure 6 (bl) shows a gold bump 4 plated with copper 43 and a 5lsNa film 37 on an 81 substrate 31.
A polyimide film 39 is placed on the pad 38 that contacts at the opening.
A base metal layer 44 having a kl-Cr-Cu structure is provided through the resist WA40, and the Au bumps 41 are in contact with this base metal layer 44 at the openings of the resist WA40. Shown in FIG. 6 tc+ is a solder bump 510! on the SI board 31. A lower layer Cr45. Upper layer C
A base metal layer of U46 is provided, and solder bumps 47 are formed on this base metal layer. The bumps shown in No. 6) and fol are hemispherical.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

スクリーン印刷の場合、被塗布面が平面であれば、問題
なく形成されるが、第2図のような液晶表示体のガラス
基板21とガラス基板25との段差部に駆動ICを実装
する場合、IC実装部のスペースは最少限にするため、
配線電極lをできるだけ上側基板25に近付けることが
望ましい、その結果狭い面積で段差の大きい場所におい
ては、スクリーン22が上側基板25にぶつかる。この
ため、透明ガラス基板のエツジに近い部分の配線電極に
ペースト樹脂がほとんど塗布形成されないという問題を
有していた。また、第3図のようにして樹脂ペースト2
をスクリーン印刷で塗布したICチップ3は、塗布後移
動して反転させなければならない。
In the case of screen printing, if the surface to be coated is flat, it can be formed without any problem, but when mounting the drive IC on the step between the glass substrate 21 and the glass substrate 25 of a liquid crystal display as shown in FIG. In order to minimize the space of the IC mounting section,
It is desirable to place the wiring electrode l as close to the upper substrate 25 as possible. As a result, the screen 22 collides with the upper substrate 25 in places with a narrow area and large steps. Therefore, there was a problem in that the paste resin was hardly coated on the wiring electrodes near the edges of the transparent glass substrate. Also, as shown in Figure 3, apply the resin paste 2.
The IC chip 3 coated by screen printing must be moved and reversed after coating.

この作業を行うと、突起量8i4上に設置したペースト
樹脂2が流れたり、あるいは、変形して膜厚が変わった
りするという難点がある。これは、突起電極が平坦であ
る場合とくに顕著である。しかし、第6図(a)に示し
たように中央に凹部を有する金バンブの場合は、凹部に
樹脂が加圧状態で閉しこめられ、その応力により圧力を
取去ったのら配線電極から剥がれてしま・)。
When this operation is performed, there is a problem that the paste resin 2 placed on the protrusion amount 8i4 flows or is deformed and the film thickness changes. This is particularly noticeable when the protruding electrode is flat. However, in the case of a gold bump with a recess in the center as shown in Figure 6(a), the resin is confined in the recess under pressure, and when the pressure is removed due to the stress, the wiring electrode It has peeled off.)

次に、デイスペンサの場合は、先端にあるノズル径が一
般的に直径0.2■1以上であり、ファインピッチパタ
ーンでドツトタイプ電極に対しては、厚み制御が難しく
、また、塗布回数も増え、作業時間が長くなるという欠
点を有している。直径0,2 ts以上の塗布面積に対
しては、多連デイスペンサにより、配線電極1を数個お
きにずらして設置し、数回繰り返して塗布する。樹脂吐
出し塗布方法が採られるが、さらに、微細ピンチパター
ン。
Next, in the case of a dispenser, the nozzle diameter at the tip is generally 0.2×1 or more in diameter, making it difficult to control the thickness for dot-type electrodes with a fine pitch pattern, and the number of applications increases. It has the disadvantage that it takes a long time to work. For a coating area with a diameter of 0.2 ts or more, the wiring electrodes 1 are placed at intervals of several electrodes using a multiple dispenser, and the coating is repeated several times. A resin discharge coating method is used, but in addition, a fine pinch pattern is applied.

多端子パターンに対しては適応しにくい欠点を有してい
た。
It has the disadvantage that it is difficult to adapt to multi-terminal patterns.

本発明の課題は、一つには段差のある基板上の段差部に
近接した配線電極へのペースト状接続材の塗布も容易に
できるようにし、他の一つはICチップの突起電極の端
面に塗布したペースト状接続材の電極への付着力が強く
、ICチップの反転。
One of the objects of the present invention is to make it possible to easily apply a paste-like connecting material to wiring electrodes close to a step on a substrate with a step, and the other is to make it possible to easily apply a paste-like connecting material to a wiring electrode close to a step on a substrate with a step, and to The paste-like connecting material applied to the electrodes has strong adhesion to the electrodes, causing the IC chip to flip over.

移動時に接続材の流下あるいは変形による膜厚の変化が
おきないようにし、ICチップと配線電極との接続が確
実にできるICの実装方法を提供することにある。
An object of the present invention is to provide an IC mounting method that prevents changes in film thickness due to flowing down or deformation of a connecting material during movement, and ensures reliable connection between an IC chip and a wiring electrode.

(11!11を解決するための手段〕 上記のiI題の解決のために、本発明は、ICチップの
複数の突起電極を基板との複数の配線電極をフェースダ
ウンで位置合わせし、ペースト状接続材により画電極を
接着せしめて両電極間を電気的に接続させる際に、基板
上の配線電極の位置と鏡面対称の位置に突起を有する押
印治具を配線電極への接続材の塗布に用い、各治具の先
端を一定の厚さの接続材層に浸漬したのち引上げ、垂直
方向から配線電極上に押印するものとする。また、端面
に一定の深さを持ち、外周まで延びる複数の放射状の凹
溝を有する突起電極を用い、この突起電極の先端を一定
の厚さの接続材層に浸漬したのち引上げて付着した接続
材を配線電橋上に塗布するものとする。
(Means for solving 11! 11) In order to solve the above-mentioned problem i, the present invention aligns a plurality of protruding electrodes of an IC chip with a plurality of wiring electrodes with a substrate face down, and forms a paste-like structure. When bonding the picture electrodes with a connecting material and electrically connecting both electrodes, a stamping jig with protrusions at positions mirror-symmetrical to the positions of the wiring electrodes on the board is used to apply the connecting material to the wiring electrodes. The tip of each jig shall be dipped into a connecting material layer of a certain thickness, then pulled up and stamped onto the wiring electrode from the vertical direction.In addition, multiple A protruding electrode having radial grooves is used, and the tip of the protruding electrode is dipped into a layer of connecting material of a certain thickness and then pulled up to apply the adhering connecting material onto the wiring bridge.

〔作用〕[Effect]

配線電極への接続材の塗布を、先端を一定の深さの接続
材に浸漬して接続材を付着させた押印治具を垂直方向か
ら押印することにより行えば、段差部が近接していても
障害にならず、同時に複数の配線電極へ均一に塗布する
ことができる。また、ICチップの突起電橋端面に放射
状で外周まで延びる複数の凹溝を設ける1ことにより、
その凹溝により一定の厚さに接着材が保持され、流下す
る量が少なく、スクリーンを用いないで塗布できる。
If the connecting material is applied to the wiring electrodes by dipping the tip into the connecting material to a certain depth and stamping from a vertical direction with a stamping jig to which the connecting material is attached, the stepped portions will be close together. Also, it does not become a hindrance and can be uniformly applied to a plurality of wiring electrodes at the same time. In addition, by providing a plurality of grooves radially extending to the outer periphery on the end surface of the protruding electric bridge of the IC chip,
The concave grooves maintain the adhesive at a constant thickness, reducing the amount of adhesive that flows down and allowing application without the use of a screen.

さらに、配線電極に対して加圧接着させても、接着材は
凹溝により外部に通じていて閉しこめられないので応力
が加わった状態にならず、剥離のおそれがない。
Furthermore, even if the adhesive is bonded to the wiring electrode under pressure, the adhesive communicates with the outside through the groove and is not confined, so no stress is applied and there is no risk of peeling.

〔実施例〕〔Example〕

第1図tal〜(的は本発明の一実施例のICチップの
実装工程を示し、前出の各図と共通の部分には同一の符
号が付されている。先ず、方形樹脂溜容器11にペース
ト樹脂2を充填し、スキージ12を方形容器11の対向
する二辺に乗せ、図では左から右へ移動して平坦面を出
す(図a)s次に、押印治具13を用いる。押印治具1
3は金属板14にドリルで直径0.2鶴の穴をあけ、そ
の穴にはめ合いで金属棒15を植え込み、1m以内突出
させたものである。
FIG. 1 shows the mounting process of an IC chip according to an embodiment of the present invention, and the same parts as those in the previous figures are given the same reference numerals. First, the rectangular resin reservoir 11 is filled with paste resin 2, and the squeegee 12 is placed on two opposing sides of the rectangular container 11, moving from left to right in the figure to produce a flat surface (Figure a).Next, a stamping jig 13 is used. Stamp jig 1
3, a hole with a diameter of 0.2 mm is made in the metal plate 14 using a drill, and a metal rod 15 is inserted into the hole so as to protrude within 1 m.

この金属棒15は第1図telに示すように金属板14
に配線電極と同ピンチの0.3uX0.3鶴の格子状に
埋込まれている。この治具13を矢印方向に下げて金属
棒15の先端を樹脂2に涜ける (図b)、そして治具
13を引上げると、金属棒15の先端に樹脂2が付着す
る (図c)0次に、治具13の下にガラス基板21を
、金属棒15の先端の真下に配線電極lが来るように、
X、Y、  θテーブルを用いて目視で位置合わせし 
(図e)、治具13を下ろして樹脂2を配線電極1に転
写する (図f)、この場合、上側基板25に近接した
配線電極1にも支障なく転写できる。
This metal rod 15 is attached to the metal plate 14 as shown in FIG.
They are embedded in a grid of 0.3u x 0.3 squares with the same pinch as the wiring electrodes. The jig 13 is lowered in the direction of the arrow so that the tip of the metal rod 15 touches the resin 2 (Figure b), and when the jig 13 is pulled up, the resin 2 adheres to the tip of the metal rod 15 (Figure c). Next, place the glass substrate 21 under the jig 13, so that the wiring electrode l is directly under the tip of the metal rod 15.
Visually align using the X, Y, and θ tables.
(Fig. e), the jig 13 is lowered and the resin 2 is transferred to the wiring electrode 1 (Fig. f). In this case, the wiring electrode 1 adjacent to the upper substrate 25 can also be transferred without any problem.

別にICチップ3の突起電極4にペースト樹脂を印刷ス
クリーンなどで塗布しておき、真空チャックにより固定
し、これをX−Y・θテーブルにてガラス基板21の下
面より目視で位置合わせを行ったのち、両方の樹脂を接
着させる (図g)、この後、ICチップ3を上より加
圧してその状態で硬化処理する。 実験では、治具13
の金属板14には黄銅。
Separately, a paste resin was applied to the protruding electrodes 4 of the IC chip 3 using a printing screen, etc., and this was fixed using a vacuum chuck, and this was visually aligned from the bottom surface of the glass substrate 21 using an X-Y/θ table. Afterwards, both resins are bonded together (Fig. g), and then the IC chip 3 is pressurized from above and cured in that state. In the experiment, jig 13
The metal plate 14 is made of brass.

アルミニウム等のような軟質金属を用い、金属棒15に
は、圧入時に変形しにくいステンレスamのような硬質
金属を用いた。第7図に示す別の実施例としては、治具
13の金属棒15の先端部16を、例えばシリコンゴム
、多孔質シリコンゴム、ウレタンゴム等を用いて形成す
る事により、基板tlilに転写時に樹脂のきれを良く
するようにした。また、第8図に示した治具13は、金
yA細線15をシリコンゴム17に埋込み成型したもの
である。この治具の特徴はさらにピッチが敵側化して0
.IIピッ千程度まで対応出来るようにしたものである
。転写する膜厚の制御は、樹脂溜容器11の凹部の深さ
を調整する事により数十Jja〜20〇−程度まで自由
に替えられる。第9図+a+〜(Qlは別の実施例を示
し、この場合は図aに示すようなドクターブレード19
を用い、PTFEシート1B上に1J112を流してか
らギャップ調整されたドクターブレード19を矢印方向
に動かす く図b)、これによりブレード19で樹脂2
が平坦化して、所定の厚みの樹脂2の膜を作成する事が
出来る (図c)e以後の工程は第1図(bl〜(Kl
と同様である。この場合の特徴としては、特に膜厚が薄
くて良い場合に有効である。
A soft metal such as aluminum or the like was used, and the metal rod 15 was made of a hard metal such as stainless steel am, which is not easily deformed during press-fitting. In another embodiment shown in FIG. 7, the tip 16 of the metal rod 15 of the jig 13 is made of, for example, silicone rubber, porous silicone rubber, urethane rubber, etc. The resin is now easier to clean. Furthermore, the jig 13 shown in FIG. 8 is made by embedding and molding a gold YA thin wire 15 into a silicone rubber 17. The feature of this jig is that the pitch is on the enemy side and 0.
.. It is designed to be able to handle up to about 1,000 II pitches. The thickness of the transferred film can be freely controlled from several tens of Jja to about 200 Jja by adjusting the depth of the recess of the resin reservoir 11. Figure 9+a+~ (Ql indicates another embodiment, in this case the doctor blade 19 as shown in Figure a)
After pouring 1J112 onto the PTFE sheet 1B, move the gap-adjusted doctor blade 19 in the direction of the arrow (Figure b).
The process after e (Figure c) is shown in Figure 1 (bl~(Kl
It is similar to This case is particularly effective when the film thickness can be thin.

ペースト樹脂の膜厚?よ、導電材スリ:rボ々・“/樹
脂等の場合は出来るだけ厚< 100〜200−程度が
良く、光硬化樹脂の場合は出来るだけ薄<10−〜2O
n程度が良い条件である。導電材入りエポキシ樹脂等の
場合、導電tオとしてN1.Cr、炭素1はんだ球等が
混合されており、この導電材の接触により、数Ω〜数十
Ωの低い導通抵抗で電極間が接続される。そしてエポキ
シ樹脂により、ICチップの突起電極と配線電極間に駆
動ICチップ当たり数K。
Paste resin film thickness? Conductive material pickpocket: ``/In the case of resin etc., the thickness should be as low as <100~200~, and in the case of photocuring resin, it should be as thin as <10~20~
A good condition is about n. In the case of epoxy resin containing conductive material, N1. Cr, carbon-1 solder balls, etc. are mixed, and the contact between the electrodes is made with a low conduction resistance of several ohms to several tens of ohms. Epoxy resin is used to connect the protruding electrodes of the IC chip and the wiring electrodes with several kilograms per driving IC chip.

の接着強度が得られる。光硬化樹脂の場合は、電気的接
続は、ガラス基板電極と駆動ICの突起電極とを直接接
触によって行われる0両電極間の接着は、電極間に残っ
た樹脂により行われる。詳しく言えば、電極の表面に数
十ないし数百人の微細凹凸があるため、その隙間に残っ
た樹脂によた接着力が保持される。
Adhesive strength of . In the case of photocurable resin, electrical connection is achieved by direct contact between the glass substrate electrode and the protruding electrode of the drive IC, and adhesion between the two electrodes is achieved by the resin remaining between the electrodes. Specifically, since the surface of the electrode has tens to hundreds of microscopic irregularities, the adhesive strength is maintained by the resin remaining in the gaps.

上述の実施例ではICチップの突起電極にもペースト樹
脂を塗布したが、配線電極側にのみ樹脂を塗布して両電
掻を接着させても、上記程度の導通および接着力を得る
ことができる。
In the above embodiment, the paste resin was also applied to the protruding electrodes of the IC chip, but even if the resin is applied only to the wiring electrode side and both electrodes are bonded together, the above level of conductivity and adhesive strength can be obtained. .

次にICチップの突起!極にのみベース)[脂を塗布し
た実施例の工程を第10図+8)〜fflに示す。
Next is the protrusion of the IC chip! Figure 10 +8) to ffl show the steps of an example in which fat was applied only to the base).

PTFEシート18の上にペースト樹脂2を置きドクタ
ーブレード19で平坦化する工程(図a)は、第9図と
同様である。ドクターブレードを用いる場合、第9図の
場合もそうであるが、粘度管理が重要である。粘度は、
膜厚制御に対しても影響する。
The step of placing the paste resin 2 on the PTFE sheet 18 and flattening it with the doctor blade 19 (Fig. a) is the same as that shown in Fig. 9. When using a doctor blade, as in the case of FIG. 9, viscosity control is important. The viscosity is
It also affects film thickness control.

通常、導電打入リペースト樹脂の場合、2000〜50
00cP (センチボワズ)位、光硬化樹脂の場合は5
00〜2000cP位が良い0次に、駆動用1cチフプ
3に突起1t$lj4をあらかじめ形成したものを、図
示していないが真空チャックにより固定して下げ(図b
)、平坦ペースト樹脂2に浸漬する (図c)。
Usually, in the case of conductive injection repaste resin, 2000 to 50
00cP (centiboise), 5 for photocuring resin
00 to 2000 cP is preferable Next, the drive 1c tip 3 with the protrusion 1t$lj4 formed in advance is fixed with a vacuum chuck (not shown) and lowered (Fig. b
), immersed in flat paste resin 2 (Figure c).

ICチップを引上げると突起電極の先端にシート18上
の樹脂の厚さと粘度によって決まる、例えば200μの
厚さの樹脂2が付着して残る0次にICチップ3を液晶
表示体のガラス基板21の上に形成しであるITOより
なる透明配線1掻10の上に移動し、1mlを用いて下
側から見て、基Fi21を支持するX−Y・θテーブル
を操作しながら位置合わせを行う (図e)。そしてI
Cチップ3を垂直方向に下ろし、1にg程度の圧力で先
端に樹脂2の付着した突起型8i4を配線電極10に押
圧する (図r)。
When the IC chip is pulled up, resin 2 with a thickness of, for example, 200μ, which is determined by the thickness and viscosity of the resin on the sheet 18, adheres to the tips of the protruding electrodes, and the remaining IC chip 3 is transferred to the glass substrate 21 of the liquid crystal display. Move the transparent wiring 1 to 10 made of ITO formed on top, and use 1 ml to align the position while operating the X-Y/θ table that supports the base Fi 21 when viewed from below. (Figure e). And I
Lower the C-chip 3 in the vertical direction and press the protruding mold 8i4 with the resin 2 attached to the tip against the wiring electrode 10 with a pressure of about 1 g (Figure r).

この状態のまま樹脂を硬化させる。導電材入りペースト
の場合は約170℃で30分加熱し熱硬化させる。光硬
化樹脂の場合は紫外線を約200mW /cdの照度で
数十秒照射して硬化させる。硬化後押圧力を除く。
The resin is cured in this state. In the case of a paste containing a conductive material, heat it at about 170° C. for 30 minutes to heat cure it. In the case of a photocurable resin, it is cured by irradiating it with ultraviolet rays at an illumination intensity of approximately 200 mW/cd for several tens of seconds. Excludes pressing force after curing.

ICチップの突起電橿配宜の例を第11図、第12図に
示し、いずれも(4)が平面図5(b)が側面図である
。第11図は格子状に配置した例で、突起電極4のピッ
チは0.3寵亀XQ、4m、高さは20〜50−である
、第12図は両側に配室した例で、突起電極4のピッチ
は0.1 fi位ときびしく、高さは5〜20μmであ
る。
Examples of the arrangement of protrusions on the IC chip are shown in FIGS. 11 and 12, in which (4) is a plan view and 5(b) is a side view. Fig. 11 shows an example in which the protruding electrodes 4 are arranged in a grid pattern, the pitch of the protruding electrodes 4 is 0.3 m, and the height is 20 to 50 m. Fig. 12 shows an example in which protruding electrodes are arranged on both sides. The pitch of the electrodes 4 is approximately 0.1 fi, and the height is 5 to 20 μm.

第13図ないし第15図は本発明に基づく金バンブの形
状の例で、fatがいずれも平面図、(b)がtalの
八−A腺、B−B腺、c−cNIAに沿っての断面図で
ある。これらは、ペースト樹脂が密着しやす(、樹脂内
の応力発生のないバンプ1掻である。第13図は方形、
第14図は大角形で、共にAuバンプ4!の中央部に凹
部5を有し、十字状に同一の深さの凹部6が形成されて
いる。第15図は凹部5が形成されず、十字状の凹a6
のみ形成されている。凹溝6の形成は、フォトプロセス
を用いて容易にできる、ただし、はんだバンプ47の場
合はレーザ加工等を必要とする。第16図ないし第18
図は第15図に示したAuバンプを有するICチップを
ペースト樹脂を用いて実装した例であり、第16図では
、ペースト樹脂2として導電材入り樹脂を用い樹脂厚が
約200 n以下になるように接着した。この時の透明
配線電極10とM配&1133の間の導通抵抗は数Ωな
いし数十Ωであった。樹脂2はバンプ41の凹溝6に入
り込むため、ICチップ当たり数Kgの接着強度が得ら
れ、実用的に問題がない、第17図では、耐温度、接着
強度等の信顛性をさらに向上させるため、ICチップ3
とガラス基板21の間隙に絶縁樹脂7を真空含浸したも
のである。第18図では、ペースト樹脂2に光硬化樹脂
を用いた。この場合はバンプ41と透明配線型$110
とが直接接触するように、lバンプ当たり40〜100
gの力で加圧し、加圧状態で紫外線により硬化処理した
。接着強度は、はみ出した樹脂2と凹部5および凹溝6
に残った樹脂により保持される。導通抵抗は20Ω以下
が得られた。この場合も、第17図のように間隙を絶縁
樹脂で埋めてもよい。
Figures 13 to 15 are examples of the shape of gold bumps according to the present invention, in which fat is a plan view, and (b) is a view along the 8-A gland, B-B gland, and c-cNIA of tal. FIG. These are bumps to which the paste resin adheres easily (and no stress is generated within the resin. Figure 13 is a square bump,
Figure 14 shows a large square shape with 4 Au bumps! It has a recess 5 in the center thereof, and recesses 6 of the same depth are formed in a cross shape. In Fig. 15, the recess 5 is not formed and the cross-shaped recess a6 is formed.
is formed only. The grooves 6 can be easily formed using a photo process; however, the solder bumps 47 require laser processing or the like. Figures 16 to 18
The figure shows an example in which the IC chip having the Au bumps shown in Fig. 15 is mounted using a paste resin. In Fig. 16, a resin containing a conductive material is used as the paste resin 2, and the resin thickness is about 200 nm or less. It was glued like this. At this time, the conduction resistance between the transparent wiring electrode 10 and the M wire &1133 was several ohms to several tens of ohms. Since the resin 2 enters the concave groove 6 of the bump 41, an adhesive strength of several kilograms per IC chip is obtained, and there is no practical problem. Figure 17 shows that the reliability of temperature resistance, adhesive strength, etc. is further improved. IC chip 3
The gap between the glass substrate 21 and the glass substrate 21 is vacuum impregnated with an insulating resin 7. In FIG. 18, a photocurable resin was used as the paste resin 2. In this case, bump 41 and transparent wiring type $110
40 to 100 per l bump so that there is direct contact with
It was pressurized with a force of 1.5 g and was cured with ultraviolet rays under pressure. The adhesive strength is determined between the protruding resin 2, the recess 5, and the groove 6.
It is held by the resin left behind. A conduction resistance of 20Ω or less was obtained. In this case as well, the gap may be filled with insulating resin as shown in FIG.

これに対し第19図(al、 (bl、 tc+に示す
ように凹溝のないバンプを用いた場合、第19図tag
、 fblでは凹部5にペースト樹脂が保持されるが、
接続後の導通不良が多く発生した。これは既に述べたよ
うに、凹部48の内部の樹脂が対向する配線電極との間
の空間に閉じ込められ、加圧の際の応力がそのまま残っ
て応力歪で剥離しやすいためと考えられる。
On the other hand, when bumps without grooves are used as shown in Fig. 19 (al, (bl, tc+),
In , fbl, the paste resin is held in the recess 5, but
Many continuity failures occurred after connection. As already mentioned, this is thought to be because the resin inside the recess 48 is trapped in the space between the opposing wiring electrodes, and the stress from pressurization remains, making it easy to peel off due to stress strain.

これに対し第19図fc)ではペースト樹脂の保持は悪
く接着強度は低いが、接触による導通性はかなり良い、
第13図ないし第15図に示したバンプはこれらの欠点
を除いたものである。
On the other hand, in Fig. 19 fc), the paste resin retention is poor and the adhesive strength is low, but the conductivity through contact is quite good.
The bumps shown in FIGS. 13-15 eliminate these drawbacks.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、基板上の配線電
極への接続材塗布に押印治具を用い、定の厚さの接続材
層へ治具先端を浸漬後、垂直方向から配線電極上押印す
ることにより、所期の膜厚の接続材の塗布ができ、段差
部に接近した配線電極のICチップの実装に問題がなく
なった。また本発明によれば、ICチップの突起電極の
端面に放射杖の溝を形成することにより樹脂の保持を良
好にし、押印治具と同様、一定の厚さの接続材層へ浸漬
後、配線電極に位置合わせして接続することが可能にな
り、スクリーン印刷あるいはデイスペンサの使用が不能
となった。さらに突起電極端面中央凹部と配線電極との
間の空間への接続材の閉じ込めの問題もなくなり、作業
が簡単で信転性の高いICの実装方法が得られた。
As explained above, according to the present invention, a stamping jig is used to apply a connecting material to wiring electrodes on a board, and after dipping the tip of the jig into a layer of connecting material of a certain thickness, the wiring electrode is applied from a vertical direction. By applying the top stamp, it was possible to apply the connecting material to the desired thickness, and there was no problem in mounting the IC chip on the wiring electrode close to the step. Further, according to the present invention, by forming a radiation wand groove on the end surface of the protruding electrode of the IC chip, resin retention is improved, and like the stamping jig, after being dipped into a connecting material layer of a certain thickness, wiring It is now possible to align and connect to the electrodes, making it impossible to use screen printing or dispensers. Furthermore, the problem of confinement of the connecting material in the space between the central recess on the end face of the protruding electrode and the wiring electrode is eliminated, and an IC mounting method that is easy to work with and has high reliability is obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(al〜(g)は本発明の一実施例のIC実装工
程を順次示す断面図および平面図、第2図(al、 f
blは従来のスクリーン印刷法での配線電極への樹脂塗
布の工程を示す断面図、第3図はスクリーン印刷法での
ICチップの突起電極への樹脂塗布工程を示す断面図、
第4図は第2図、第3図の工程後の接続工程を示す断面
図、第5図は従来のデイスペンサによる配線電極への樹
脂塗布工程を示す断面図、第6図(al 、 (b) 
、 telは従来rcの突起1tlliiとして用いら
れている3種のバンプの断面図、第7図、第8図は第1
図に示した押印治具の異なる実施例をそれぞれ示す断面
図、第9図ta+〜fclは第1図に示した浸γ責用樹
脂層形成の別の実施例を示す正面図、第10図!al〜
(flは本発明の別の実施例のIC実装工程を順次示す
断面図、第11図、第12図はICチップの突起電橋配
置の二つの例を示し、いずれもfalは平面図、(b)
は側面図、第13図、第14図第15図は本発明の実施
例に用いるatl類のバンプをそれぞれ示し、(4)は
いずれも平面図、(b)はそれソtllal(2)A 
−AM、 B −B線、C−C線に沿ッテの矢視断面図
、第16図、第17図、第18図は本発明の三つの実施
例により形成された接続部の断面図、第19図fat〜
(clは第13〜15図と比較のために示した311I
ffのバンプの平面図である。 1:配線電極、2:ペースト樹脂、3:ICチップ、4
:突起電極、41 : Auバンプ、5:凹部、6:凹
溝、11:樹脂溜容器、12:スキージ、13:押印治
具、14:金属板、15:金属棒、19:ドクターブレ
ード、21ニガラス基板。 代序人f1)Y上 山 口  巌 \ご+/ 第1 図 SZ図 1!311 第4図 115図 ii6図 第7図 518図 第9図 (b) 第11図 (b) ; 112図 第10図 第14図 (Q) (b) 第15図 第16図 イ3 \ ( 第17図 第19図
Figures 1 (al to g) are cross-sectional views and plan views sequentially showing the IC mounting process of an embodiment of the present invention, and Figures 2 (al, f)
bl is a cross-sectional view showing the process of applying resin to the wiring electrodes using the conventional screen printing method, and FIG. 3 is a cross-sectional view showing the process of applying resin to the protruding electrodes of the IC chip using the screen printing method.
FIG. 4 is a cross-sectional view showing the connection process after the steps shown in FIGS. 2 and 3, FIG. 5 is a cross-sectional view showing the process of applying resin to wiring electrodes using a conventional dispenser, and )
, tel is a cross-sectional view of three types of bumps conventionally used as protrusions 1tllii of RC, and FIGS. 7 and 8 are 1
FIG. 9 is a cross-sectional view showing different embodiments of the stamping jig shown in the figures, FIG. ! al~
(fl is a cross-sectional view sequentially showing the IC mounting process of another embodiment of the present invention, FIGS. 11 and 12 show two examples of the protruding electric bridge arrangement of the IC chip, and in both cases, fal is a plan view, ( b)
13, 14, and 15 respectively show the ATL type bumps used in the embodiments of the present invention, (4) is a plan view, and (b) is a solitary view.
16, 17, and 18 are cross-sectional views of connecting portions formed according to three embodiments of the present invention. , Figure 19 fat~
(cl is 311I shown for comparison with Figures 13-15.
ff is a plan view of a bump. 1: Wiring electrode, 2: Paste resin, 3: IC chip, 4
: protruding electrode, 41: Au bump, 5: recess, 6: groove, 11: resin reservoir, 12: squeegee, 13: stamp jig, 14: metal plate, 15: metal rod, 19: doctor blade, 21 Niglass substrate. 115 Figure ii 6 Figure 7 518 Figure 9 (b) Figure 11 (b); 112 Figure 10 Figure 14 (Q) (b) Figure 15 Figure 16 A3 \ ( Figure 17 Figure 19

Claims (1)

【特許請求の範囲】 1)半導体集積回路チップの複数の突起電極を基板上の
複数の配線電極をフェースダウンで位置合わせし、ペー
スト状接続材により両電極を電気的に接続させる際に、
基板上の配線電極の位置と鏡面対称の位置に突起を有す
る押印治具を配線電極への接続材の塗布に用い、各治具
の先端を一定の厚さの接続材層に浸漬したのち引上げ、
垂直方向から配線電極上に押印することを特徴とする半
導体集積回路の実装方法。 2)半導体集積回路チップの複数の突起電極を基板上の
複数の配線電極をフェースダウンで位置合わせし、ペー
スト状接続材により両電極を電気的に接続させる際に、
端面に一定の深さを持ち、外周まで延びる複数の放射状
の凹溝を有する突起電極を用い、この突起電極の先端を
一定の厚さの接続材層に浸漬したのち引上げて付着した
接続材を配線電極上に塗布することを特徴とする半導体
集積回路の実装方法。
[Claims] 1) When aligning a plurality of protruding electrodes of a semiconductor integrated circuit chip with a plurality of wiring electrodes on a substrate face down and electrically connecting both electrodes with a paste-like connecting material,
A stamping jig with a protrusion mirror-symmetrical to the position of the wiring electrode on the board is used to apply the connecting material to the wiring electrode, and the tip of each jig is dipped into the connecting material layer of a certain thickness and then pulled up. ,
A semiconductor integrated circuit mounting method characterized by stamping on wiring electrodes from a vertical direction. 2) When aligning multiple protruding electrodes of a semiconductor integrated circuit chip with multiple wiring electrodes on a substrate face down and electrically connecting both electrodes with a paste-like connecting material,
A protruding electrode with a plurality of radial grooves extending to the outer periphery with a certain depth on the end surface is used, and the tip of this protruding electrode is dipped into a layer of connecting material of a certain thickness and then pulled up to remove the attached connecting material. A method for mounting a semiconductor integrated circuit, characterized by coating on wiring electrodes.
JP23310988A 1988-09-17 1988-09-17 Semiconductor integrated circuit mounting method Expired - Lifetime JP2546351B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23310988A JP2546351B2 (en) 1988-09-17 1988-09-17 Semiconductor integrated circuit mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23310988A JP2546351B2 (en) 1988-09-17 1988-09-17 Semiconductor integrated circuit mounting method

Publications (2)

Publication Number Publication Date
JPH0281448A true JPH0281448A (en) 1990-03-22
JP2546351B2 JP2546351B2 (en) 1996-10-23

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ID=16949914

Family Applications (1)

Application Number Title Priority Date Filing Date
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JPH05291346A (en) * 1992-04-07 1993-11-05 Mitsubishi Electric Corp Semiconductor device and its packaging method
JP2007233117A (en) * 2006-03-02 2007-09-13 Denso Corp Display device and its manufacturing method
JP2011176368A (en) * 2011-06-01 2011-09-08 Fujitsu Ltd Electrode, electronic component and substrate
US8101768B2 (en) 2004-03-31 2012-01-24 Nippon Soda Co., Ltd. Cyclic amine compound and pest control agent
JP2012227423A (en) * 2011-04-21 2012-11-15 Denso Corp Mounting method of semiconductor sensor

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JPH05291346A (en) * 1992-04-07 1993-11-05 Mitsubishi Electric Corp Semiconductor device and its packaging method
US8101768B2 (en) 2004-03-31 2012-01-24 Nippon Soda Co., Ltd. Cyclic amine compound and pest control agent
USRE45364E1 (en) 2004-03-31 2015-02-03 Nippon Soda Co., Ltd. Cyclic amine compound and pest control agent
JP2007233117A (en) * 2006-03-02 2007-09-13 Denso Corp Display device and its manufacturing method
JP2012227423A (en) * 2011-04-21 2012-11-15 Denso Corp Mounting method of semiconductor sensor
JP2011176368A (en) * 2011-06-01 2011-09-08 Fujitsu Ltd Electrode, electronic component and substrate

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