JPH0278230A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent a dielectric breakdown and a deterioration of an insulation breakdown strength and to enhance electrical reliability by a method wherein a semiconductor region formed near a MISFET on a semiconductor substrate of a first conductivity type or on a main face of a well region of a second semiconductor type is connected to a gate electrode. CONSTITUTION:A transfer MISFET is constituted of the following: a gate insulating film 10 on a p<+> type semiconductor substrate 1; an n-type semiconductor region 11 forming an end part on the side of a channel region of a source and a drain; an n<+> type semiconductor region 12 forming a part other than the region 11; a gate electrode used also as a first word line 6. A capacitance element of a memory cell is constituted of a dielectric film 14, a plate electrode 15 and an n-type semiconductor region 16. An electric charge charged in the word line 6 when ions of an n-type impurity are implanted by making use of the word line 6 as a mask in order to form the region 11 and an electric charge charged in the line 6 when an n-type impurity is implanted by making use of the line 6 and a side wall 13 as a mask in order to form the region 12 are discharged to the substrate 1 via a junction diode composed of an n<+>type semiconductor region 25 and the substrate 1.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and particularly to a MISF
The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit device equipped with an ET.

[Prior art]

Conventionally, dynamic RAM is one of the semiconductor integrated circuits, and its memory cells are composed of capacitive elements and transfer MIS.
It consists of FET. And transfer MIS
The gate electrode of the FET also serves as a word line. This word line will later be the source.

It is formed using polysilicon, which has excellent heat resistance, so that it can withstand high-temperature annealing after ion implantation to form the drain. One end of the word line is connected to the source and drain of a MISFET that constitutes a word line driver.

By the way, since polysilicon has higher resistance and slower signal propagation speed than aluminum film, in recent years, after covering the word line made of polysilicon with a passivation film, the word line made of polysilicon etc. The speed of symbol propagation is increased by extending an aluminum wire parallel to the wire and connecting the aluminum wire to the word line made of polysilicon or the like through a contact hole. That is, the word line is composed of two words: a word line made of polysilicon and a wiring made of an aluminum film. The wiring made of the aluminum film is actually made by forming a passivation film on a word line made of polysilicon or the like, forming a data line on this, and then applying a second layer of passivation film on top of this. After forming, it is formed on this. The wiring made of the aluminum film here is connected to the source and drain of the MISFET of the word line driver through the connection hole. In other words, word lines made of polysilicon etc. are directly connected to the MISFE of the word line driver.
It is not connected to T and is in an electrically floating state until the aluminum wiring is formed.

Next, the source of the transfer MISFET.

The drain is formed by using the gate electrode as a mask for ion implantation and implanting n-type impurities such as arsenic (As) by ion implantation.

[Problem to be solved by the invention]

The inventor of the present invention investigated the word line of the dynamic RAM and found the following problem.

As mentioned above, the word line made of polysilicon etc. also serves as the gate electrode of the transfer MI 5FET.
Used as a mask for ion implantation when forming sources and drains. Therefore, since charged ions also fall on the word line, it is charged up. However, as described above, the word line made of polysilicon or the like is insulated from the semiconductor substrate until it is connected to the source and drain of the MISFET of the word line driver by the aluminum wiring. Therefore, the charge charged in the word line by the ion implantation remains in the word line without being discharged to the semiconductor substrate. The electric charge charged in this word line is extremely small, about 10-'' to 10-'' A/μM in terms of current. However, transfer MIS
The gate insulating film of an FET is extremely thin, with a thickness of about 350 mm, and there are pinholes in it, so the voltage applied between the gate electrode and the semiconductor substrate due to the small charge mentioned above is However, there were problems such as dielectric breakdown of the gate insulating film and deterioration of dielectric strength.

As described above, development in which the gate electrode of the MISFET is charged up during the manufacturing process also occurs when a passivation film is formed by plasma CVD after forming the gate electrode. Next, this will be explained using a gate array as an example.

The gate array consists of MISFETs arranged regularly on a semiconductor substrate.
are arranged and connected with aluminum wiring to form various logic gates. As the number of gates increases, the number of layers of aluminum wiring connecting between the MISFETs is also increasing. For this reason,
The gate electrode of a MISFET should always be connected to the source or drain of another MISFET, but when multilayer wiring is used as described above, for example, until the third layer of aluminum wiring is formed,
A gate electrode appears that is not connected to the source or drain of. Then, for example, the charges that are charged on the gate electrode when forming the first layer of passivation film covering the gate electrode will not be discharged until the third layer of aluminum wiring is formed. Further, when a first layer of aluminum wiring is formed on the passivation film and a second layer of passivation film is further formed thereon, charges are also charged on the aluminum wiring. At this time, if the first layer of aluminum wiring is connected to the gate electrode but not to the semiconductor substrate (source or drain) after it is formed, this aluminum wiring The charges charged in the gate electrode begin to flow to the gate electrode. In this way, when forming a passivation film, the gate electrode is charged, and as in the case of ion implantation, there is a problem that dielectric breakdown of the gate insulating film or deterioration of the dielectric strength voltage occurs. Semiconductor World, November 1987 issue, pages 31-37 (1987), shows that if the upper wiring is patterned by plasma etching, the wiring becomes electrically charged.
Semiconductor World).

An object of the present invention is to provide a technique that can improve the electrical reliability of a semiconductor integrated circuit device by preventing dielectric breakdown or deterioration of dielectric strength of a gate insulating film of an IMISFET.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in Suito is as follows.

In a semiconductor integrated circuit device comprising a MISFET in a predetermined region of a main surface of a semiconductor substrate of a first conductivity type or a well region of a second conductivity type of the semiconductor substrate, the semiconductor substrate of the first conductivity type or the semiconductor substrate of the second conductivity type The second conductivity type or first conductivity type provided near the MISFET on the main surface of the well region of
This is a semiconductor integrated circuit device in which a conductive type semiconductor region and a gate electrode of the MISFET are electrically connected.

[Effect]

According to the above means, the charge charged in the gate electrode of the MISFET is transferred to the PN junction formed by the semiconductor substrate of the first conductivity type and the semiconductor region of the second conductivity type on the main surface thereof, or the second conductivity type semiconductor region. The leakage into the semiconductor substrate or well region occurs through the PN junction formed by the well region of the mold and the semiconductor region of the first conductivity type on its main surface, so that the gate insulating film is damaged by the charge charged to the gate electrode. There is no possibility of dielectric breakdown or deterioration of dielectric strength. Therefore, the electrical reliability of the semiconductor integrated circuit device can be improved.

[Embodiment I of the invention]

Hereinafter, one embodiment of the present invention will be specifically described using the drawings.

In addition, in all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

FIG. 1 is a plan view showing a schematic configuration of a dynamic RAM according to a first embodiment of the present invention.

In FIG. 1, 1 is a semiconductor substrate made of P° type single crystal silicon, and 2 is a peripheral circuit area in which address buffers, decoders, word line drivers, output buffers, etc. are provided. Region 3 surrounded by a solid line is a memory cell array region. 4 is a sense amplifier area. Reference numeral 5 denotes a portion in the memory cell array region 3 where the repeated arrangement of memory cells is interrupted, that is, a region where no memory cells are provided. A first word line 6 is made of, for example, a composite film of a polycrystalline silicon film and a transition metal silicide film. A second word line 7 is made of an aluminum film. The second word line 7 is a wiring layer above the first word line 6. The first word lines 6 are shortened, and a second word line 7 connects the plurality of short first word lines 6. The second word line 7 is connected to the MISFET of the word line driver in the peripheral circuit area 2. The connection between the first word line 6 and the second word line 7 is as follows:
This is carried out on a region 5 where no memory cells are provided.

Next, an example of the structure of a memory cell will be described.

2 is a plan view of a memory cell in the memory cell array region of FIG. 1, and FIG. 3 is a sectional view taken along the line m--■ in FIG. 2.

In FIGS. 2 and 3, 8 is a field insulating film;
9 is a p-type channel stopper. The memory cell is composed of a transfer MISFET and a capacitive element,
The transfer MISFET consists of a gate insulating film 10, an n-type semiconductor region 11 forming the ends of the source and drain on the side of the channel region, and an n-type semiconductor region 12 forming the portion other than the n-type semiconductor region 11 of the source and drain. and a gate electrode which also serves as the first word line 6. 13
is a sidewall made of silicon oxide or the like. The semiconductor region 11.12 is connected to the first word line 6 or the first
It is formed by ion implantation using the word line 6 and sidewall 13 as a mask for ion implantation. The capacitive element of the memory cell is composed of a dielectric film 14, a plate electrode 15, and an n-type semiconductor region 16. 1
An interlayer insulating film 7 insulates between the plate electrode 15 and the first word line 7, and is made of silicon oxide obtained by thermally oxidizing the surface of the plate electrode 15. 18 is an interlayer insulating film that insulates between the first word line 6 and the data g20, and is made of, for example, a silicon oxide film formed by plasma CVD, a phosphorus silicate glass (PSG) film, or a boron phosphorus silicate glass (BPSG) film. It consists of a composite membrane of

19 is a connection hole. The data line 20 is made of an aluminum film. An interlayer insulating film 21 insulates the data line 20 and the second word line 7, and is made of a composite film such as a silicon oxide film, a PSG film, or a BPSG film formed by plasma CVD.

Next, the first word line 6 and the second word line 7 shown in FIG.
The specific configuration of the connecting part will be explained.

FIG. 4 is a plan view showing an enlarged connection portion between the first word line and the second word line shown in FIG. 1;

FIG. 5 is a cross-sectional view taken along the line ■--■ in FIG. 4.

As shown in FIGS. 4 and 5, the connection between the first word line 6 and the second word line 7 is made on the region 5 where no memory cells are provided. A relay conductive film 23 made of an aluminum film of the same layer as the data line 20 is provided between the first word line 6 and the second word line 7 on the region 5, and the second word line 7 is connected to the first word line 6.

24 is a connection hole that connects the second word line 7 to the relay conductive film 23, and 19 is a connection hole that connects the relay conductive film 23 to the first word line 6. The region 5 on the main surface of the semiconductor substrate 1 where no memory cells are provided is covered with a field insulating film 8, but the field insulating film 8 is not formed under the connection hole 19, and the p-type Channel stopper 9 is also not formed. In the portion where the field insulating film 8 is not formed, a thin silicon oxide film, which is a gate insulating film 10 (see FIG. 3), is formed. Then, this thin silicon oxide film is removed to form a connection hole 22, through which the first word line 6 is connected to the surface of the semiconductor substrate 1. On the surface, there is an
There is an n3 type semiconductor region 25 formed by diffusing type impurities (for example, phosphorus).

A PN junction diode is configured between the n-type semiconductor region 25 and the p-type semiconductor substrate 1, but when the dynamic RAM is in operation, the voltage applied to the first word line 6 is connected to the semiconductor substrate 1. Since the potential is the same as or higher than , the PN junction diode is always reverse biased, and the first word line 6 and the semiconductor substrate 1 are never short-circuited.

From the configuration described above, in order to form the n-type semiconductor region 11 of the transfer MISFET shown in FIGS. 2 and 3, an n-type impurity (for example, phosphorus) is implanted using the first word line 6 as a mask for ion implantation. The charges charged to the 17th word line 6 during ion implantation and n
When ion implanting an n-type impurity (for example, arsenic) using the first word line 6 and sidewall 13 as an ion implantation mask to form the ゛-type semiconductor region 12, the charge charged in the first word line 6 is as follows. The semiconductor substrate is discharged through a PN junction diode constituted by the n-type semiconductor region 25 and the p-type semiconductor substrate 1 shown in FIGS. 4 and 5.

Therefore, a strong electric field is not generated between the semiconductor substrate 1 and the first word line 6 on the gate insulating film 10 of the transfer MISFET due to the charge on the first word line 6. Dielectric breakdown of the film 10 or deterioration of dielectric strength can be prevented.

[Embodiment 2 of the Invention] FIG. 6 is a plan view of a gate array according to Embodiment 2 of the present invention.

In FIG. 6, 30 is a bonding pad, 31 is a human output buffer circuit area, and 32 is a basic cell column in which basic cells 32A are arranged in a column. One basic cell 32A is composed of, for example, two p-channel MISFETs and two n-channel MISFETs.

Next, a specific configuration of one basic cell will be explained.

FIG. 7 is an enlarged plan view of one basic cell 32A in the gate array shown in FIG. 6, and FIG. 8 is a cross-sectional view taken along the section line ■-■ in FIG. be.

In FIGS. 7 and 8, 33 is an n-type well.

38 is a p-type well, and 34 is a field insulating film.

A P-type channel stopper 44 is provided below the field insulating film 34 of the P-type well 38. Basic cell 32
The p-channel MIS FET of A (FIG. 6) has a gate insulating film 35 made of a silicon oxide film with a thickness of about 350 mm, and a gate electrode 36 made of, for example, an n-type polycrystalline silicon film. The p-type semiconductor region 37 serves as a source and a drain. n-channel MISFET
is a gate insulating film 35, a gate electrode 36, a source,
It is composed of an n'-type semiconductor region 39 which becomes a drain. The p'' type semiconductor region 37 and the n'' type semiconductor region 39 are formed by ion implantation using the gate electrode 3G as an ion implantation mask.A first layer of interlayer insulation is formed on the gate electrode 36. It is covered with a film 40. The interlayer insulating film 40 is made of, for example, a silicon oxide film formed by plasma CVD.

Wirings 51 to 57 are made of a first layer of aluminum film and extend on the interlayer insulating film 40. The wiring 51 is a wiring for feeding a potential Vcc, for example, 5V, and is connected to the p'-type semiconductor region 37 of the p-channel MISFET via the connection hole 41. The wiring 52 has a potential of VsS
For example, it is a wiring for feeding Ov, and is connected to the n-type semiconductor region 39U of the n-channel MISFET via the connection hole 41. Wiring 53 is P channel MI
This is a manual signal wiring for the SFET and n-channel MISFET, and is connected to the gate electrode 36.

The wiring 55 is an input signal wiring for a p-channel MISFET and an n-channel MISFET different from those described above, and is connected to a gate electrode 36 different from those described above.

The wiring 56 is a wiring for discharging charges flowing into the gate electrode 36 from the semiconductor substrate during the manufacturing process described later, and is connected to the two gate electrodes 36 and also connected to the semiconductor substrate 1. Wiring 56 of semiconductor substrate 1
The field insulating film 34 is not formed on the portion to which the two are connected, and a p' type semiconductor region 45 is provided below it. This p' type semiconductor region 45 is formed in the same process as the p' type semiconductor region 37 which becomes the source and drain.

The wiring 56 and the p' type semiconductor region 45 are provided in all basic cells 32A. The wiring 57 is a human signal wiring, and one end is connected to a wiring 61 to be described later, and the other end is connected to the source or drain of a MrSFET (not shown). A second interlayer insulating film 42 is provided on these wirings 51 to 57. Interlayer insulation film 42
is formed by laminating a silicon oxide film and a PSG film or a BPSG film formed by, for example, a plasma CVD method. Reference numeral 61 denotes a wiring made of a second layer of aluminum film, and extends over the glabella insulating film 42. The signal wiring 57 and the signal wiring m54 are connected.

When forming the interlayer insulating film 42 on the wirings 51 to 57, the wirings 51 to 57 are charged. At this time, the charges charged in the signal wirings 54 and 55 enter the gate electrode 36, but are discharged from the wiring 56 to the 11-type well 33 via the p' type semiconductor region 45. By providing the wiring 56 and the P' type semiconductor region 45 in this way,
Charges flowing into the gate electrode 36 when forming the interlayer insulating films 40 and 42 using the plasma CVD method are transferred to the n-type well 33.
Therefore, it is possible to prevent the gate insulating film 35 from dielectric breakdown or dielectric breakdown voltage from deteriorating due to the charges charged in the gate electrode. The wiring 56 for discharging may be provided on the p'' type well 38, and an n' type semiconductor region may be provided in the p- type well 38 instead of the p' type semiconductor region 45.

As described above, according to Example 1 or Example H, a predetermined region of the main surface of the semiconductor substrate 1 of the first conductivity type or the n-type well 33 of the second conductivity type of the semiconductor substrate 1 MISFET for configuring memory cells (Example I)
or M for configuring logic gates such as NAND gates and NOR gates other than the popular cover sofa.
A semiconductor integrated circuit device equipped with an I S FET (Example 2) is installed, and the semiconductor substrate 1 or the n-type well 3 is
The semiconductor region of the second conductivity type or the first conductivity type provided near the MISFET on the main surface of No. 3 (the n-type semiconductor region 25 of the embodiment A wiring (first word line 6 itself) that is made of a conductive film in the same layer as the word line 6) and connects the n-type semiconductor region 25 and the gate electrode (first word line 6), or The conductive film is one layer above the gate electrode 36 of Example H and the semiconductor region (Example
By providing a wiring (wiring 56 of Example H) connecting the p° type semiconductor region 45) and the gate array 36, the gate electrode of the MISFET (first word,
6 or gate electrode 36), the first conductivity type semiconductor substrate 1 and the semiconductor region (
The n-type semiconductor region 25 of the embodiment) or the well region (the n-type well 3 of the embodiment
3) and the semiconductor region on its main surface (the p-type semiconductor region 45 of Example 2), leaks into the semiconductor substrate or well region, so that the charge charged in the gate electrode leaks into the semiconductor substrate or well region. The gate insulating film (Example I is the gate insulating film 10°; Example I is the gate insulating film 3)
5) will not cause dielectric breakdown or deterioration of dielectric strength voltage. Therefore, the electrical reliability of the semiconductor integrated circuit device can be improved. Although the present invention has been specifically described above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

The electrical reliability of the semiconductor integrated circuit device can be improved by preventing dielectric breakdown of the gate insulating film of the MISFET or deterioration of the dielectric strength.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a schematic configuration of a dynamic RAM according to the embodiment (2) of the present invention. 2 is a plan view of the memory cells in the memory cell array area of FIG. 1. FIG. 3 is a cross-sectional view taken along the line ■-■ of FIG. 2. FIG. FIG. 5 is a plan view showing an enlarged connection between the first word line and the second word line, and FIG. FIG. 6 is a plan view of a gate array according to Example 2 of the present invention. FIG. 7 is an enlarged plan view of one basic cell in the gate array shown in FIG. FIG. 8 is a cross-sectional view taken along the line ■--■ in FIG. 7. In the figure, 6...first word line, 7...second word line,
10... Gate insulating film, 11... N-type semiconductor region,
12... n-type semiconductor region, 16... n-type semiconductor region, 20... data line, 23... relay conductive film, 25
...n" type semiconductor region, 33...n° type well, 3
5... Gate insulating film, 36... Gate electrode, 37.
...P' type semiconductor region, 38...p- type well, 39
. . . n° type semiconductor region, 40. 42 . . . interlayer insulating film, 45 . . . p ゛ type semiconductor region. Figure 1 Figure 3 Figure 5

Claims (1)

[Claims] 1. A semiconductor substrate of a first conductivity type or a second conductivity type of the semiconductor substrate
In a semiconductor integrated circuit device including a MISFET in a predetermined region of a main surface of a well region of a conductivity type, the MISFET is provided in the vicinity of the MISFET of the semiconductor substrate of the first conductivity type or the main surface of the well region of the second conductivity type. A semiconductor integrated circuit device, characterized in that a semiconductor region of a second conductivity type or a first conductivity type is electrically connected to a gate electrode of the MISFET via a PN junction. 2. A semiconductor integrated circuit characterized in that the semiconductor region and the gate electrode of the MISFET are connected by a wiring made of a conductive film in the same layer as the gate electrode or a conductive film in one layer above the gate electrode. Device.