JPH0278980A - Semiconductor integrated circuit, mount substrate, and inspecting method - Google Patents

Abstract

PURPOSE:To obtain an inspection result which is easily analyzed by latching test data which is outputted from an IC to an external interface part and latching test data which is inputted from the external interface part. CONSTITUTION:Optional test data is scanned in the output latch circuit 6 of an IC circuit 1a according to a determined procedure and the latched test data is outputted to the interface part. When the clock CK1 of the input latch circuit 4 of an IC circuit 1b is turned on, test data from the interface part is inputted to the circuit 4 of the IC circuit 1b. Then scan-out operation is performed as to the circuit 4 and the input test data is sent to the circuit 6 of the IC circuit 1b and latched. Then the data is sent to the latch control part 8 of a next IC circuit 1c and sent data is inputted to a next IC circuit 1d from a terminal 11b. Consequently, whether or not the function of the interface part is normal can be inspected.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a method for connecting a plurality of semiconductor integrated circuits to a substrate, and an interface portion provided on the substrate for connecting each semiconductor integrated circuit. Semiconductor integrated circuit suitable for testing functionality.

The present invention also relates to a board on which the same is mounted, and an inspection method thereof.

[Prior Art] Generally, a plurality of semiconductor integrated circuits are often mounted on a substrate.

Usually used when mounting semiconductor integrated circuits on a board.

Before that, each semiconductor integrated circuit and substrate are inspected.

What is the testing method for this semiconductor integrated circuit?

Various proposals have been made. For example, JP-A-61-15587
No. 4 discloses a method and apparatus for testing internal functions of a semiconductor integrated circuit using a scan path method.

Furthermore, Japanese Patent Application Laid-open No. 161469/1983 describes a technology related to semiconductor integrated circuits, in which a latch function is provided at the front stage of the input buffer, and the skew of the input signal is eliminated by the latch, and the skew of the input signal is eliminated. A system has been disclosed that allows accurate functional testing of logic circuits of semiconductor integrated circuits.

On the other hand, continuity tests are also performed on the board itself by means such as bringing probe pins into contact with appropriate locations on the wiring pattern.

[Problem to be solved by the invention] By the way, there is a board on which a semiconductor integrated circuit is mounted.

To ensure proper operation, it is necessary to test that the semiconductor integrated circuit is accurately connected to the conductive patterns on the substrate.

However, conventional inspection methods and devices, including the techniques disclosed in the above-mentioned publications, are all techniques for semiconductor integrated circuits and the substrate itself, and are not applicable to the interface of the substrate with the semiconductor integrated circuit mounted thereon. No consideration was given to departmental inspections.

For example, by applying a test method for logic circuits of semiconductor integrated circuits, test signals are applied to the input terminals of the board on which the semiconductor integrated circuit is mounted, or to the input pins of the mounted semiconductor integrated circuit. It is conceivable to check whether the interface section is functioning normally by checking what kind of signal is output to the output terminal of the semiconductor integrated circuit or the output pin of the semiconductor integrated circuit.

However, in this method, a plurality of mounted semiconductor integrated circuits are connected to each other via an interface section.

Because it is organically connected to the input signal.

The result of the operation of each semiconductor integrated circuit appears as an output signal. Therefore, it is very difficult to analyze from the output signal whether the interface section is functioning in a normal connected state.

On the other hand 1. ! ! It is conceivable to apply a continuity test method for the board itself to check the continuity between each pin of each mounted semiconductor integrated circuit.

However, this method has a problem in that it is not easy to bring the probe pin into contact with a large number of pins accurately and reliably. For example, it is conceivable to provide a jig to position the probe pins, but since the jig must be manufactured with high precision, it is time consuming and expensive. Moreover, there is also the inconvenience of requiring a jig for each substrate with a different pattern. .

Furthermore, in this substrate inspection method, the logic circuit of the semiconductor integrated circuit may operate due to the signal applied to the pin. Therefore, it is necessary to perform the inspection with consideration to prevent such an operation from occurring. However, it is practically difficult to inspect a board with complicated wiring connections while taking such considerations into consideration, from the viewpoint of reliability of inspection results, work efficiency, etc.

Therefore, conventionally, after mounting a semiconductor integrated circuit, testing to determine whether the interface section of the board functions normally is often omitted.

The present invention provides a substrate on which a semiconductor integrated circuit is mounted,
This is used when testing whether or not the interface section functions normally. This was done to solve the above problem.

The purpose is to be able to perform inspections without using special jigs or operating the internal logic circuits of semiconductor integrated circuits, and to efficiently produce test results that are highly reliable and easy to analyze. It is an object of the present invention to provide a semiconductor integrated circuit, a mounting substrate, and an inspection method suitable for obtaining the semiconductor integrated circuit.

[Means to solve the problem] The present invention is a means to solve the above problems.

In a semiconductor integrated circuit having a logic function section that performs a logic operation, and one or more input signal lines and output signal lines connected to the logic function section, a semiconductor integrated circuit having one or more input signal lines and output signal lines connected thereto in correspondence with each of the input signal lines and output signal lines. The semiconductor integrated circuit is characterized by comprising a latch function section that latches test data output from the semiconductor integrated circuit to an external interface section and also latches test data input from the external interface section.

Furthermore, the semiconductor integrated circuit of the present invention sends output test data to each of the latch function sections to cause them to latch, instructs them to output to the outside, and takes in data from the outside to test 1. It is preferable to include a latch control unit that instructs to latch the data and to transfer the latched data.

In the present invention, each of the above latch function sections.

It is preferable to connect serially so that latched data can be sequentially transferred to a subsequent stage, and to connect the first and last latch function sections to the latch control section to form a scan loop. In this case, an output latch function section that outputs test data to the outside is connected to the output signal line, and an input latch function section that takes in data to test 1 input from the outside is connected to the input (line 6). In other words, the latch function section is separated into an input latch circuit and an output latch circuit, and each is connected to the corresponding signal line.However, the function of the latch function section itself is the same whether it is for input or output, so they are the same. The following configuration is sufficient.

Further, it is preferable that each latch function section is provided with a switch 1 function for disconnecting the logic function section from each input signal line and output line 13 during inspection.

One example of a circuit having such a function is a circuit using a master flip-flop and a slave flip-flop.

Next, according to the present invention, a substrate is constructed on which a plurality of the above semiconductor integrated circuits are mounted. This board forms an interface section mainly consisting of conductor wiring, and is provided with wiring for transmitting test data for testing the interface section, external control signal wiring and terminals for controlling the testing. The semiconductor integrated circuit is mounted thereon.

In this board, it is preferable to provide a signal line that serially connects the scan loop of each of the 4T-conductor integrated circuits mounted above.In this case, each of the mounted semiconductor integrated circuits is It is also possible to divide the circuit into groups and provide a signal line for serially connecting the gaps and loops of the conductor integrated circuits constituting the group for each group.

Note that two or more scan loops may be provided within the semiconductor integrated circuit.

Furthermore, as the above-mentioned semiconductor integrated circuit, one without a latch control section is mounted on the substrate, and the scan loops of each semiconductor integrated circuit are serially connected. It may also be configured to control a latch function section of the circuit.

The present invention also provides a method for inspecting a board on which the semiconductor integrated circuit is mounted.

This inspection method is characterized by the following steps.

■For each latch function unit connected to the output signal line of the semiconductor integrated circuit on the output side, among the semiconductor integrated circuits that sandwich the interface unit for inspection, Test data is sequentially transferred and latched via other latch function units.

(2) The latched test data is then sent from each latch function section to the interface section via the output signal line.

(2) On the other hand, the test data input from the interface section is taken into each latch (hyperactive section) connected to the input signal line of the semiconductor integrated circuit serving as the input side.

(7i) Next, this is sequentially transferred via other latch function units on the scan loop subsequent to these.

(Yes) The function of the interface section is evaluated by comparing the pattern of test data sequentially output from the latch function section at the last stage with the test data given first or with a preset expected value.

The present invention also provides a method for testing a substrate on which a plurality of the semiconductor integrated circuits described above are mounted, in which scan loops formed in the mounted semiconductor integrated circuits are serially connected. In this method, among the steps of the above-mentioned inspection method, (2), (2) and (2) are the same, so only CD and (2) are shown.

(For each latch function unit connected to the output signal line of the semiconductor integrated circuit on the output side among the semiconductor integrated circuits that sandwich the interface unit for the purpose of D inspection.

Including other semiconductor integrated circuits, the test data is sequentially transferred and latched via other latch function units located at the preceding stages on the scan loop.

(2) Then, this is sequentially transferred via other latch function units in subsequent stages on the scan loop including other semiconductor integrated circuits.

As a further development of the test method described in L, test data is serially transferred to the output latch function section of each semiconductor integrated circuit and latched.

There is a method of inputting the signal to the input latch function section of each other semiconductor integrated circuit through an interface section, and then serially transferring and taking out the input signal for inspection.

Note that the interface section to be inspected in the present invention mainly refers to the conductor wiring that interconnects the input pins and output pins of each semiconductor integrated circuit mounted on the board, but is not limited to this. -Includes electronic circuit components and combinatorial logic circuits that exist between the pins. This inspection includes not only the quality of the interface part itself, but also the quality of the connection with the semiconductor integrated circuit.

Check whether the interface section functions properly.

[Function] As described above, the present invention outputs test data to the interface section using the latch function section provided on the input/output signal line of each semiconductor integrated circuit mounted on the substrate, and also outputs test data to the interface section. Test data can be obtained from the Uke.

In this case, test data is externally set and latched to the latch function section connected to the output signal line.
By outputting this to the non-interface section, output data can be formed regardless of the operation of the logic function section within the integrated circuit. 9. Also, by taking out the des+- data input from the interface section to the outside from the latch function section, test results can be obtained without being influenced by the logic function section inside the integrated circuit.

By the way, each latch function is 1mN serially.
By doing *'j, output test data and input test data can be serially transferred. This allows for fewer wires and terminals.

It is possible to send data to the target output signal line, while receiving and receiving test data from the target input signal line. .

``Therefore, 5. Prints with many large-scale semiconductor integrated circuits'' ↓Inspection of the interface parts on the board does not require any special jigs, and it also eliminates labor-intensive work such as contacting probe pins. Since it is not necessary, it can be carried out efficiently.

In addition, as mentioned above, since the inspection can be performed independently of the operation of the internal logic function section, highly reliable
-Data can be obtained. Moreover, since complex logical operations are not involved, analysis of test data becomes easy.
, [Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an embodiment of a semiconductor integrated circuit according to the present invention.

The semiconductor integrated circuit 1 of the embodiment shown in FIG. 1 includes a logic function section 5 (circuit configuration not shown) that performs logic operations, and a plurality of input signal lines 51 and output signal lines 52 connected thereto. , a terminal 2 provided at the ends of these signal lines 51 and 52, an input buffer 3 inserted and connected to the input signal line 51, and an output buffer 7 connected to the output signal line 52. There is.

The semiconductor integrated circuit 1 also includes an output latch circuit 6 that latches and outputs test data to be outputted to the outside, an input latch circuit 4 that latches test data that is inputted from the outside, and an output latch circuit 6 that latches test data that is outputted to the outside. For input latch circuit 4.

A latch control circuit 8 that sends test data, receives and receives latched test data from the outside, and controls output of the test data to the outside; The input latch circuits 4 and the output latch circuits 6 are serially connected in a loop.

It has a scan loop signal line 80 that transmits data to test 1 and also transmits a control signal.

The latch control circuit 8 instructs the input latch circuit 4 to take in test data from the outside, and outputs a clock signal that instructs the output latch circuit 6 to output test data to the outside. Also, regarding the above output latch circuit.

It instructs the input latch circuit to latch the output test data from the scan loop signal line 80 (hereinafter referred to as scan-in), and also transfers the test data taken in from the outside and latched to the scan loop signal line 80. (hereinafter referred to as scan-out)
Outputs a scan trigger signal that instructs. The input latch circuit 4 is as follows.

In this embodiment, the output latch circuit 6 is provided after the input buffer 3, while the output latch circuit 6 is provided before the output buffer 7. Further, both the input latch circuit 4 and the output latch circuit 6 are constructed of flip-flops.

FIG. 2 shows the configuration of the input and latch circuit 46.Furthermore, FIG. 3 shows its detailed circuit configuration, and FIGS.
Figure B shows a truth table during operation of this flip-flop.

In FIG. 2, the input latch circuit 4 includes a master flip-flop (hereinafter abbreviated as master FF) 41 and a slave flip-flop (hereinafter abbreviated as slave FF) 42.

As shown in Figure 3, the master FI? 41 is an inverter@path 411, an OR circuit 412 and a NAND circuit 413
It is made up of. The slave FF 42 includes an inverter circuit 421 . OR circuit 422 and NAND circuit 423
It is made up of. This circuit is well known as a circuit constituting a flip-flop. Therefore, description of the circuit configuration will be omitted.

In the above-mentioned master FF4], the contents of the D signal are normally taken in by the clock signal CK, and during scan-in,
The content of the DSI signal is the scan trigger signal S '1” B
captured by. The captured content is output signal Q
The data is output to the slave FF 42 and becomes input data to the slave FF 42.

In other words, the master FF 41 has a clock signal CK of 'H'.
' When the scan trigger signal STB is at the l L 1 level, the contents of the data input signal DSI are taken in, and when the scan trigger signal STB is at the l L 1 level, the contents of the scan-in data signal DSI are taken in.

When both the clock signal CK and the scan trigger signal 5TI3 are in the 'off' state, the state continues to be maintained. When the clock signal CK and the scan trigger signal 5TI3 are in the 1-on state at the same time, and the data input signal and the scan-in data signal DSI show the same level, the state of that level is captured, but if there is a mismatch, Time becomes uncertain.

On the other hand, the slave FF 42 takes in the contents of the master FF 41 using the scan trigger signal STA.

Output as scan out signal DSO.

The slave FF 42 is configured so that the scan 1-rigger signal STA is
When it is at L1 level, it takes in the contents of the master FF 41, and when it is at 'H' level, it continues to hold the state and outputs it as a scan out signal DSO.

In other words, in this embodiment, the input latch circuit 4 is connected to the master F
By configuring F and slave FF, it has a switch function to switch whether the logic function section 5 is in a through state or disconnected from the input signal line, and a switch function to take in test data from the terminal or to output test data. The latch function section has a selection switch function for selecting whether to latch the data, and a storage function for holding data.

Note that this point also applies to the output latch circuit 6, which has a switch function to switch whether the logic function section 5 is in a through state or disconnected from the output signal line, and outputs the test data latched to the terminal. A selection switch function for selecting whether to send the latched input data to the next output latch circuit, and a storage function to hold the data are realized.

Although the configuration and operation of the one-input latch circuit 4 have been described above, the output latch circuit 6 also has the same circuit configuration as the human latch circuit 4 and operates in the same manner. Therefore, the explanation will not be repeated.

Next, a scan loop formed by serially connecting the above-described input latch circuit 4 and output latch circuit 6 through a B return line 80 will be described with reference to FIG.

In FIG. 5, a scan trigger signal STB for the master FF 41 and a scan trigger signal S for the slave FF 42 are shown.
TA is commonly input to all input latch circuits 4 and output latch circuits 6.

In addition, the clock signal for capturing the input data signal during normal operation is connected to the clock signal CKI commonly input to all input latch circuits 4 and the clock signal CKO commonly input to all output latch circuits 6. has been done. Note that explanations of the data input signal and output signal Q of the master r''F 41 will be omitted.

In the scan loop shown in FIG. 5, the semiconductor integrated circuit 1 includes 1, 2.3...n input latch circuits 4 and 1, 2.3...m output latch circuits 6. Assuming that It is connected to the scan-in data signal DSI' of the input latch circuit 4. In this way, all the input latch circuits 4 and output latch circuits in the semiconductor integrated circuit 1 can be Connect circuit 6 serially.

Note that there is no need to distinguish between the input latch circuit 4 and the output latch circuit 6 in the order of serially connected latch circuits, and the order is the same even if they are mixed.

Next, the latch control circuit 8 will be explained with reference to FIG.

The latch control circuit 8 includes 1, an input buffer circuit 84, an output buffer circuit 87. Inverter circuit 81. AND circuit 82
．． , and an OR circuit 83. This latch control circuit 8 inputs the scan trigger signals STB and STA from the terminal 2 of the semiconductor integrated circuit 1, and generates inverted signals at the input buffer circuit 84, respectively.
A scan trigger signal STB for the master r''F 41 and a scan trigger signal STA for the slave FF 42 are created.

The scan-in data signal DSI for the serially connected first-stage latch circuit is connected to terminal 2 of the semiconductor integrated circuit 1 or "
Either one of the scan-in data (a SID) and the scan-out data signal DSO output from the serially connected final stage latch circuit is selected and output by the scan mode signal SIM. Scan-out data signal/DSO of stage latch circuit output
teeth.

The signal is output to terminal 2 of semiconductor integrated circuit 1 via output buffer circuit 87 .

The clock signal CKI for the input latch circuit and the clock signal CKO for the output latch circuit are generated from the clock signals CKI and CK2 from the terminal 2 via the input buffer circuit 84, respectively.

In the above circuit configuration, the scan-in operation for the input latch circuit 4 and the output latch circuit 6 in the semiconductor integrated circuit 1 will be explained with reference to FIG.

When the scan mode signal SIM is at the 'I-I' level, scan signals are input alternately 1) Enable signal ST
A and STB sequentially capture the contents of the scan-in data signal SID into the input latch circuit 4 and the output latch circuit 6.

By the first scan trigger signal STB.

The master 1”F of the first stage latch circuit is connected to the cell 1- (Q
l), - Next, the content A of the master FF is transferred to the slave FF by the second scan trigger signal STA (DSOI). 7. Next, the master FF of the first stage latch circuit is activated by the second scan trigger signal STB.
The contents B of the first-order input data signal SID are set to the first-order input data signal SID, and the contents A of the slave FF of the first-stage latch circuit are set to the master FF of the second-stage latch circuit (
Q2).

Next, the contents of the master FFs of the first and second stage latch circuits (
B, A) are transferred to slave FFs (DSO
I, DSO2).

Similarly, by inputting scan 1-rigger signals STB and STA for the number of latch circuits, the contents of scan-in data <a number SID can be scanned into all the latch circuits.

At this time, the normal clock number 9113 CK 1.

CK 2 is set not to output ('L level).

To scan out the contents of all latch circuits, set the scan mode signal SIM to the "■," level, and apply the scan trigger signals STA and STB in the same way as during scan-in, to scan out the scan-out data signal S.
The contents of all latch circuits can be output as OD.

The purpose of setting the scan mode signal to L' level during scan out mode is to reset the contents of all latch circuits from scan alarm 1 to end to the same value as at the start of scan out. be.

Also, during normal operation (other than during scan-in and scan-out), the clock signal CK1. and CK2 to I-1
' By setting this level, the latch circuit can be set to the through state.

Next, the inspection of the interface section by the semiconductor integrated circuit 1 of this embodiment will be explained.

Assume now that among multiple semiconductor integrated circuits mounted on a board, the output of one is connected to the input of the other via the interface section of the board.

Check whether the interface between the two is functioning properly.

First, test data is scanned into the output latch circuit 6 of the semiconductor integrated circuit 1 on the output side by the scan data signal DSI of the scan loop signal line 80 by the above-mentioned hand Jli.

In this case, data is sent serially on a scan loop that also includes the one-input latch circuit 4. Therefore, the TEST data is formed as serial data so that a single value is set in each output latch circuit 6. For example, if four input latch circuits 4 are connected, and then four output latch circuits are connected, the first 4 bits of the 8-bit serial data will have the desired value. Set it as follows.

Note that the connection order of the output latch circuit and the input latch circuit differs depending on the semiconductor integrated circuit.

Both are often mixed and connected serially, so
The test data is set taking this connection order into account.

The value to be set is '1' or '0', but which one to set is determined by taking into consideration the logic circuits etc. included in the interface section.

Note that the test data is generated in a data creation device (not shown) provided outside the board, and sent to the latch control circuit via the conductor wiring of the saw board.

From here, it is sent to the scan loop as described above.

Assuming that target test data is set in each output latch circuit as described above, this data is first sent from the terminal of the semiconductor integrated circuit to an external interface section.

On the other hand, in the semiconductor integrated circuit serving as the input side, test data is input through the terminal connected to the interface section, and is taken in and latched by the input latch circuit according to the above-described procedure. Thereafter, in accordance with a scan-out instruction from the latch control circuit, the test data latched in each input latch circuit is output onto the scan loop and sequentially sent to the latch control circuit via the subsequent latch circuit.

The latch control circuit sends this data to the data creation device that created the test data described above. Then, this data creation device compares the created data with the data passed through the interface section to determine whether the interface section is functioning normally, that is, whether the connection state with the semiconductor integrated circuit is good or not. Determine.

As explained above, according to this embodiment, arbitrary data can be set in the latch circuit provided immediately before and after the human output buffer circuit with a small number of control signals without being affected by the internal state of the semiconductor integrated circuit. It is possible, and
It can be taken out. Therefore, there is an effect that failure detection of an input/output interface of a board on which a semiconductor integrated circuit is mounted is facilitated.

In this embodiment, the human output latch circuit of the semiconductor integrated circuit is made into a series of serially connected scan circuits, but it is possible to add a scan address signal and increase the scan-in data, scan alarm, and data signal. It is easy to understand that this allows a scan loop configuration in which a plurality of sets are serially connected, and a scan operation can be performed in a short time.

Furthermore, although the latch circuit of this embodiment has a scan circuit configuration using a master FF and a slave FF, by using an edge trigger type flip-flop, it can achieve the same function as the previous embodiment with one type of scan trigger signal. realizable.

Next, an embodiment of a board on which a plurality of semiconductor integrated circuits are mounted will be described with reference to FIG.

In the embodiment shown in FIG. 8, a plurality of semiconductor integrated circuits 18 to 1f having the same configuration as that shown in FIG. 1 are mounted on a printed circuit board 10.

In this embodiment, a scan-out data signal SOD of a semiconductor integrated circuit 1 and a scan-out data signal SID of another semiconductor integrated circuit 1 are connected via a data line 3 12, and a plurality of semiconductor integrated circuits 1 and It has a serially connected scan loop configuration. The scan-in data signal y-s Ip of the first-stage semiconductor integrated circuit 1a is connected to the terminal 11a of the printed circuit board 10, and the scan-in data signal SOD of the final-stage semiconductor integrated circuit 1f is connected to the terminal 11b of the printed circuit board 10. It is configured to be connected to. Also, scan trigger No. 4a S "I'A".

STB and clock signals CKI, CK2 are commonly connected to each of the semiconductor integrated circuits 18 to 1f, and
It is connected to the terminal 11c of the printed circuit board 1o.

Next, the inspection method in this embodiment will be explained.

Now, let's focus on semiconductor integrated circuits 1a and 1b. It is assumed that an interface section (not shown) exists between the two from the former to the latter.

First, arbitrary test data is scanned into the output latch circuit 6 (not shown in FIG. 8, see FIGS. 1 to 3) of the semiconductor integrated circuit 1a using the above-described procedure. Then, the latched test data is output to the interface section.

- On the other hand, the input latch circuit 4 of the semiconductor integrated circuit 1b (the eighth
The clock CKI (not shown in the figure, see FIGS. 1 to 3) is turned on. As a result, test data is taken in from the interface section to the input latch circuit 4 of the semiconductor integrated circuit 1b.

After that, scan the input latch circuit 4!・By executing the operation, the input test data is
It is sent to the output latch circuit He of the semiconductor integrated circuit 1b and latched therein. Next.

The data latched in the output latch circuit of the semiconductor integrated circuit 1b is sent to the latch control section 8 of the primary semiconductor integrated circuit 1c, passed through the scan loop in the semiconductor integrated circuit 1a, and then transferred to the next semiconductor integrated circuit ld. send. In this way, data can be extracted through the scan loop of the serially connected subsequent semiconductor integrated circuit.

This test data is taken out from terminal 11b.

If the interface section is functioning normally, it is possible to detect whether or not there is a failure in the interface section by comparing it with the expected value that would be obtained based on the initially given test data, and the function of the interface section can be determined. It is possible to check whether or not it is normal.

For example, when testing the interface between semiconductor integrated circuits 1c and 1d, test data is first sent to the output latch circuit 6 of the semiconductor integrated circuit 1c via the semiconductor integrated circuits 1a and 1b. This is then sent to the input latch circuit 4 of the semiconductor integrated circuit Mid via the interface section.

Necessary inspection data can be obtained by taking out the test data obtained in step 22 from the terminal 11b via the semiconductor integrated circuits 1e and IF in the subsequent stage.

Similarly, other interface sections can be tested as well.

Note that although the above example describes a method of individually inspecting the interface section sandwiched between each semiconductor integrated circuit, other methods are also possible.

For example, test data is set in the output latch circuits 6 of the semiconductor integrated circuits 1a to 1 (second), and transferred to the input latch circuits 4 of the corresponding other semiconductor integrated circuits 1b to 1f via each interface section. The test data is sequentially extracted through scan loops of the serially connected semiconductor integrated circuits 1b to 1f.

In this case, the first test data is the semiconductor integrated circuit 10.
Formed into serial pieces in the order of ~1a, and.

Dummy data for each input latch circuit 4 interposed in between is provided. Then, this semiconductor integrated ff circuit 1
By sequentially sending the data to the scan loops 8 to 1(!), the output latch circuits 4 of the corresponding semiconductor integrated circuits 1e to 1a are latched.

At the time of the above inspection, since the scan loop is configured separately from the internal logic function section in any semiconductor integrated circuit, the test data is not affected by the operation of the logic function section. Therefore, a highly reliable test can be performed. Also, the changes that occur in the test data are
Since these are only caused by the state of the interface section, it is easy to analyze the obtained data, and it is also easy to set the pattern of test data to be initially given.

Although this embodiment has described failure detection in an interface section between semiconductor integrated circuits, it is clear that failure detection can be similarly performed in an interface section between a semiconductor integrated circuit and a printed circuit board terminal.

Although not shown in this embodiment, even if a combinational circuit exists between semiconductor integrated circuits, it is possible to detect failures in the combinational circuit by preparing expected values that take the combinational circuit into consideration. That should be obvious.

Furthermore, in the inspection method of this embodiment, the test data and control signals are sent to the latch control circuit 8 in each semiconductor integrated circuit 1, but this latch control circuit 8 is provided on the substrate 10, A scan loop may be formed by serially connecting the latch circuits in all the mounted semiconductor integrated circuits.

In addition to this example, pudding!・All of the semiconductor integrated circuits on the board were configured as a series of serially connected scan loops, but scan address No. 43 was added, and
Increase scan-in and scan-out data signals,
By connecting to the terminals of the printed circuit board, it is possible to create a scan loop configuration in which multiple sets are serially connected. According to this configuration, a scanning operation can be performed in a short time, and the time required for inspection can be shortened.

In each of the above embodiments, the test data is serially output manually, but it is also conceivable that the test data is manually output to each latch circuit in parallel. However, the parallel method requires a large number of input/output signal lines, so
Not suitable for complex circuits. On the other hand, the serial method requires fewer input/output signal lines, so it can be used even with complex circuits and is practical.

Further, in each of the above embodiments, the input latch circuit and the output latch circuit are connected in series, but they may be separated and a scan loop may be configured for each.

[Effects of the Invention] As explained above, according to the present invention, inspection can be performed without being influenced by the internal logic circuit of a semiconductor integrated circuit, and inspection results are highly reliable and easy to analyze. can be obtained.

Furthermore, according to the present invention, it is only necessary to focus on the input/output portion of the semiconductor integrated circuit, and there is no need to consider the internal logic.
This has the advantage that even large-scale semiconductor integrated circuits can be easily inspected.

Further, according to the present invention, no special jig is required during inspection, and inexpensive and highly efficient inspection is possible.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the semiconductor integrated circuit of the present invention, FIG. 2 is a block diagram showing a latch circuit which is the main structure of the embodiment of FIG. 1, and FIG. 4A and 4B are truth tables showing the operation of the latch circuit shown in FIG. 3, and FIG. 5 is a logic circuit diagram showing the detailed configuration of the latch circuit shown in FIG. 6 is a block diagram showing the configuration of the connected scan loop, FIG. 6 is a logic circuit diagram showing the detailed configuration of the latch control circuit in FIG. 1, and FIG. 7 is a block diagram showing the scan-in operation in the embodiment shown in FIG. 1. The time chart shown in FIG. 8 is a block diagram showing the configuration of an embodiment of a substrate on which a plurality of semiconductor integrated circuits shown in FIG. 1 are mounted. 1...Semiconductor integrated circuit 3...Input buffer 4...Input latch circuit 5...Logic function section 6...Output latch circuit 7...Output buffer 8...Latch control circuit 2... Terminal 10...Printed board

Claims (1)

[Claims] 1. In a semiconductor integrated circuit having a logic function section that performs a logic operation, and one or more input signal lines and output signal lines connected thereto, each of the input signal line and output signal line The device is characterized by comprising a latch function unit that is connected to correspond to the semiconductor integrated circuit, latches test data output from the semiconductor integrated circuit to an external interface unit, and latches test data input from the external interface unit. Semiconductor integrated circuit. 2. Send output test data to each of the latch function sections to cause them to latch, instruct them to output to the outside, take in test data from the outside, cause them to latch, and transfer the latched data. 2. The semiconductor integrated circuit according to claim 1, further comprising a latch control section for instructing. 3. A scan loop is formed by connecting each of the latch function sections in series so that latched data can be sequentially transferred to a subsequent stage, and connecting the first and last latch function sections to the latch control section. 2. The semiconductor integrated circuit according to 2. 4. An output latch function section for outputting test data to the outside is connected to the output signal line, and an input latch function section for taking in test data input from the outside is connected to the input signal line. Semiconductor integrated circuit. 5. The semiconductor integrated circuit according to claim 1, wherein each of the latch function sections is provided with a switch function for separating the logic function section from each input signal line and output signal line during testing. 6. Forming an interface section mainly consisting of conductor wiring, and providing wiring for transferring test data for testing the interface section, control signal wiring and terminals for controlling the testing, and Claim 2 above
A mounting board on which a plurality of semiconductor integrated circuits according to 3 or 4 are mounted. 7. The mounting board according to claim 6, further comprising a signal line serially connecting the scan loops of the semiconductor integrated circuits to be mounted. 8. The mounting board according to claim 6, wherein each of the semiconductor integrated circuits to be mounted is divided into two or more groups, and each group is provided with a signal line that serially connects the scan loops of the semiconductor integrated circuits constituting the group. . 9. A semiconductor having a latch function part in each of the input signal line and output signal line leading to the logic function part, and connecting these latch function parts serially to form a scan loop so that the latch contents can be transferred. When inspecting the interface section of a board on which multiple integrated circuits are mounted, each latch function connected to the output signal line of the semiconductor integrated circuit on the output side of the semiconductor integrated circuits that sandwich the interface section to be inspected. The test data is sequentially transferred to and latched by the other latch function units in the previous stage on the scan loop, and then the latched test data is transmitted from each latch function unit to the output signal line. On the other hand, the test data input from the interface section is read into each latch function section connected to the input signal line of the semiconductor integrated circuit on the input side, and then this is scanned as described above. The test data pattern is sequentially transferred through other latch function units in subsequent stages on the loop, and the pattern of test data sequentially output from the last stage latch function unit is compared with the test data given first to determine the function of the interface unit. A method for inspecting an interface section, characterized by evaluating. 10. A semiconductor having a latch function part in each of the input signal line and output signal line leading to the logic function part, and connecting these latch function parts serially to form a scan loop so that the latch contents can be transferred. When inspecting an interface section on a board on which a plurality of integrated circuits are mounted and the above-mentioned scan loops of each semiconductor integrated circuit are further serially connected, among the semiconductor integrated circuits that sandwich the interface section for the purpose of inspection, Each latch function unit connected to the output signal line of the semiconductor integrated circuit on the output side is sequentially connected to other latch function units located at the previous stage on the scan loop, including other semiconductor integrated circuits. Then, the latched test data is sent from each latch function section to the interface section via the output signal line, and connected to the input signal line of the semiconductor integrated circuit on the input side. The test data inputted from the interface section is read into each of the latch function sections, and then sequentially passed through other latch function sections in subsequent stages on the scan loop including other semiconductor integrated circuits. A method for inspecting an interface section, characterized in that the function of the interface section is evaluated by comparing the pattern of test data sequentially output from the latch function section at the last stage with an expected value.