JPH0256853B2 - - Google Patents
Info
- Publication number
- JPH0256853B2 JPH0256853B2 JP58184787A JP18478783A JPH0256853B2 JP H0256853 B2 JPH0256853 B2 JP H0256853B2 JP 58184787 A JP58184787 A JP 58184787A JP 18478783 A JP18478783 A JP 18478783A JP H0256853 B2 JPH0256853 B2 JP H0256853B2
- Authority
- JP
- Japan
- Prior art keywords
- input
- output
- circuit
- clock
- flop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000013256 coordination polymer Substances 0.000 claims description 10
- 238000007493 shaping process Methods 0.000 claims description 10
- 238000003708 edge detection Methods 0.000 claims description 8
- 230000000630 rising effect Effects 0.000 claims description 7
- 238000001514 detection method Methods 0.000 claims description 5
- 230000003111 delayed effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000001934 delay Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/04—Shaping pulses by increasing duration; by decreasing duration
- H03K5/06—Shaping pulses by increasing duration; by decreasing duration by the use of delay lines or other analogue delay elements
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Pulse Circuits (AREA)
Description
【発明の詳細な説明】
〔発明の分野〕
本発明はパルス幅にばらつきのあるクロツクか
ら、正負とも一定値以上のパルス幅を持つクロツ
クを作成するクロツク整形回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a clock shaping circuit that creates a clock having a pulse width of a certain value or more in both positive and negative directions from a clock whose pulse width varies.
従来、クロツク整形回路は正のパルス幅または
負のパルス幅を一定にするようなデユーテイ補正
回路、ジツタ等を吸収できるフエーズロツクトル
ープ等があつたが、正のパルス幅と負のパルス幅
の両方を一定値以上にするのは困難であつた。特
に、クロツクの系を切替えた時等に生じるパルス
幅の狭い、正または負のパルス等があると、十分
に補正しきれない場合が多かつた。
Conventionally, clock shaping circuits have included duty correction circuits that keep the positive pulse width or negative pulse width constant, phase lock loops that can absorb jitter, etc. It was difficult to maintain both values above a certain value. In particular, if there are positive or negative pulses with narrow pulse widths that occur when switching the clock system, etc., it is often not possible to sufficiently correct them.
第３図は、SRフリツプ・フロツプ遅延回路と
から構成された従来のパルス整形回路の波形を示
す。第２図の入力クロツク１と同一の波形をフリ
ツプ・フロツプのＳ入力とし、Ｑ出力を出力クロ
ツクとするとともに遅延回路を通して遅延Ｔをか
けてフリツプ・フロツプのＲ入力とした場合に
は、第３図に示すように、負のパルス幅Δ１，Δ
２がいづれもＴ以下となつてしまう。 FIG. 3 shows waveforms of a conventional pulse shaping circuit composed of an SR flip-flop delay circuit. If the same waveform as input clock 1 in FIG. 2 is used as the S input of the flip-flop, the Q output is used as the output clock, and a delay T is applied through the delay circuit to make it the R input of the flip-flop. As shown in the figure, the negative pulse width Δ1, Δ
2 will all be less than T.
本発明の目的はこのような時にも、出力のパル
ス幅を正負とも一定値以上に整形するクロツク整
形回路を提供することにある。
An object of the present invention is to provide a clock shaping circuit which shapes the output pulse width to a certain value or more in both positive and negative directions even in such a case.
本発明は、パルス幅にばらつきのある入力クロ
ツクから整形された出力クロツクを得るクロツク
整形回路において、入力クロツクの立上り検出回
路と、入力クロツクの立下り検出回路と、出力ク
ロツクの遅延回路と、該出力遅延回路の反転出力
と前記立上り検出回路の出力とを入力とする第１
の論理積回路と、前記立下り検出回路の出力と前
記出力遅延回路の出力とを入力とする第２の論理
積回路と、Ｓ入力、Ｒ入力、Ｄ入力およびCP入
力を有し前記第１の論理積回路の出力が前記Ｓ入
力に接続され前記第２の論理積回路の出力が前記
Ｒ入力に接続され前記出力遅延回路の出力が前記
CP入力に接続されかつ前記Ｄ入力には常にロー
レベルの信号が接続されたフリツプ・プロツプと
を備え、該フリツプ・フロツプは前記Ｒ入力およ
び前記CP入力のいずれか一方によりリセツトさ
れ、このフリツプ・フロツプの出力を出力クロツ
クとすることを特徴とする。
The present invention provides a clock shaping circuit that obtains a shaped output clock from an input clock with varying pulse widths, which includes an input clock rising edge detection circuit, an input clock falling edge detection circuit, an output clock delay circuit, and an input clock falling edge detection circuit. A first circuit whose inputs are the inverted output of the output delay circuit and the output of the rising edge detection circuit.
a second AND circuit which receives the output of the fall detection circuit and the output of the output delay circuit as inputs, and has an S input, an R input, a D input, and a CP input. The output of the second AND circuit is connected to the S input, the output of the second AND circuit is connected to the R input, and the output of the output delay circuit is connected to the S input.
The flip-flop is connected to the CP input and the D input is always connected to a low level signal, and the flip-flop is reset by either the R input or the CP input. It is characterized in that the output of the flop is used as the output clock.
次に図面を参照して、本発明の実施例について
説明する。
Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明におけるクロツク整形回路の一
実施例を示すブロツク図、第２図は第１図の動作
を説明するタイムチヤートである。パルス幅にば
らつきのある入力クロツク１は第１図に示すよう
に立上り検出回路１０に入力され、立上り検出回
路１０は立上り位置を検出して立上り出力２にパ
ルスを出す。（第２図Ａ，Ｂ，Ｃ，Ｄ，Ｊ，Ｋ）
又、この入力クロツク１は立下り検出回路１１に
も入力され、立下り検出回路１１は立下り位置を
検出して立下り出力３にパルスＥ，Ｆ，Ｃ，Ｈ，
Ｌ，Ｍを出す。一方出力遅延回路１５は出力クロ
ツク７をクロツク整形後に最小限必要な正負のパ
ルス幅に対応する時間Ｔだけ遅延させて遅延出力
６を出す。この遅延出力６はフリツプ・フロツプ
１４のCP入力に入力され、CP入力に“１”が入
力されたときにフリツプ・フロツプ１４のＤ入力
には常に“０”が入力される。又遅延出力６は同
時に論理積回路１３の一方に入力され、他方の入
力には前記立下り出力３が接続される。そして論
理積回路１３の出力５はフリツプ・フロツプ１４
のリセツト入力Ｒに接続される。このように接続
されることによつてフリツプ・フロツプ１４はリ
セツトされてから時間Ｔ後にCP，Ｄ入力により
リセツトされるので、その出力クロツク７の正の
パルス幅に対応する時間はＴとなる。又、出力ク
ロツク７が正になつてから時間Ｔ以内は入力クロ
ツク１の立下りが検出され立下り出力３にパルス
が出ても論理積回路１３の働きにより正のパルス
幅が時間Ｔ以下になることはない。（第２図パル
スＡ，Ｊ）一方出力遅延回路１５の遅延出力６は
反転されて論理積回路１２の一方に入力され、他
方の入力には前記立上り出力２が入力されて論理
積回路１２の出力４はフリツプ・フロツプのセツ
ト入力Ｓに入力される。この接続によつて出力ク
ロツク７が負になつてから時間Ｔ以内は、入力ク
ロツク１の立上りが検出され立上り出力２にパル
スが出ても論理積回路１２の働きにより負のパル
ス幅に対応する時間がＴ以下になることはない。
（第２図パルス幅Ｇ，Ｍ）
〔発明の効果〕
本発明は以上説明したように簡単な構成で、パ
ルス幅に変動のあるクロツクから一定値以上の正
負のパルス幅を持つクロツクをつくることができ
る。 FIG. 1 is a block diagram showing one embodiment of the clock shaping circuit according to the present invention, and FIG. 2 is a time chart explaining the operation of FIG. 1. An input clock 1 having varying pulse widths is input to a rising edge detection circuit 10 as shown in FIG. (Figure 2 A, B, C, D, J, K)
This input clock 1 is also input to a falling edge detection circuit 11, which detects the falling position and outputs pulses E, F, C, H,
Bring out L and M. On the other hand, the output delay circuit 15 delays the output clock 7 by a time T corresponding to the minimum required positive and negative pulse widths after clock shaping, and outputs a delayed output 6. This delayed output 6 is input to the CP input of the flip-flop 14, and when "1" is input to the CP input, "0" is always input to the D input of the flip-flop 14. Further, the delayed output 6 is simultaneously input to one side of the AND circuit 13, and the falling output 3 is connected to the other input. The output 5 of the AND circuit 13 is sent to the flip-flop 14.
is connected to the reset input R of the With this connection, the flip-flop 14 is reset by the CP and D inputs after a time T after being reset, so that the time corresponding to the positive pulse width of the output clock 7 is T. Furthermore, even if a falling edge of input clock 1 is detected within time T after output clock 7 becomes positive and a pulse is generated at falling output 3, the width of the positive pulse becomes less than time T due to the action of AND circuit 13. It won't happen. (Pulse A, J in Figure 2) The delayed output 6 of one output delay circuit 15 is inverted and inputted to one side of the AND circuit 12, and the rising output 2 is inputted to the other input of the AND circuit 12. Output 4 is input to the set input S of the flip-flop. Due to this connection, within time T after the output clock 7 becomes negative, even if the rising edge of the input clock 1 is detected and a pulse is output to the rising output 2, it will correspond to a negative pulse width due to the action of the AND circuit 12. Time cannot be less than T.
(Fig. 2 Pulse Widths G, M) [Effects of the Invention] As explained above, the present invention has a simple configuration, and it is possible to create a clock having positive and negative pulse widths of a certain value or more from a clock whose pulse width fluctuates. Can be done.
第１図は、本発明の一実施例を示すブロツク
図、第２図は第１図の動作を説明するタイムチヤ
ートである、第３図は従来のクロツク整形回路の
動作のタイムチヤートである。
１……入力クロツク、７……出力クロツク、１
０……立上り検出回路、１１……立下り検出回
路、１２，１３……論理積回路、１４……フリツ
プ・フロツプ、１５……出力遅延回路。
FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a time chart explaining the operation of FIG. 1, and FIG. 3 is a time chart of the operation of a conventional clock shaping circuit. 1...Input clock, 7...Output clock, 1
0... Rise detection circuit, 11... Fall detection circuit, 12, 13... AND circuit, 14... Flip-flop, 15... Output delay circuit.
Claims (1)
整形された出力クロツクを得るクロツク整形回路
において、入力クロツクの立上り検出回路と、入
力クロツクの立下り検出回路と、出力クロツクの
遅延回路と、該出力遅延回路の反転出力と前記立
上り検出回路の出力とを入力とする第１の論理積
回路と、前記立下り検出回路の出力と前記出力遅
延回路の出力とを入力とする第２の論理積回路
と、Ｓ入力、Ｒ入力、Ｄ入力およびCP入力を有
し前記第１の論理積回路の出力が前記Ｓ入力に接
続され前記第２の論理積回路の出力が前記Ｒ入力
に接続され前記出力遅延回路の出力が前記CP入
力に接続されかつ前記Ｄ入力には常にローレベル
の信号が接続されたフリツプ・フロツプとを備
え、該フリツプ・フロツプは前記Ｒ入力および前
記CP入力のいずれか一方によりリセツトされ、
このフリツプ・フロツプの出力を出力クロツクと
することを特徴とするクロツク整形回路。1. In a clock shaping circuit that obtains a shaped output clock from an input clock with varying pulse widths, an input clock rising edge detection circuit, an input clock falling edge detection circuit, an output clock delay circuit, and the output delay circuit a first AND circuit that receives as inputs the inverted output of and the output of the rise detection circuit; a second AND circuit that receives as inputs the output of the fall detection circuit and the output of the output delay circuit; The output delay circuit has an S input, an R input, a D input, and a CP input, the output of the first AND circuit is connected to the S input, the output of the second AND circuit is connected to the R input, and the output delay circuit has S input, R input, D input, and CP input. a flip-flop whose output is connected to the CP input and whose D input is always connected to a low level signal, and the flip-flop is reset by either the R input or the CP input. ,
A clock shaping circuit characterized in that the output of this flip-flop is used as an output clock.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18478783A JPS6076808A (en) | 1983-10-03 | 1983-10-03 | Clock shaping circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18478783A JPS6076808A (en) | 1983-10-03 | 1983-10-03 | Clock shaping circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6076808A JPS6076808A (en) | 1985-05-01 |
| JPH0256853B2 true JPH0256853B2 (en) | 1990-12-03 |
Family
ID=16159280
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18478783A Granted JPS6076808A (en) | 1983-10-03 | 1983-10-03 | Clock shaping circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6076808A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012244389A (en) * | 2011-05-19 | 2012-12-10 | New Japan Radio Co Ltd | Glitch processing circuit |
| GB2599681B (en) * | 2020-10-08 | 2024-09-25 | Thermo Fisher Scient Bremen Gmbh | Pulse shaping circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS516053U (en) * | 1974-07-02 | 1976-01-17 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52133147U (en) * | 1976-04-02 | 1977-10-08 |
-
1983
- 1983-10-03 JP JP18478783A patent/JPS6076808A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS516053U (en) * | 1974-07-02 | 1976-01-17 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6076808A (en) | 1985-05-01 |
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