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JPH0252260A - Digital electric energy integrating meter - Google Patents

Digital electric energy integrating meter

Info

Publication number
JPH0252260A
JPH0252260A JP20338588A JP20338588A JPH0252260A JP H0252260 A JPH0252260 A JP H0252260A JP 20338588 A JP20338588 A JP 20338588A JP 20338588 A JP20338588 A JP 20338588A JP H0252260 A JPH0252260 A JP H0252260A
Authority
JP
Japan
Prior art keywords
output
rate multiplier
voltage
frequency
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20338588A
Other languages
Japanese (ja)
Inventor
Satoshi Ichiki
敏 一木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP20338588A priority Critical patent/JPH0252260A/en
Publication of JPH0252260A publication Critical patent/JPH0252260A/en
Pending legal-status Critical Current

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  • Measurement Of Current Or Voltage (AREA)

Abstract

PURPOSE:To reduce the cost by converting a clock of a crystal oscillator and digital value of a voltage to a frequency being in proportion to the voltage and a current respectively by two rate multipliers. CONSTITUTION:Inputs 1, 2 of the voltage and the current are converted into the digital value respectively by A/D convertors 3, 4. The output of this convertor 3 and the clock of a crystal oscillator 5 are inputted into a first rate multiplier 6, and converted here to the frequency being in proportion to a voltage input. This frequency and the output of the convertor 4 are inputted into a second rate multiplier 7 and if it is converted to the frequency being in proportion to the current then the output of the multiplier 7 is allowed to be an electric power. Although this is inputted in an up-down counter 12, before that, executing the discrimination of both effective and reactive powers at a FOR (exclusive OR) circuit 8, the output of the multiplier 7 is switched to the up side and down side by AND circuits 10, 11 and integrated. By this method, inputting it into the counter 12 then an integrated value is obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、電力量の積算をディジタルで行なう積算器に
関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrator that digitally integrates electric energy.

〔従来の技術〕[Conventional technology]

電圧、電流をディジタル量に変換して積算することは、
マイクロコンピュータ(マイコン)ヲ用いて、その演算
により可能である。マイクロコンピュータの動作として
は、A/D変換器によりディジタル量に変換された電流
と電圧とを読取り、これを掛は合せて電力量を算出し、
それを加算してそれまでの電力総量を出す。
Converting voltage and current into digital quantities and integrating them is
This is possible using a microcomputer and its calculations. The microcomputer operates by reading the current and voltage converted into digital quantities by the A/D converter, multiplying them together to calculate the amount of electricity, and
Add it up to get the total amount of electricity.

このようなマイコンにより演算処理を行なわせる場合に
は、サンプリングごとに積、和の演算を行なうことにな
る。
When arithmetic processing is performed by such a microcomputer, multiplication and summation calculations are performed for each sampling.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

以上のように、マイコンでサンプリングごとに積、和の
演算を行なわなければならないことは、他の処理と並行
してこれを行なう必要が生じるとかなり忙しい処理とな
ってしまう。
As described above, the microcomputer must perform multiplication and sum calculations for each sampling, which becomes quite a busy process if it is necessary to perform this in parallel with other processing.

本発明の目的はこのような不都合を解消し、マイコンに
よることなく簡単にディジタル処理ができるディジタル
電力量積算器を提供するものである。
An object of the present invention is to eliminate such inconveniences and provide a digital power amount integrator that can easily perform digital processing without using a microcomputer.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は、前記目的を達成するため、A/D変換器によ
りディジタル変換された電圧値を受ける第1のレートマ
ルチプライアと、この第1のレートマルチプライアから
の出力及びA/D変換器によりディジタル変換された電
流値を受ける第2のレートマルチプライアと、この第2
のレートマルチプライアの出力を受けるカウンタとから
なることを要旨とするものである。
In order to achieve the above object, the present invention includes a first rate multiplier that receives a voltage value digitally converted by an A/D converter, and an output from the first rate multiplier and the A/D converter. a second rate multiplier receiving the digitally converted current value;
The gist of the system is that it consists of a counter that receives the output of the rate multiplier.

〔作用〕[Effect]

本発明によれば、水晶発振器のクロックと電圧のディジ
タル量が第1のレートマルチプライアに入力され、ここ
で電圧に比例する周波数に変換される。この周波数と電
流のディジタル量とが、第2のレートマルチプライアに
入力され、ここで電流に比例する周波数に変換される。
According to the invention, the crystal oscillator clock and voltage digital quantities are input to a first rate multiplier, where they are converted to a frequency proportional to the voltage. This frequency and the digital amount of current are input to a second rate multiplier where they are converted to a frequency proportional to the current.

この周波数は電圧と電流の積を演算したものであり、こ
れがカウンタに入力されることにより電力の積算値が得
られる。
This frequency is obtained by calculating the product of voltage and current, and by inputting this frequency to a counter, an integrated value of power can be obtained.

〔実施例〕〔Example〕

以下、図面について本発明の実施例を詳細に説明する。 Embodiments of the present invention will be described in detail below with reference to the drawings.

第1図は本発明のディジタル電力量積算器の1実施例を
示すブロック回路図で、図中3.4はA/D変換器で、
これらはそれぞれ電圧入力1、電流人力2をディジタル
量に変換する。
FIG. 1 is a block circuit diagram showing one embodiment of the digital power integrator of the present invention, in which 3.4 is an A/D converter;
These convert voltage input 1 and current input 2 into digital quantities, respectively.

水晶発振器5のクロック出力とA/D変換器3の出力と
が第1のレートマルチプライアロに導入され、さらにこ
の第1のレートマルチプライアロの出力とA/D変換器
4の出力とが第2のレートマルチプライア7に導入され
、この第2のレートマルチプライアの出力をアップダウ
ンカウンタ12に導入するようにした。
The clock output of the crystal oscillator 5 and the output of the A/D converter 3 are introduced into a first rate multiplier allo, and the output of this first rate multiplier allo and the output of the A/D converter 4 are It is introduced into the second rate multiplier 7, and the output of this second rate multiplier is introduced into the up/down counter 12.

レートマルチプライアは周知のごとく、ディジタル入力
に対して周波数変換を行なうもので、たとえば第2図に
示すようにカウンタCTとDラッチDFFにより簡単に
製作できるものである。第2図はレートマルチプライア
ロの構成を示す。レートマルチプライア7は第2図にお
いて水晶発振器5をレートマルチプライアロで置換し、
A/D変換器3をA/D変換器4で置換すればよい。
As is well known, a rate multiplier performs frequency conversion on a digital input, and can be easily manufactured using a counter CT and a D latch DFF, for example, as shown in FIG. FIG. 2 shows the configuration of the rate multiplier allo. The rate multiplier 7 replaces the crystal oscillator 5 in FIG. 2 with a rate multiplier,
The A/D converter 3 may be replaced with an A/D converter 4.

また、電力の積算に有効電力、無効電力を対応させるた
め、A/D変換器3,4の出力をFOR(エクスクル−
シブオア)回路8に導入し、このEOR回路8の出力を
、NOT回路9を介してAND回路10に、またそのま
まAND回路11にそれぞれ導入し、これらAND回路
10.11に第2のレートマルチプライア7の出力を導
入し、これらAND回路10.11の出力をカウンタ1
2に導入するようにした。
In addition, in order to make active power and reactive power correspond to power integration, the outputs of A/D converters 3 and 4 are
The output of this EOR circuit 8 is introduced into an AND circuit 10 via a NOT circuit 9, and directly into an AND circuit 11. 7 is introduced, and the outputs of these AND circuits 10 and 11 are input to counter 1.
I decided to introduce it in 2.

このようにして、電圧入力1をA/D変換器3によりデ
ィジタル量に変換し、電流人力2をA/D変換器4によ
りディジタル量に変換する。
In this way, the voltage input 1 is converted into a digital quantity by the A/D converter 3, and the current input 2 is converted into a digital quantity by the A/D converter 4.

このA/D変換器3のディジタル出力と水晶発振器5の
クロックとが第1のレートマルチプライアロに入力され
ることにより、この第1のレートマルチプライアロで電
圧入力に比例した周波数に変換される。
By inputting the digital output of the A/D converter 3 and the clock of the crystal oscillator 5 to the first rate multiplier, the first rate multiplier allo converts it into a frequency proportional to the voltage input. Ru.

この周波数とA/D変換器4からの電流のディジタル量
を第2のレートマルチプライアに入力し、電流に比例す
る周波数に変換すれば、この第2のレートマルチプライ
ア7の出力は電力となる。
If this frequency and the digital amount of current from the A/D converter 4 are input to the second rate multiplier and converted to a frequency proportional to the current, the output of the second rate multiplier 7 will be electric power. .

これをアップダウンカウンタ12に入力するが、この場
合、有効電力、無効電力の判別をEOR回路8により行
ない、レートマルチプライア7の出力をAND回路10
.11によりアップ側、ダウン側に切替えて積分を行な
う。このようにして、有効電力と無効電力が電圧と電流
の向きにより判別可能であるカウンタ12の出力が、電
力量となる。
This is input to the up/down counter 12. In this case, the EOR circuit 8 discriminates between active power and reactive power, and the output of the rate multiplier 7 is input to the AND circuit 10.
.. 11, the integration is performed by switching to the up side and down side. In this way, the output of the counter 12, in which active power and reactive power can be determined based on the direction of voltage and current, becomes the amount of electric power.

〔発明の効果〕〔Effect of the invention〕

以上述べたように、本発明のディジタル電力量積算器は
、マイコン以外の簡単なディジタル回路で作成できるも
ので、コストダウンを実現できるものである。
As described above, the digital power amount integrator of the present invention can be created using a simple digital circuit other than a microcomputer, and can realize cost reduction.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明のディジタル電力量積算器の1実施例を
示すブロック回路図、第2図はレートマルチプライアを
示す回路図である。 1・・・電圧入力      2・・・電流入力3.4
・・・A/D変換器  5・・・水晶発振器6.7・・
・レートマルチプライア 8・・・EOR回路     9・・・NOT回路10
.11・・・AND回路12−・・カウンタr C’J
 (Y)U)すω■Uへ
FIG. 1 is a block circuit diagram showing one embodiment of the digital power integrator of the present invention, and FIG. 2 is a circuit diagram showing a rate multiplier. 1... Voltage input 2... Current input 3.4
...A/D converter 5...Crystal oscillator 6.7...
・Rate multiplier 8...EOR circuit 9...NOT circuit 10
.. 11...AND circuit 12-...Counter r C'J
(Y)U) To ω■U

Claims (1)

【特許請求の範囲】[Claims] 水晶発振器のクロックとA/D変換器によりディジタル
変換された電圧値を受ける第1のレートマルチプライア
と、この第1のレートマルチプライアからの出力及びA
/D変換器によりディジタル変換された電流値を受ける
第2のレートマルチプライアと、この第2のレートマル
チプライアの出力を受けるカウンタとからなることを特
徴とするディジタル電力量積算器。
A first rate multiplier receives the clock of the crystal oscillator and the voltage value digitally converted by the A/D converter, and outputs the output from the first rate multiplier and the A/D converter.
1. A digital power amount integrator comprising: a second rate multiplier that receives a current value digitally converted by a /D converter; and a counter that receives an output of the second rate multiplier.
JP20338588A 1988-08-16 1988-08-16 Digital electric energy integrating meter Pending JPH0252260A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20338588A JPH0252260A (en) 1988-08-16 1988-08-16 Digital electric energy integrating meter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20338588A JPH0252260A (en) 1988-08-16 1988-08-16 Digital electric energy integrating meter

Publications (1)

Publication Number Publication Date
JPH0252260A true JPH0252260A (en) 1990-02-21

Family

ID=16473163

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20338588A Pending JPH0252260A (en) 1988-08-16 1988-08-16 Digital electric energy integrating meter

Country Status (1)

Country Link
JP (1) JPH0252260A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0945275A2 (en) 1998-03-24 1999-09-29 Matsushita Electric Industrial Co., Ltd. Image forming apparatus and image forming method
JP2009066766A (en) * 2007-09-10 2009-04-02 Ricoh Co Ltd Image forming apparatus
US7821527B2 (en) 2007-08-09 2010-10-26 Ricoh Company, Ltd. Image forming apparatus
US8167410B2 (en) 2008-09-11 2012-05-01 Ricoh Company, Ltd. Image forming apparatus
US8259142B2 (en) 2009-02-25 2012-09-04 Ricoh Company, Limited Image forming apparatus with developer passage amount control electrodes
US8376494B2 (en) 2009-08-20 2013-02-19 Ricoh Company, Limited Image forming device and image forming apparatus

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0945275A2 (en) 1998-03-24 1999-09-29 Matsushita Electric Industrial Co., Ltd. Image forming apparatus and image forming method
US7821527B2 (en) 2007-08-09 2010-10-26 Ricoh Company, Ltd. Image forming apparatus
JP2009066766A (en) * 2007-09-10 2009-04-02 Ricoh Co Ltd Image forming apparatus
US8167410B2 (en) 2008-09-11 2012-05-01 Ricoh Company, Ltd. Image forming apparatus
US8259142B2 (en) 2009-02-25 2012-09-04 Ricoh Company, Limited Image forming apparatus with developer passage amount control electrodes
US8376494B2 (en) 2009-08-20 2013-02-19 Ricoh Company, Limited Image forming device and image forming apparatus

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