JPH0250508A - Digital signal processor - Google Patents

Abstract

PURPOSE:To prevent the deterioration of the output signal due to a limit cycle at the time of silence by inputting the output of a first comparator and a second comparator, and when the input of an unlimited impulse response filter is '0' and the output is closed in a fluid sector area, resetting a delaying device in an infinite impulse response filter. CONSTITUTION:A signal xn impressed to an input terminal 11 is inputted to a first comparator 13 to compare whether or not a primary input signal is '0'. An output yn of an infinite impulse response(IIR) filter 12 is inputted to a second comparator 14 and here, it is compared whether or not it is in the blind sector area. The compared result of first and second comparators 13 and 14 is inputted to a control circuit 15, and the control circuit 15 detects that the input signal xn is '0' and the output yn of the IIR filter 12 is in the blind sector area, and resets the value held by the delaying device in the internal part of the IIR filter 12 to '0'. Thus, a limit cycle is stopped and the deterioration of the output signal due to the limit cycle can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital signal processing device used for digital processing of audio signals and the like.

2. Description of the Related Art In recent years, digital audio devices such as compact disc players and digital audio tape recorders have become popular. Along with this, equipment that uses digital signal processing to adjust sound quality, add reverberation, etc. has also been developed.

A digital filter that performs digital signal processing has a finite impulse response (Finite IμulseR6).
spons6 (hereinafter referred to as FIR) filter and an infinite impulse response (FIR) filter.
There is a Re5ponse (hereinafter referred to as IIR) filter. FIR filters have the advantage of being stable and capable of realizing a linear phase, but the circuit scale is large, and in some cases real-time processing may be impossible because the operating speed of the elements is insufficient. On the other hand, an IIR filter has a small circuit scale and a short processing time, but since it is a feedback circuit, attention must be paid to stability.

As a technique using a conventional IIR filter.

There are Japanese Patent Publication No. 63-18367, etc. FIG. 2 shows a conventional first-order IIR filter. This IIR filter is composed of a subtracter 1, a delay device 2, and a multiplier 3, and the subtracter 1 subtracts the output of the multiplier 3 from the input signal. The output of the subtracter 1 is delayed by a delay device 2 and multiplied by a coefficient α in a multiplier 3. 4 is an output terminal. The first-order IIR filter in FIG. 2 is realized with a fixed point, and the input
, output yT1 is an integer. At this time, yfl
, x, and ll have the relationship expressed by the following equation 1.

yn=Xn (α·yn-4)' (1) In the first equation, ()' indicates rounding to the nearest integer.

When the input x0 is sufficiently large and the quantization error due to rounding can be ignored, the first equation can be considered equal to the second equation.

yn=X-αyn-0... (2) From the second equation, the second
The transfer function H1 (Z), amplitude frequency characteristic A, (f), and phase frequency characteristic φ, (f) of the first-order IIR filter in the figure are as follows:
They are respectively expressed by the third to fifth equations.

Hx(Z)=t/(1+aZ-1)...(3)(A,
Cf)) ”=1/(1+α”+2αcos(2πf/
f2)l...(4)φ, (f)=tan-1(-sin
(2πf#s) / (1+α・cos(2π#fg)
B...(5) where fg is the sampling frequency. This type of IIR filter is created by changing the value of α.

Filters with various characteristics can be realized. For example -1
When α<0, a low-pass characteristic is obtained.

Furthermore, in combination with an FIR filter, low frequency emphasis, high frequency emphasis, phase shifting, etc. can be realized.

Next, the second-order IIR filter will be explained.

FIG. 3 shows the configuration of a conventional second-order IIR filter.
The next IIR filter consists of a subtracter 5, first and second delay devices 6 and 7, and first and second multipliers 8 and 9. The outputs of multipliers 8 and 9 are subtracted. The output of the subtracter 5 is input to the first multiplier 8 via the first delay device 6, and the output of the subtracter 5 is input to the second multiplier 9.
The output of the delay device 6 is further delayed by a second delay device 7 and inputted. Here, the coefficients of the first and second multipliers 8 and 9 are β1. β. The signal is output from the output terminal 10.

Assume that the second-order IIR filter in FIG. 3 is realized using a fixed point number, and the input X and the output yn are integers.

At this time, the outputs y and n are expressed by the sixth equation.

Vn=1rs (β1・y2,)′−(β2・′I
n-t)' (6) When the input Xn is sufficiently large and the quantization error due to rounding can be ignored, the sixth equation can be considered to be equal to the seventh equation.

)'n = It will be done.

H, (Z) = 1 / (1 + β, z-1 + βzz-”)
-(s) In the eighth equation, if β1'<4β2, it has a complex conjugate pole, and if O<β2×1, it is stable.

β1 that satisfies these two conditions. By β2, for example,
A bandpass filter can be realized.

Generally, when realizing more complex characteristics, an FIR filter and a first-order or second-order IIR filter are often combined.When using a third-order or higher-order IIR filter, it is difficult to ensure the stability of the filter.

Problems to be Solved by the Invention In such a conventional configuration, limit cycle oscillation may occur. After inputting a non-O signal to the IIR filter, if the input is set to O, it will be non-O in the case of a finite word length.
becomes a constant value, or undamped parasitic vibrations occur. This is called a limit cycle. A limit cycle occurs when the output yn enters the dead band after the input Xyl becomes O, and the input xt, is no longer 0 again, and y
, disappears when it leaves the dead band. 1 expressed by the first equation
The dead band D1 of the next IIR filter is D□=[-□, Ki] for the largest integer □ that satisfies Equation 9.

K,≦0.57(1-lα1)...(9) The dead band D2 of the second-order IIR filter expressed by the seventh equation is the first
Dz= (Kz−
kg).

K2≦0.5/(1-β2)...(10) For example,
When inputting the output of a compact disc player to a filter, limit cycle oscillation may occur when disc playback is stopped at -. Furthermore, I
When IR filters are connected in series, the limit cycle of the first-stage IIR filter becomes the input to the subsequent-stage filter.

Therefore, the influence of the limit cycle may be amplified, which is undesirable because noise is generated during unmanned signalling.

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital signal processing device that can prevent deterioration of output signals due to limit cycles when there is no signal.

Means for Solving the Problems The digital signal processing device of the present invention comprises: an infinite impulse response filter to which a signal to be filtered is applied to an input; a first comparator that compares the input of the infinite impulse response filter with 0; , a second comparator that compares the output of the infinite impulse response filter with a reference value to determine whether the output is trapped in a dead band; and the outputs of the first comparator and the second comparator are input; The present invention is characterized by comprising a control circuit that resets a delay device in the infinite impulse response filter when the input of the infinite impulse response filter is 0 and the output is confined within its dead band.

According to this configuration, when a limit cycle occurs, the first and second comparators and the control circuit force the output to 0 to stop the limit cycle from occurring.

Example An embodiment of the present invention will be described below with reference to FIG.

It should be noted that here, the case of a first-order IIR filter will be described as an example.

FIG. 1 shows a digital signal processing device of the present invention. The signal Xn applied to the input terminal 11 has a transfer function Hz (Z)
= 1 / (1+ a ・Z-1) of the first order II
The signal is input to a first comparator 13 which compares the input signal with the R filter 12 to see if it is O. The outputs y, 11 of the IIR filter 12 are input to the second comparator 14, where the dead band D□=(-(0,5/(1-1α1)).

(0,5/(1-1α1))]. The comparison results of the first and second comparators 13 and 14 are input to the control circuit 15, and the control circuit 15 receives the input signals x, .
is O, and the output ytl of the IIR filter 12 is in the dead band D
1 is detected, and the value held by the delay device (delay device 2 in FIG. 2) inside the IIR filter 12 is reset to O. 16 is an output terminal.

Because of this configuration, when the input is not 0, I
The IR filter 12 performs processing using its transfer function H (Z), and outputs the result from the output terminal 16. When the input becomes 0, the first comparator 13 determines that the input is O. The received signal is transmitted to the control circuit 15. II
Generally, when the input of the R filter 12 becomes 0, the output also becomes 0.
, and when the output falls within the dead band D1, a signal indicating that the output falls within the dead band is transmitted from the second comparator 14 to the control circuit 15. And the control circuit 15 is II
The value held in the delay device inside the R filter 12 is reset to 0 to stop the limit cycle. As a result,
The output of the IIR filter 12 also becomes 0. When the input signal is no longer 0, information is transmitted to the control circuit 15 through the first comparator 13, the reset is canceled, and normal filtering is performed.

In the above embodiment, the IIR filter 12 is first-order, but it may be second-order. In this case, the dead band D2 is the largest integer that satisfies the first θ equation, and D2 = (-, K,).
In this case, there are two delay devices inside the IR filter, so when the IIR filter output is within D2 twice in a row, it is determined that the output is trapped in the dead band. I have to.

In addition, when the subtracter of the IIR filter is shared with the accumulator of the n-th FIR filter, the output of the first comparator is configured to be inflated by n cycles and transmitted to the control circuit. .

Effects of the Invention As described above, according to the present invention, by focusing on the fact that the limit cycle occurs when there is no human power and that the output at that time is confined within the dead band, both The control circuit automatically resets the infinite impulse filter and stops the limit cycle by determining that a limit cycle is occurring when it detects that the condition is met, so the output signal deteriorates due to the limit cycle. can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a digital signal processing device according to an embodiment of the present invention, and FIGS. 2 and 3 are block diagrams of a conventional IIR filter. DESCRIPTION OF SYMBOLS 11... Input terminal, 12... Infinite impulse response filter, 13... First comparator, 14... Second comparator, 15... Control circuit, 16... Output terminal. Agent Yoshihiro Morimoto 1st

Claims (1)

[Claims] 1. An infinite impulse response filter to which a signal to be filtered is applied to its input, a first comparator that compares the input of the infinite impulse response filter with 0, and a comparison between the output of the infinite impulse response filter and a reference value. a second comparator that determines whether or not the device is trapped in the dead band;
a control circuit that resets a delay device in the infinite impulse response filter when the input of the infinite impulse response filter is 0 and the output is confined within its dead band.