JPH0247862A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a large capacitance with a small area easily by a method wherein a capacitance element is composed of a conductor film formed on a substrate, a dielectric film covering the conductor film and a conductor film formed on the dielectric film, while said conductor film is composed of a multilayer structure consisting of at least three conductor layers. CONSTITUTION:An aluminum wiring 12 is provided as a third electrode and electrically connected to a first electrode 3 through a through-hole 11. Therefore, a capacitor composed of the first and third electrodes 3 and 12 and a second electrode 6 which are facing electrodes and oxide films 4 and 7 and nitride films 5 and 8 which are dielectric films. As a capacitor area is a summation of the areas of the first electrode 3 and the third electrode 12, the capacitor area twice the area occupied by a capacitance element can be obtained. With this constitution, a large capacitance can be obtained with a small area.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device using a capacitive element, and particularly to a semiconductor integrated circuit device that requires a small area and a large capacity.

[Conventional technology]

Conventionally, when constructing a capacitive element in a semiconductor integrated circuit device, for example, a capacitive element is used whose manufacturing process cross-section is shown in FIGS. 7(a) to (f), and whose planar fabrication is shown in FIG. There is.

That is, as shown in FIG. 7(a), after forming the first electrode 3 of polycrystalline silicon on the oxide film 2 of the silicon substrate 1,
The surface is coated with an oxide film 4 and a nitride film 5 as shown in FIG. 3(b). Furthermore, as shown in FIG. 7(C), a second electrode 6 is formed of polycrystalline silicon on the nitride film 5, and a second electrode 6 is formed on the nitride film 5 as shown in FIG.
It is covered with a relatively thick oxide film 9 as shown in d).

Next, as shown in FIG. 7(e), an oxide film 9 and a nitride film 5 are formed on the second electrode 6 and the first electrode 3. Contact holes 11 are formed in each of the oxide films 4, and aluminum wiring 1 is inserted through the contact holes 11 as shown in FIG. 7(f) and FIG.
2 is formed.

In this configuration, a capacitor is formed in which the first electrode 3 and the second electrode 6 are opposed electrodes, and the oxide film 4 and nitride film 5 are dielectric films.

[Problem to be solved by the invention]

The conventional capacitive element described above requires the first
There is a problem in that it is necessary to increase the area of the electrode 3 and the second electrode 6, and it is not suitable for increasing the density of semiconductor integrated circuit devices. Further, the oxide film 4 and nitride film 5 as dielectric films may be made thinner, but pinholes are likely to occur in these films due to thinner films, and there is also a limit to their withstand voltage, making it difficult to increase the capacitance. be.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device equipped with a capacitive element that has a small area and can easily obtain a large capacity.

[Means to solve the problem]

In the semiconductor integrated circuit device of the present invention, a capacitive element is constituted by a conductive film formed on a substrate, a dielectric film covering this conductive film, and a conductive film formed on this dielectric film, and this conductive film is
It is composed of multiple layers that are larger than the eyebrows.

[Effect]

In the above-described configuration, the capacitive element composed of the conductor film and the dielectric film can be configured in multiple layers of two or more in the same plane area, and the capacitance in the same plane area can be increased.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to (h) are vertical cross-sectional views showing the first embodiment of the present invention in the order of manufacturing steps, and FIG. 2 shows FIG. 1(h).
1 shows a plan view of .

First, as shown in FIG. 1(a), after forming a first electrode 3 of polycrystalline silicon on an oxide film 2 of a silicon substrate l, a first electrode 3 is formed using polycrystalline silicon.
The surface is coated with an oxide film 4 and a nitride film 5 as shown in FIG. Furthermore, as shown in FIG. 1(C), a second electric wire 6 is formed of polycrystalline silicon on the nitride film 5, and this surface is covered with the first wire.
It is covered with an oxide film 7 as shown in FIG. 1(d), and then
) is coated with a nitride film 8.

Next, as shown in FIG. 1(f), a relatively thick oxide film 9 is formed on the entire surface, and the oxide film 9 on the second electrode 7 is removed over a relatively wide area to open a window 10. Second
Oxide film 9 on the electrode 7 and the first electrode 3. Nitride film 5. Contact holes 11 are formed in each of the oxide films 4.

Then, as shown in FIG. 1(h) and FIG.
2 is formed.

According to this configuration, the aluminum wiring 12 is configured as a third electrode and is electrically connected to the first electrode 3 through the through hole 11. For this reason, the first electrode 3, the third electrode 12, and the second electrode 6 are used as opposing electrodes, respectively, and the oxide films 4, 7
．． A capacitor is constructed using the nitride film 5.8 as a dielectric film. And here, the capacitance area is the first voltage gi3 and the third voltage gi3.
Since this is the sum of the areas of the electrodes 12, it is possible to obtain a capacitive area that is approximately twice the area occupied by the capacitive element.

As a result, a large capacity can be obtained with a small area.

FIG. 3 is a longitudinal sectional view of a second embodiment of the present invention, and the same parts as in FIG. 1 are given the same reference numerals. In this embodiment, the third electrode 13 is made of polycrystalline silicon, and after the third electrode 13 is formed on the second electrode 6, the oxide film 9 is formed,
Also, a through hole 11 is opened to connect the aluminum wiring 12.
The configuration is such that the two are connected.

FIG. 4 is a longitudinal sectional view of a third embodiment of the present invention, in which an oxide film 7. A thick oxide film 1194 is directly formed without forming a nitride film 8, and this oxide film 9 is etched to a required thickness to form an aluminum wiring 12 there as a third electrode. Therefore, the remaining thickness of the oxide film 9 is configured as a dielectric film.

FIG. 5 is a longitudinal sectional view of a fourth embodiment of the present invention, and FIG. 6 is a plan view thereof. Here, a 31f'M12 is formed of aluminum on the oxide film 9 on the second electrode 6, and the third electrode 12 is further covered with an oxide film 14, and a fourth electrode 15 is formed using a part of the aluminum wiring. It consists of The first electrode 3 and the third electrode 12 are electrically connected by the through hole 11, and the second electrode 6 and the fourth electrode 15 are electrically connected.

This configuration has a four-layer capacitor structure, making it possible to obtain extremely large capacitance in a small area.

〔Effect of the invention〕

As explained above, in the present invention, since the capacitive element composed of the conductive film and the dielectric film formed on the substrate is configured in multiple layers in the same plane area, the capacitance in the same plane area can be increased, and the capacitance element can be increased in a small area. It becomes possible to construct a large-capacity element.

[Brief explanation of the drawing]

FIGS. 1(a) to (h) are longitudinal sectional views showing the first embodiment of the present invention in the order of manufacturing steps, FIG. 2 is a plan view of FIG. 1(h),
3 is a longitudinal sectional view of a second embodiment of the invention, FIG. 4 is a longitudinal sectional view of a third embodiment of the invention, FIG. 5 is a longitudinal sectional view of a fourth embodiment of the invention, and FIG. 6 is a longitudinal sectional view of a fourth embodiment of the invention. The figure is a plan view of Figure 5, and Figure 7 (a).
7(f) are vertical sectional views showing the conventional structure in the order of manufacturing steps, and FIG. 8 is a plan view of FIG. 7(f). 1... Silicon substrate, 2... Oxide film, 3... First
Electrode, 4... Oxide film, 5... Nitride film, 6... Second
Electrode, 7... Oxide film, 8... Nitride film, 9... Thick oxide film, 10... Window, 11... Through hole, 12
...Third electrode, 13...Third electrode, 14...Oxide film, 15...Fourth electrode. Fig. 1 Silicon difference, a Fig. 4 Fig. 6 Fig. 7

Claims (1)

[Claims] 1. In a semiconductor integrated circuit device in which a capacitive element is constituted by a conductor film formed on a substrate, a dielectric film covering this conductor film, and a conductor film formed on this dielectric film, the conductor film is formed in three layers. A semiconductor integrated circuit device characterized by having a multilayer structure as described above.