JPH0246762A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable high speed operation and reduce gate input capacitance and occupied area, by a method wherein, when two or more insulated gate field effect transistors are connected in series, the gate length of the insulated gate field effect transistor is made short, as compared with the gate length of the one which is not connected in series. CONSTITUTION:When at least one of an input A and an input B is 'high', either one of PMOSFET's P1A, P2A turns off. Since the MOSFET's are connected in series, the voltage applied between the source and drain of the PMOSFET becomes smaller than Vcc, an MISFET, whose gate length is short as compared with a circuit not connected in series, can be used in a circuit connected in series. As a result, the current of an MISFET increases, so that it is unnecessary to increase the gate width, and the gate capacitance is reduced. Thereby high speed operation is enabled.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit constructed using insulated gate field effect transistors.

[Conventional technology]

Figures 3 and 4 are block diagrams of a NOR circuit and a NAND circuit using complementary metal oxide field effect transistors (hereinafter referred to as CMOSFETs).
．． P3. P4 is PMOSFET, N 1 , N 2
.

N3. N4 is NMOSFII! It is T.

In addition, FIGS. 5 and 6 are configuration diagrams of other semiconductor integrated circuits,
P5 is PMOSFET, N5 is NMO5FI! T
, N6 is an NMO3FET, and R1 is a resistance.

Next, the operation will be explained.

In FIG. 3, PMOSFETs P 1 , P
2 are connected in series, so when A=B="10W", both PMO5FtiT P1 and P2 are O.
n, so X=“high”. NMO3FET
Since N 1 and N 2 are connected in parallel, A
Or when B is "high", NMO5FET N1 or N2 is turned on, so X = "Ilow", and NOR
take action. Here, PMOSFET P1.

Since P2 is connected in series, when outputting X = "high", the output current is PMOSFET P1
, P2 is limited by the series resistance. Therefore, in circuits that require high-speed operation, PMOSF[! The gate widths of T P 1 and P 2 are PMOSFs connected in parallel in Fig. 4.
It was necessary to make the gate width larger than that of ET P3 and P4.

At this time, the enhancement type MISFET (insulated gate field effect transistor) used in the CMOS circuit is used, so as shown in FIG. .

It is required to turn off at =0■.

However, by reducing the gate length of the MISFET, a punch-through phenomenon occurs, and as shown in Figure 8, the I
When vogl is increased, Il, 1 even at Ves=OV
increases. In Figure 8, curve 1 is the NMOSFET
, curve 2 is PMoSFETMISFET.

When the gate length is reduced, the curve in FIG. 8 changes from curve 1b to 1a for NMOSFET, and from curve 2b to 2a for PMOSFET. As is clear from these facts, by reducing the gate length, the MOSF
The source-drain voltage that can be turned off by the gate voltage of ET becomes smaller. Therefore, in the circuit configuration shown in FIG. 6, a MOSFET in which a bunch-through phenomenon occurs and a large current flows even when VGS=0■ cannot be used. Similar thing 2. The same can be said of the CMOS inverter circuit shown in FIG.

Therefore, the gate length is reduced, and a MISFET with a small gate input capacitance and a large current driving ability is used. That was difficult.

Also, in the CMOS NAND circuit shown in Fig. 4, NMOSFETs N 3 and N are connected in series.
The gate width of NMOSFETN1.4 is the same as that of NMOSFETN1.4 connected in parallel in FIG. It was necessary to make the gate width larger than the gate width of N2.

[Problem to be solved by the invention]

Conventional semiconductor integrated circuit devices are configured as described above, so it is necessary to increase the gate width of elements connected in series in high-speed operating circuits in order to increase the load driving force. This has led to problems such as an increase in gate input capacitance and an increase in the area occupied by the circuit.

The present invention has been made to solve the above-mentioned problems, and aims to provide a semiconductor integrated circuit device that can operate at high speed, has a small gate input capacitance, and occupies a small area.

[Means to solve the problem]

In the semiconductor integrated circuit according to the present invention, when two or more insulated gate field effect transistors are connected in series, the gate length of the insulated gate field effect transistor is shorter than that of a transistor not connected in series. It is characterized by this.

[Effect]

In the present invention, the gate length of the insulated gate field transistors (MISFETs) connected in series is shorter than the gate length of the MISFETs connected in parallel, and a larger current flows, reducing the gate capacitance.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, PIA and P2A are two 5FETs SNl and N2 are NMOSFETs with shortened gate lengths.

A and B are input terminals, and X is an output terminal. This circuit is
This is a NOR circuit that performs a logical operation expressed by the logical formula =A+H.

Next, the operation will be explained.

Now, at least one of inputs A or B is hi
gh”, the corresponding PMOSFET P I
A.

Either P2A is turned off. At this time, PMOSF
Since the ETs are connected in series, the voltage applied between the source and drain of the PMOSFET is smaller than Vcc, so in a series-connected circuit,
MISFE with short gate length compared to other circuits
T can be used. This allows MISFET
Since the current increases, there is no need to increase the gate width, and the gate capacitance is reduced, allowing high-speed operation.

FIG. 2 shows another embodiment of the invention. In this case, the MISFETs connected in series are NMOSFETs N3A and N4A with short gate lengths.

Here, the NMOSFETs N3. The same result is obtained by reducing the gate length of N4.

Furthermore, in the above embodiments, two-man powered CMOS NOR and NAND circuits have been described, but the present invention can also be applied to multi-input CMOS logic circuits.

〔Effect of the invention〕

As explained above, according to the present invention, when two or more insulated gate field effect transistors are connected in series, the gate length of the insulated gate field effect transistor is compared with that of one not connected in series. I made it shorter, so
A semiconductor integrated circuit device that operates at high speed and occupies a small area can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] In a semiconductor integrated circuit configured using insulated gate field effect transistors, when two or more of the insulated gate field effect transistors are connected in series, the gate lengths of the insulated gate field effect transistors are A semiconductor integrated circuit characterized by being shorter than one without.