JPH024010A - Output circuit - Google Patents

Abstract

PURPOSE:To reduce an oscillating transition voltage at the time of switching by connecting the outputs of second and third inverters(In) common in gate signals to the gates of the P-type transistor(Tr) and N-type Tr of a first In, respectively, and connecting capacities between the gates and drains, respectively. CONSTITUTION:When a signal IN is at an L level, nodes (a) and (b) are at an H level, the L level is outputted to an output terminal OUT, and capacitors C1 and C2 for correcting a phase are charged so as to make the nodes (a) and (b) into +. Next, when the signal IN is changed to the H, a TrP4 of an In3 is turned off, the TrN4 is turned on, thereby, the potential of the node (b) is changed to the L through TrN4 and N2, and the gate voltage of a TrN0 of an In1 is made into VSS+VTN (VSS is a lowest potential and VTN is threshold voltage of N-type Tr). Since the gate of a TrP0 of the In1 is made into ADD-VTP (ADD is highest potential and VTP is threshold voltage of P-type Tr) and the gate of the TrN0 is made into VSS+VTN, microcurrents are made to flow, respectively, and the output terminal OUT is gradually changed from the L to H.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output circuit, and particularly to an output circuit using CMOS transistors.

[Conventional technology]

Conventionally, this type of output circuit is a CMO circuit as shown in FIG.
It is composed of an S inverter, and the driving capacity is set according to the size of the load. This conventional output circuit has a P-type transistor P5. P6 and N-type transistor N5. N6
are connected in series between the highest potential VDD and the lowest potential SS, and further connected to an input terminal IN and an output terminal OUT, respectively. Note that a load CL is connected to the output terminal OUT side.

[Problem to be solved by the invention]

In the conventional output circuit described above, the drive capability was set by widening the channel widths of the transistors P6 and N6 in order to match the maximum values of the loads C and L to be driven.

The signals to the gates of transistors P6 and N6 are set by transistors P5 and N5, and the rise and fall times of the input signals are not affected by the size of load CL.Therefore, the output rise and fall times of transistors P6 and N6 are The time varies depending on the load CL, and the smaller the load CL, the shorter the charging and discharging time, and the output changes in a shorter time.

However, the influence of parasitic inductance caused by bonding wires, wiring cables, etc. increases, and oscillating transient voltages occur in the output, which causes malfunctions in other semiconductor circuits that receive the output signals. there were.

An object of the present invention is to provide an output circuit capable of reducing oscillatory transient voltages during switching.

[Means to solve the problem]

The output circuit of the present invention includes a first CMOS inverter and a second CMOS inverter having a common gate signal. P-type transistor 1 having a third CMOS inverter and having its gate and drain connected
and the drain side of the N-type transistor 1 whose gate is connected to the bias circuit, respectively.
a second inverter connected to the source side of the N-type transistor and the N-type transistor, the drain side of the P-type transistor 2 whose gate is connected to the bias circuit, and the drain of the N-type transistor 2 whose gate and drain are connected,
A third inverter is connected to the sources of the P-type transistor and the N-type transistor, respectively, and the outputs of the second inverter and the third inverter are connected to the gates of the P-type transistor and the N-type transistor of the first inverter, respectively. , a capacitor C1 is connected between the gate and drain of the P-type transistor of the first inverter, and a capacitor C2 is connected between the gate and drain of the N-type transistor.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an output circuit which is an embodiment of the present invention.
In the figure, IN is an input terminal, and BII is an input terminal.

BI2 is a bias input terminal, OUT is an output terminal, PO, P
L, P2. P3. P4 is P type MOS) transistor No.
Nl, N2. N3. N4 is an N-type MOS transistor, C
1 and C2 are phase correction capacitors, CL is a capacitive load, a and b are nodes, and VDD is the highest potential and VSS is the lowest potential, respectively.

The PO and No of the first inverter are the load CL as before.
The driving capacity is set according to the size of the motor.

Bias BII connected to the gates of N1 of the second inverter and P2 of the third inverter.

Nl by arbitrarily setting the potential of BI2.

The current flowing through P2 is controlled to determine the output fall time of the second inverter and the output rise time of the third inverter.

Pl of the second inverter and N2 of the third inverter are:
By connecting the gate and drain, the equibending has the same characteristics as a diode, and the output amplitude of the second inverter changes from VDD-VTP to VSS.The output amplitude of the third inverter changes from VDD to VSS+VTN.

VTP...P-type transistor threshold voltage VTN.
...Threshold voltage of N-type transistor Next, the operation of this embodiment will be explained. When the IN signal is at a low level, nodes a and b are at a high level, and a low level is output to the OUT output terminal. Also, nodes a and b are at high level, OU
Since the T output terminal is at a low level, the phase correction capacitors CI and C2 are charged with charges so that the nodes a and b become ten.

Next, when the IN signal changes to high level, P4 of the third inverter is turned off and N4 is turned on.
of the inverter N4. changes to low level through N2, and sets the gate voltage of the first inverter NO to VSS+VTH.
Set to the value of Also, the charge on C2 is the charge on N4 of the third inverter.
．． It is discharged through N2, and further charged to 02 through C1 so that OUT becomes ten. Also, the gate of the P-type transistor of the first inverter is VDD-VTP.
Since the gates of the N-type transistors are at the potential of VSS-+-VTN, a small current flows through the P-type transistors and the N-type transistors, so OUT gradually changes from a low level to a high level.

Next, when the IN signal approaches a high level, P3 of the second inverter turns off and N3 turns on, so the potential at node a becomes the second
OUT changes little by little to a low level by N1 of the inverter, and the current flowing through the P-type transistor increases, further changing to a high level.

Next, when the IN signal becomes completely high level, the nodes a and b become low level and the OUT output terminal outputs high level. The same operation also occurs when the IN signal changes from high level to low level. Therefore, the P-type transistor and N-type transistor of the first inverter are turned on and off by the second.
Since this is done at the timing of the third inverter or CI, C2, there is no sudden change in the output of the first inverter even when the load CL is small.

〔Effect of the invention〕

As explained above, by applying the output circuit of the present invention, it is possible to reduce the oscillatory transient voltage during switching. Also, the potential of the bias input or the second C
P-type transistor 1 and third CM of MOS inverter
By changing the channel width of the N-type transistor 2 of the OS inverter, there is an effect that the rise and fall times of the output can be easily set.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a conventional output path, and FIG. 3 is a signal waveform illustrating the operation of the embodiment of the present invention and the conventional output circuit. It is a diagram. PO, PL, P2. P3. P4. P5. P6...P type MO3) transistor, NO, Nl, N2°N3. N4.
N5. N6...N type MO3) - transistor, C1, C
2...Capacitor, CL...Load, a. b, c... Node name, VDD... Highest potential, VSS.
...Lowest potential, IN...Input terminal, QUT...Output terminal, BII, BI2...Bias input terminal.

Claims (1)

[Claims] A first CMOS inverter and a second CMOS inverter having a common gate signal.
, a third CMOS inverter, the drain side of the P-type transistor 1 whose gate and drain are connected, and the drain side of the N-type transistor 1 whose gate is connected to the bias circuit, respectively, a P-type transistor, a second inverter connected to the source side of the N-type transistor;
P-type transistor 2 whose gate is connected to the bias circuit
the drain side of the gate, and the gate and drain connected to the
A third inverter connects the drain of the type transistor 2 to the sources of the P-type transistor and N-type transistor, respectively, and connects the outputs of the second and third inverters to the P-type transistor of the first inverter and the N-type transistor The output circuit has a structure in which a capacitor C1 is connected between the gate and drain of the P-type transistor of the first inverter, and a capacitor C2 is connected between the gate and drain of the N-type transistor of the first inverter.