JPH0234894A - Display controller - Google Patents

Abstract

PURPOSE:To display various display areas on one display by setting individually the maximum display capacity of the display and display areas which are used actually. CONSTITUTION:A register 102 for setting the maximum display capacity of the display and a register 103 for setting the display areas where a video signal is used actually for displaying are presented independently. Therefore, even when a display area used actually for displaying is smaller than the display capacity, the display is possible by setting them independently. Consequently, even if there are many display areas, corresponding values are set as the display areas to display many kinds of display areas for one kind of display capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a display controller that generates display control signals for flat displays (LCDs, plasma displays, etc.) used in computers and the like.

[Conventional technology]

In conventional display controllers, there is only one type of display area setting means. For example, horizontal direction 6
When using a flat display with 40 dots x 400 dots in the vertical direction, set the display area (display size) on the controller to 640 x 400, and
When using a flat display of 1640 dots x 200 dots vertically, the display area setting on the controller is changed to 640 x 200. Therefore, if one system has multiple display areas, for example two types of display areas, 640X400 and 640X200, prepare two types of flat displays and select the display that suits each display mode. I was using it.

[Problem to be solved by the invention]

In conventional display controllers, there is only one type of display area setting means, so if there is only one type of display area in two systems, there is no problem, but within one system, there are many types of display areas depending on the software. If there is a display area of That is, it is not possible to display various types of software on one display. For example, a personal computer manufactured by IBM
Taking IBM-PC as an example, in this system,
Display area is 640x350 dots or 640x20
There are multiple numbers, such as 0 dots. The selection of this display area is done by software, so the display is
If fixed to 0x350 dot, 640x200
Software that only supports DOT displays will no longer be usable.

An object of the present invention is to solve the problem of not being able to display a plurality of display areas on a single display using a mode setting method for a display controller, and to enable a wide range of uses even if the display area changes.

[Means to solve the problem]

The display controller of the present invention has means for independently setting the maximum display capacity (first display size) that the display can display and the display area (second display size) that is actually used for display.

[For production]

Since the present invention has the above configuration, even if the display area (second display size) actually used for display is smaller than the display capacity (first display size), display is possible by setting each area independently. . Therefore, even if there are several display areas, if you set the corresponding value as the display area,
Various types of display areas can be displayed for one type of display capacity.

〔Example〕

LCD controller (hereinafter referred to as video-L) that converts video signals for CRT into signals for liquid crystal display (hereinafter referred to as LCD)
FIG. 1 shows an example in which the present invention is applied to a CD interface. First, the operation of this controller will be briefly explained. Video data VD for CRT usually has a display data period (shaded area) and a retrace period (outside the shaded area) as shown in FIG. Further, the retrace period can be classified into four types: vertical back porch, vertical front porch, horizontal back porch, and horizontal front porch. Video data is scanned point-by-point from the upper left and input serially from the VD shown in Figure 1.
The data is taken into a serial/parallel conversion circuit (hereinafter referred to as an S/P conversion circuit) 115 by a dot clock CK synchronized with VD. This serial data is converted into parallel data every 8 bits and written to external buffer memory 120 via data bus 130. At that time, the write address is determined by the write address counter 105, which counts the write clock 131 obtained by dividing the frequency of CK by 1/8 by the frequency divider 104, in order from the upper left as shown in FIG.
Each dot is counted up and output. The write address AW switches every 8 dots and is transferred to the write address bus 122 via the write address conversion circuit 106.
is output to. The read/write control circuit 107 outputs an address switching signal 125 and write control signals 126 and 127 in synchronization with the rise and fall of the write clock 131.
Output. The address switching circuit 129 switches the address of one of the write address bus 122 and the read address bus 123 to the address bus 1 using the address switching signal 125.
Output to 24. Therefore, during writing, when the write address is switched every 8 dots of the dot clock, the write address is output to the bus 124 in the first half of the write clock 131, and the 8-bit data is output from the S/P conversion circuit 115 in synchronization with the control signal 126. Parallel data is input, and the control signal 127 causes the external buffer memory 120 to
becomes a write state, and parallel data is written to the address of the memory 120 corresponding to the address data of the bus 124.

As mentioned above, the video data has invalid data (retrace period).
is included, so that part is ignored and only the display data can be taken in by the S/P conversion circuit. Control with. The horizontal synchronizing signal H8C is input to the horizontal back porch determination circuit/horizontal dot counter as a counter start pulse, and the dot clock CK is input as a counter clock.

The vertical synchronization signal vSC is inputted to the vertical back porch determination circuit/vertical gain counter as the start pulse of the counter, and the horizontal synchronization signal H8C is inputted as the clock of the counter.

Next, reading from the external buffer memory will be explained. The clock generation circuit 111 outputs a basic clock for reading. The read address counter 108 generates a read address by counting the read clock 132 obtained by dividing the read basic clock by 1/2 using the frequency divider 110 in an order suitable for the LCD. The data read from the external buffer memory 120 is transferred to the data bus 13.
0 to the LCD data conversion circuit 118, and L
The data is converted into a format suitable for a CD and output via a blanking control 119 (described later). In addition, the control signals (data shift clock, data latch pulse, etc.) necessary for the LCD 121 are generated by the clock generation circuit 111.
The LCD control signal generation circuit 117 that counts clocks from the LCD control signal generating circuit 117 generates the clock signal and supplies it to the LCD. At the time of reading, a control signal 128 is output from the read/write control circuit 107, and the control signal 127 causes the external buffer memory 1 to
27 is in a read state. The control signal 128 is output in synchronization with the write clock 131 when the read address counter 108 counts the read clock 132 and the read address changes. This signal 128
The latch 109 latches the read address and outputs the address data to the bus 123. During a read cycle immediately after the read address changes, the address switching circuit 129 outputs read address data, and data is read from the memory address corresponding to this address. The above is an outline of the video-LCD interface.

Next, details of the portion to which the present invention is applied will be explained.

First, the mode setting register 101 will be described.

This register is a register group that performs various settings such as the driving method and display area of the LCD, and includes a register 102 that sets the maximum display capacity (first display size) that can be displayed on the LCD, and a register 102 that sets the video signal. Register 103 for setting the display area (second display size) actually used for display
exist independently. For example, a 640 x 480 dot matrix LCD has a display area of 640 x 350 dots (for example, an IBM personal computer IB
If the M-PC EGA mode is to be used, the register 102 is set to 640x480 dots, and the register 103 is set to 640x350 dots. The display in this case is as shown in FIG. 4, and the buffer memory is reserved for the display capacity (640×480 dots). The valid video data (hatched area) here is 350
Since there is only one line, in order to display the LCD as shown in FIG. 4, it is necessary to provide an offset to the address when writing to the buffer memory.

The write address conversion circuit 106 performs this exchange.
It is. Further, the maximum number to be counted by the write address counter 105 is set by D103 indicating the display area. In the case of the display shown in FIG. 4, the address to be accessed may be added to the main screen blank data as an offset. As an example of this circuit, FIG. 5 shows a circuit that uses an adder to add the offset.

Here, the offset address register 501 is a register in which the offset value of the address is written. Since several types of offset values are required depending on the combination of display capacity and display area, a plurality of registers are prepared. One value is selected from among these registers via selector 502. At this time, selector 502 makes a selection based on output signals D102 and D103 from the mode setting register shown in FIG. 1 selected in this way
The 6-bit offset value is output to 503 and input to a 16-bit adder 504 together with the output AW from write address counter 05. As a result, an address obtained by adding the offset address to the normal write address AW is obtained from the output AAW. That is, since the write address counter 105 only counts 640 dots x 350 lines with the count number set by D103 as described above, the address conversion circuit 1
06 adds a blank area bone of 640 dots x 65 lines to address AW. Therefore, the video data is not stored in the aforementioned 5200 bytes of buffer memory 120, but is stored starting from the next address. If the contents of the mode setting registers 102 and 103 change, the maximum count of the write address counter 105 and the offset amount of the address conversion circuit 106 will also change accordingly. Settings are now possible. When writing is performed using this method, writing is not performed in the portion of the buffer memory corresponding to the blank data shown in FIG. 4, and valid video data is written from the address next to the address corresponding to the offset. On the other hand, since reading is performed for the entire display capacity, that is, for all 640×480 dots, reading is also performed from the buffer memory to which the above-mentioned writing is not performed, and data is transferred to the LCD. Therefore, read it out as is and LC
If it is transferred to D, random data may be displayed in the upper and lower blank data areas. To avoid this, either provide a memory clear sequence and clear the contents of the buffer memory every time (when the power is turned on, etc.), or control the blanking data part so that it is not transferred to the LCD. It is necessary to do this.

The part that controls the latter is blanking control 1.
It is 19. This is register 102 and register 103.
It has a function of disabling data output to the LCD corresponding to the blanking data section based on the information.

In this case, the data output is disabled (fixed at low level) during data transfer from the 1st line to the 65th line and during data transfer from the 416th line to the 480th line. An example of a blanking control circuit is shown in FIG. The operation will be briefly explained below. The input signal LINEC is a bit line counter output signal of the LCD.

This LCD line counter is included in the LCD control signal generation circuit 117 of FIG. 1, and is a 9-bit counter that counts up the number of LCD lines (480 lines in this case). This counter output LINEC is input to the decoder 601 in the blanking control 119. This decoder includes a mode register 102 and a
The decoder output is switched in response to the contents D102 and D103 of 03. Here, based on D102 and D103, LINEC decodes the contents of the 65th line beginning where the display area begins and outputs a signal 607, and also indicates that the display area ends and the blanking data begins at the 415th line. is decoded and a signal 608 is output. The timing chart is shown in FIG. These signals are further input to the R/S flip-flop 602 and displayed on the LCD.
Generates a data enable signal LCDEN. LCD
The LCD data is enabled only when EN is at high level, and the L output from the LCD data conversion circuit 118
The CD data LCDD is output to the LCD via AND gates 603-606. At other times, AND gate 6
The outputs of 03 to 606 are fixed at low level and are not displayed on the LCD. What should be noted here is that the read address counter 108 and the LCD1i control signal generation circuit 11
Each line counter in 7 indicates the display capacity of the LCD.
The maximum count number is set by 102. Therefore, the read address counter 108 counts addresses so as to repeatedly read data corresponding to the display capacity of the LCD from the buffer memory 120. Further, the line counter repeatedly counts for 480 lines as shown in FIG. Based on the output of this line counter, an enable signal LCDEN is output for 350 lines from line 65 to line 414 out of the 480 lines counted.

Therefore, the count number of these counters is D102.1
03 changes accordingly, making it possible to set various display areas for displays with various display capacities.

To summarize the above, the display controller shown in FIG. 1 defines a storage capacity corresponding to the display capacity of the display in the buffer memory 120, and when writing, the video data is stored in the storage capacity of 640 dots x 65 lines. 640 dots x 3 from the next address without memorizing it
It stores data for 50 lines. Therefore, if data is read and displayed from addresses corresponding to the display capacity, the display will display the data in the set display area. However, if erroneous data is stored in an address in the buffer memory where the video data is not stored, erroneous display may occur if the video data is simply read out.

However, in the present invention, the display position of the display is detected and data is output to the display only for the period of the display area.
Since it is set at a fixed level so that it is not displayed during other periods, there is no need to worry about it being erroneously displayed outside the display area.

In this way, display outside the display area can be completely turned off. Above, 640 x 480 dot LCD
The operation when displaying 640×350 dots has been explained. If you wish to change the display to 640 x 200 dots, simply change the contents of the register 103 for setting the display area to 640 x 200 dots.

Then, the offset amount 503 to the address of the write address conversion circuit 106 mentioned above and the output of the decoder 601 of the blanking control 119 are automatically switched, so that a display as shown in FIG. 8 can be obtained.

As described above, according to the present invention, since the display capacity setting register 102 and the display area setting register 103 are provided independently, one LCD is provided.

For example, various displays on a 640x480 dot LCD,
Not only 640 x 480 dots but also 640 x 350 dots and 640 x 200 dots can be displayed by simply changing the value of register 103 without changing the hardware. In this example,
Although we used a register, which is a readable and writable storage means, as a means for setting the display capacity and display area, this is not limited to registers, and other means may be used.For example, it is easier to provide input terminals for each, and to Settings can also be changed by changing the human input signal. In this description, the case where blanking areas exist above and below as shown in FIG. 4 has been explained, but the same applies to the case where blanking areas exist above, below, left and right as shown in FIG.

In this case, only the offset address selector 501 in the write address conversion circuit and the decoder 601 in the blanking control are slightly changed. Further, although the explanation has been given using an LCD as an example, the present invention is similarly applicable to controllers for other flat displays (for example, plasma displays).

〔Effect of the invention〕

By using the present invention, various display modes (display areas) can be displayed on one display. Therefore, even if the display mode changes depending on the software, there is no need to replace the hardware (display) each time, and it is possible to support various software. This is particularly effective when applied to laptop computers and the like that use flat displays, as a single type of flat display can support a variety of software.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention. FIG. 2 is a format diagram of the video data signal VD. Third
The figure shows the correspondence between external buffer memory addresses and display positions. FIG. 4 is a diagram showing an example of LCD display. FIG. 5 is a diagram showing a specific example of a write address conversion circuit. FIG. 6 is a diagram showing a specific example of blanking control. FIG. 7 is an operation timing chart of blanking control. FIG. 8 is a diagram showing an example of LCD display when holding blank pigs on the top, bottom, left and right sides. 101 @ 102ψ 103・106・119・501・502・503・504・601・602・・Mode setting register・Display capacity setting register・Display area setting register・Write address conversion circuit・Blanking control・Offset address register contest selector - Offset address (16 bits) - 16-bit adder, decoder, R/S flip-flop and above Applicant: Seiko Epson Corporation Representative Patent attorney: Kizobe Suzuki (and 1 other person) Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] A display controller that generates a display control signal for a display, characterized in that the display controller has means for independently setting the maximum display capacity that the display can display and the display area that is actually used for display.