JPH0233953A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0233953A JPH0233953A JP63184022A JP18402288A JPH0233953A JP H0233953 A JPH0233953 A JP H0233953A JP 63184022 A JP63184022 A JP 63184022A JP 18402288 A JP18402288 A JP 18402288A JP H0233953 A JPH0233953 A JP H0233953A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- case
- gel
- cavity
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 229920005989 resin Polymers 0.000 claims abstract description 44
- 239000011347 resin Substances 0.000 claims abstract description 44
- 230000006378 damage Effects 0.000 abstract description 7
- 238000010000 carbonizing Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000017525 heat dissipation Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000012634 fragment Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体チップの設けられた放熱板をその上
方からケースで覆い、そのケース内にゲル状樹脂と硬化
性樹脂を充填して半導体チップを封止した半導体装置に
関するものである。[Detailed Description of the Invention] [Industrial Application Field] This invention covers a heat dissipation plate provided with a semiconductor chip with a case from above, and fills the case with a gel-like resin and a hardening resin. The present invention relates to a semiconductor device in which a chip is sealed.
第３図は、従来のこの種の半導体装置の一例である電力
用半導体モジュールの内部構造を示す縦断面図である。FIG. 3 is a longitudinal sectional view showing the internal structure of a power semiconductor module, which is an example of a conventional semiconductor device of this type.
図において、金属材料からなる放熱板１上には絶縁基板
２が設けられて、１３す、この絶縁基板２上には半導体
チップ３が接着されている。さらに、放熱板１にはその
上方を覆うケース４が接着固定され、このケース４内に
半導体デツプ３の仝而を覆うようにゲル状樹脂５が充填
され、さらにその上に補強用としてエポキシ系樹脂など
の硬化性樹脂６が充填されている。また、ケース４の一
部からは、必要に応じてケース４内の半導体チップ３に
電気的に接続された電極７が外部に向けて突出させてあ
り、この電極７を外部配線と接続するためのナツト８．
ビス９などが設けられている。In the figure, an insulating substrate 2 is provided on a heat sink 1 made of a metal material, and a semiconductor chip 3 is bonded onto the insulating substrate 2 (13). Furthermore, a case 4 covering the upper part of the heat dissipation plate 1 is adhesively fixed, and a gel-like resin 5 is filled in this case 4 so as to cover the semiconductor depth 3, and an epoxy resin is added on top of it for reinforcement. A curable resin 6 such as resin is filled. Further, an electrode 7 electrically connected to the semiconductor chip 3 inside the case 4 is protruded from a part of the case 4 toward the outside as necessary, and is used to connect the electrode 7 to external wiring. Natsu 8.
Screws 9 etc. are provided.
（発明が解決しようとする課題）
しかしながら、上記構成の半導体装置では、短絡事故な
どによって半導体チップ３が破壊されると半導体チップ
３の溶解が起り、それに伴って発生する炭化ガスや熱に
よってゲル状樹脂５が膨張し、この膨張力によってケー
ス４が不特定個所で破壊されてしまう。そして、ケース
４の破壊によってゲル状樹脂５が放出されると、炭化物
が直接絶縁基板２上に付着して絶縁破壊を起したり、ま
たケース４の破壊によって周囲に飛散するケース４の破
片で周辺機器が損傷を起し、さらには半導体チップ３の
破壊時のアークによって火災が発生するなどの問題点が
あった。(Problem to be Solved by the Invention) However, in the semiconductor device having the above structure, if the semiconductor chip 3 is destroyed due to a short circuit accident, the semiconductor chip 3 will melt, and the resulting carbonized gas and heat will cause the semiconductor chip 3 to become gelatinous. The resin 5 expands, and the expansion force causes the case 4 to be destroyed at unspecified locations. When the gel-like resin 5 is released due to the breakage of the case 4, carbide may adhere directly to the insulating substrate 2 and cause dielectric breakdown, or fragments of the case 4 may be scattered around due to the breakage of the case 4. There were problems such as damage to peripheral equipment and furthermore, fire caused by arcing when the semiconductor chip 3 was destroyed.
この発明は、このような問題点を解消するためになされ
たもので、ケースの破壊を防止することのできる半導体
装置を得ることを目的とする。The present invention has been made to solve these problems, and an object of the present invention is to provide a semiconductor device whose case can be prevented from being destroyed.
この発明に係る半導体装置は、半導体チップの設けられ
た放熱板をその上方からケースで覆い、このケース内に
ト記半導体チップを全面に覆うゲル状樹脂を充填すると
ともに、このゲル状樹脂を全面に覆う硬化性樹脂をさら
に充填した半導体装置であって、上記ゲル状樹脂よりも
上方に位置するケースの内壁面より上記ゲル状樹脂に向
けて空洞の筒体を延設し、その筒体の先端の開口を上記
ゲル状樹脂内に臨ませたものである。In the semiconductor device according to the present invention, a heat dissipation plate on which a semiconductor chip is provided is covered with a case from above, a gel-like resin is filled in the case to cover the entire surface of the semiconductor chip, and the gel-like resin is filled on the entire surface. The semiconductor device is further filled with a curable resin to cover the cylindrical body, and a hollow cylindrical body is provided extending from the inner wall surface of the case located above the gel-like resin toward the gel-like resin, and the cylindrical body is covered with a curable resin. The opening at the tip faces into the gel-like resin.
この発明においては、ゲル状樹脂の膨張力は、このゲル
状樹脂内に先端の開口が臨まされている筒体の空洞によ
って吸収される。In this invention, the expansion force of the gel-like resin is absorbed by the cavity of the cylinder whose tip opening faces into the gel-like resin.
第１図はこの発明による半導体装置の一実施例である電
力用半導体モジュールの内部構造を示す縦断面図である
。第１図において、１〜９は第３図に示す従来装置と同
一のものである。この実施例に係る電力用半導体モジュ
ールでは、ケース４の内壁面のうちゲル状樹脂５よりも
上方の位置（ここでは天井面）に、空洞の筒体１０が硬
化性樹脂６を貫通して垂設されている。筒体１０の下端
には開口１０ａが形成され、その間口１０ａはゲル状樹
脂５内に臨まされている。その他の構成は第３図に示す
従来装置と同様である。FIG. 1 is a longitudinal sectional view showing the internal structure of a power semiconductor module which is an embodiment of a semiconductor device according to the present invention. In FIG. 1, numerals 1 to 9 are the same as the conventional device shown in FIG. In the power semiconductor module according to this embodiment, a hollow cylindrical body 10 extends through the hardening resin 6 and hangs down at a position above the gel-like resin 5 on the inner wall surface of the case 4 (here, the ceiling surface). It is set up. An opening 10a is formed at the lower end of the cylindrical body 10, and the opening 10a faces into the gel-like resin 5. The rest of the configuration is the same as the conventional device shown in FIG.
この電力用半導体モジュールにおいて、例えば短絡事故
などによって半導体チップ３が破壊され、半導体チップ
３の溶解が起ると、それに伴って発生する炭化ガスや熱
のためにゲル状樹脂５が膨張する。しかし、このときの
ゲル状樹脂５の膨張力は筒体１０の空洞によって吸収さ
れるため、ケース４の破壊は防止されることになる。In this power semiconductor module, when the semiconductor chip 3 is destroyed and melted due to, for example, a short-circuit accident, the gel-like resin 5 expands due to the carbonized gas and heat generated. However, since the expansion force of the gel-like resin 5 at this time is absorbed by the cavity of the cylindrical body 10, the case 4 is prevented from being destroyed.
第２図はこの発明による半導体装置の他の実施例である
電力用半導体モジュールの内部構造を示す縦断面図であ
る。１〜１０．１０ａは第１図に示す実施例と同一のも
のである。この電力用半導体モジュールでは、ケース４
のうち、筒体１０の空洞に接する部分４ａの肉厚がケー
ス４の他の部分の肉厚よりも薄く形成されている。その
他の構成は第１図の実施例と同様である。FIG. 2 is a longitudinal sectional view showing the internal structure of a power semiconductor module which is another embodiment of the semiconductor device according to the present invention. 1 to 10.10a are the same as the embodiment shown in FIG. In this power semiconductor module, Case 4
Among them, the wall thickness of the portion 4a in contact with the cavity of the cylindrical body 10 is formed to be thinner than the wall thickness of the other portions of the case 4. The rest of the structure is the same as the embodiment shown in FIG.
この電力用半導体モジュールにおいて、例えば急激なゲ
ル状樹脂５の膨張が起ってり゛−ス４が万一破壊される
場合には、ケース４のうち肉厚の最も薄い部分４ａつま
り筒体１０の空洞に接する部分で破壊が生じることにな
る。したがって、ケース４の破壊に伴ってゲル状樹脂５
が外部に放出されるとき、筒体１０の空洞がその放出経
路となる。In this power semiconductor module, if the case 4 is destroyed due to rapid expansion of the gel-like resin 5, for example, the thinnest part 4a of the case 4, that is, the cylindrical body 10 Destruction will occur at the part in contact with the cavity. Therefore, with the destruction of the case 4, the gel-like resin 5
When released to the outside, the cavity of the cylindrical body 10 becomes the release path.
つまり、ケース４はその上面が局部的に破壊され、ゲル
状樹脂５は上方に向けて放出されることになるので、ケ
ース４の破片が周囲に飛散しにくくなり、飛散する破片
による周辺機器の損傷が回避されるとともに、ゲル状樹
脂５も飛散しにくくなることから、絶縁基板２に炭化物
が付着するなどして起る絶縁破壊も回避される。ケース
４の破壊を未然に防止できるときの作用は先の実施例の
場合と全く同じである。In other words, the upper surface of the case 4 is locally destroyed and the gel-like resin 5 is ejected upward, making it difficult for the pieces of the case 4 to scatter to the surroundings, and the scattered pieces can damage peripheral equipment. Since damage is avoided and the gel-like resin 5 is also less likely to scatter, dielectric breakdown caused by adhesion of carbide to the insulating substrate 2 is also avoided. The effect when the case 4 can be prevented from breaking is exactly the same as in the previous embodiment.
以上のように、この発明によれば、先端の開口がゲル状
樹脂内に臨むように、空洞の筒体を、ゲル状樹脂よりも
上方のケース内壁面より延設し、ゲル状樹脂の膨張力を
筒体の空洞によって吸収するように構成したので、ケー
スの破壊を確実に防止することができるという効果があ
る。As described above, according to the present invention, the hollow cylindrical body is extended from the inner wall surface of the case above the gel-like resin so that the opening at the tip faces into the gel-like resin, and the gel-like resin expands. Since the structure is configured so that the force is absorbed by the cavity of the cylindrical body, there is an effect that destruction of the case can be reliably prevented.
第１図はこの発明による半導体装置の一実施例の内部構
造を示す縦断面図、第２図はこの発明による半導体装置
の他の実施例の内部構造を示す縦断面図、第３図は従来
の半導体装置の内部構造を示す縦断面図である。
図において、１は放熱板、３は半導体チップ、４はケー
ス、５はゲル状樹脂、６は硬化性樹脂、１０は筒体、１
０ａは開口である。
なお、各図中同一符号は同一または相当部分を小ず。
代理人 大 岩 増 雄FIG. 1 is a longitudinal sectional view showing the internal structure of one embodiment of the semiconductor device according to the present invention, FIG. 2 is a longitudinal sectional view showing the internal structure of another embodiment of the semiconductor device according to the invention, and FIG. 3 is a conventional FIG. 2 is a vertical cross-sectional view showing the internal structure of the semiconductor device of FIG. In the figure, 1 is a heat sink, 3 is a semiconductor chip, 4 is a case, 5 is a gel-like resin, 6 is a hardening resin, 10 is a cylinder, 1
0a is an opening. In addition, the same reference numerals in each figure represent the same or corresponding parts. Agent Masuo Oiwa
Claims (1)
ケースで覆い、このケース内に前記半導体チップを全面
に覆うゲル状樹脂を充填するとともに、このゲル状樹脂
を全面に覆う硬化性樹脂をさらに充填した半導体装置に
おいて、 前記ゲル状樹脂よりも上方に位置する前記ケースの内壁
面より前記ゲル状樹脂に向けて空洞の筒体を延設し、そ
の筒体の先端の開口を前記ゲル状樹脂内に臨ませたこと
を特徴とする半導体装置。(1) Cover the heat sink on which the semiconductor chip is installed with a case from above, fill the case with a gel-like resin that covers the entire surface of the semiconductor chip, and fill the case with a curable resin that covers the entire surface of the gel-like resin. Furthermore, in the filled semiconductor device, a hollow cylindrical body is provided extending from the inner wall surface of the case located above the gel-like resin toward the gel-like resin, and an opening at the tip of the cylinder is opened to the gel-like resin. A semiconductor device characterized by being exposed inside a resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63184022A JPH0233953A (en) | 1988-07-22 | 1988-07-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63184022A JPH0233953A (en) | 1988-07-22 | 1988-07-22 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0233953A true JPH0233953A (en) | 1990-02-05 |
Family
ID=16145974
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63184022A Pending JPH0233953A (en) | 1988-07-22 | 1988-07-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0233953A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0455147U (en) * | 1990-09-14 | 1992-05-12 | ||
| US5744860A (en) * | 1996-02-06 | 1998-04-28 | Asea Brown Boveri Ag | Power semiconductor module |
| EP0845809A3 (en) * | 1996-12-02 | 2000-05-03 | Abb Research Ltd. | Semiconductor power module |
| JP2019175923A (en) * | 2018-03-27 | 2019-10-10 | 三菱電機株式会社 | Semiconductor package |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6148947A (en) * | 1984-08-16 | 1986-03-10 | Mitsubishi Electric Corp | Semiconductor device |
-
1988
- 1988-07-22 JP JP63184022A patent/JPH0233953A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6148947A (en) * | 1984-08-16 | 1986-03-10 | Mitsubishi Electric Corp | Semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0455147U (en) * | 1990-09-14 | 1992-05-12 | ||
| US5744860A (en) * | 1996-02-06 | 1998-04-28 | Asea Brown Boveri Ag | Power semiconductor module |
| EP0845809A3 (en) * | 1996-12-02 | 2000-05-03 | Abb Research Ltd. | Semiconductor power module |
| JP2019175923A (en) * | 2018-03-27 | 2019-10-10 | 三菱電機株式会社 | Semiconductor package |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6392890B1 (en) | Method and device for heat dissipation in an electronics system | |
| US5977621A (en) | Power semiconductor module | |
| KR100342455B1 (en) | Semiconductor device and method of manufacturing the same | |
| US9559027B2 (en) | Semiconductor device and semiconductor module | |
| US3509430A (en) | Mount for electronic component | |
| KR930014905A (en) | Hermetic Packaged High Density Interconnect (HDI) Electronic Systems | |
| JPS617615A (en) | Dry capacitor circuit breaker | |
| CN100405584C (en) | Semiconductor device | |
| US5446436A (en) | High voltage high power arc suppressing fuse | |
| EP0384482B1 (en) | Composite semiconductor device | |
| JPH0233953A (en) | Semiconductor device | |
| US4839625A (en) | Fuse | |
| JPS6221249A (en) | Semiconductor device | |
| JP2934421B2 (en) | Resin encapsulated semiconductor device with heat sink | |
| JPH1012806A (en) | Semiconductor device | |
| JP2000058686A (en) | Semiconductor device and carrier for semiconductor device | |
| US20240105645A1 (en) | Semiconductor device | |
| JP2004095992A (en) | Semiconductor device | |
| JPS6129155A (en) | Semiconductor device | |
| JPH10331442A (en) | Destruction method | |
| JPH0356055Y2 (en) | ||
| JPH08130808A (en) | Pressure relieving device for sealed container | |
| JPH0870066A (en) | Semiconductor device | |
| JPH0436119Y2 (en) | ||
| JPH0534111Y2 (en) |