JPH02291123A - Silicon carbide semiconductor device - Google Patents

Abstract

PURPOSE:To form a high-resistance silicon carbide single-crystal layer which functions as an electrically insulating layer and a channel layer even in a high- temperature region by a method wherein ions of a prescribed amount are implanted into a silicon carbide single-crystal layer which has been grown on a semiconductor substrate, an ion-implanted layer is formed in its surface region and the ion-implanted layer is heat-annealed. CONSTITUTION:An undoped SiC single-crystal layer 2 is grown on an Si single- crystal substrate 1. Then, boron ions (<11>B<+>) are implanted two times into a surface region of the undoped SiC single-crystal layer 2; a B-ion-implanted layer 3 is formed. A heat-annealing operation is executed at a prescribed temperature; the B-ion-implanted layer 3 is activated; a high-resistance SiC single- crystal layer (i.e., an electrically insulating layer and a channel layer) 4 is formed. A resistivity of the high-resistance SiC single-crystal layer 4 is reduced hardly; the high-resistance SiC single-crystal layer 4 can be endowed with a performance which is sufficient for the electrically insulating layer and the channel layer.

Description

[Detailed Description of the Invention] (Field of Application in Industry) The present invention relates to a silicon carbide semiconductor device in which a high-resistance silicon carbide cumulative single crystal layer serves as an electrical insulating layer and a channel layer, and in particular to an insulated gate field effect transistor. .

(Prior art) Starting with silicon (S1), gallium arsenide (GaAs)
Semiconductor devices (e.g. diodes, transistors,
Integrated circuits, large-scale integrated circuits, light emitting diodes, semiconductor lasers, and charge-coupled devices) have been widely used in various fields of electronics.

Silicon carbide (SiC) has a wide forbidden band width (2.2-3.
3eV), which has thermal, chemical,
It also has the excellent characteristics of being extremely mechanically stable and resistant to radiation damage. Semiconductor devices using conventional semiconductor materials such as silicon are particularly susceptible to high temperatures. It is difficult to use under harsh conditions such as high-output drive and radiation exposure. Therefore, semiconductor devices using silicon carbide are expected to be applied in a wide range of fields as semiconductor devices that can be used even under such harsh conditions.

However, no crystal growth technology has been established that can stably supply large-area, high-quality silicon carbide single crystals on an industrial scale with productivity in mind. Therefore, although silicon carbide is a semiconductor material that has many advantages and possibilities as described above, its practical application has been hindered.

Traditionally, on a laboratory scale, silicon carbide single crystals have been grown by sublimation recrystallization method (Rayleigh method), or silicon carbide single crystals obtained by this method have been grown using vapor phase growth method (C
By epitaxially growing a silicon carbide single crystal layer using the VD method (VD method) or the liquid phase epitaxial growth method (LPB method), a silicon carbide single crystal of a size that can be used for prototyping semiconductor devices is obtained.

However, in these methods, the area of the single crystal removed is small, and it is difficult to control its size and shape with high precision. Furthermore, it is not easy to control the crystal polymorphism and impurity concentration of silicon carbide.

In order to solve these problems, the present inventors would like to propose a method of vapor phase growth of a high-quality silicon carbide single crystal with a large area on an inexpensive and easily available silicon single crystal substrate-L. JP-A-59-203799).

In this method, if an impurity is added during vapor phase growth of silicon carbide, it is possible to control the impurity concentration and conductivity type in the obtained silicon carbide single crystal. A method for manufacturing various semiconductor devices (for example, diodes and transistors) using a silicon carbide single crystal layer formed on a silicon substrate using this method has been developed (Japanese Patent Application No. 58-246511, No. 58-249981 and No. 252157 of 1982).

Conventionally, in these silicon carbide semiconductor devices (for example, field effect transistors), a mouth-shaped (or p-type) silicon carbide crystal layer that serves as a channel layer is formed on a p-type (or n-type) silicon carbide single crystal layer. The chamfer layer was electrically insulated from the semiconductor substrate by a pn junction between these two layers. however. In a semiconductor device with such a structure,
When a reverse high-ass voltage is applied to the pn junction, a leakage current is generated between the semiconductor substrate and the channel layer due to crystal defects present in the silicon carbide single crystal layer. Therefore, it is difficult to completely electrically insulate the channel layer from the semiconductor substrate, and good transistor characteristics cannot be obtained.

On the other hand, in order to electrically insulate the semiconductor substrate and the channel layer, instead of the ρn junction between the silicon carbide single crystal layers as described above, a ρn junction is formed between the semiconductor substrate and the channel layer by ion implantation. The company previously filed a patent application for using a high-resistance silicon carbide single crystal layer as an electrical insulating layer. A silicon carbide semiconductor device having such a structure has the advantage that device characteristics do not deteriorate up to a high temperature range of around 500°C.

(Problem to be Solved by the Invention) However, when forming an insulated gate field effect transistor (MOSFET) using a silicon carbide crystal, a channel layer is formed on an electrically insulating layer, and then the It is necessary to provide a drain region and a source region in the channel layer. Furthermore, it is necessary to further form a gate insulating film on the channel layer. Therefore, in order to simplify the manufacturing process, it is conceivable to configure the electrical insulating layer and the channel layer described in "2" with a single high-resistance silicon carbide single crystal layer. The problem is how to form a crystalline layer of silicon carbide 13 that has sufficient resistance to function as a layer. Such a formation method includes, for example, adding impurities when growing a silicon carbide single crystal layer using the above-mentioned vapor phase growth method, or thermally diffusing impurities into a silicon carbide single crystal layer that has been grown in advance. and so on.

However, impurities in the silicon carbide single crystal layer added during vapor phase growth are not all ionized at room temperature, and as the temperature rises, the carrier concentration in the silicon carbide single crystal layer decreases. - He rises. Therefore, the resistivity of the silicon carbide single crystal layer decreases as the temperature increases. Furthermore, when vapor phase growth is performed while adding impurities, many irregularities occur on the surface of the growing layer of silicon carbide single crystal. Therefore, the flatness of the surface of the channel layer made of single crystal silicon carbide deteriorates, which adversely affects the characteristics of the gate insulating film formed on the channel layer 7.

On the other hand, when forming a high-resistance layer by thermally diffusing impurities into a silicon carbide single crystal layer grown in advance, the diffusion constant of impurities in silicon carbide is small, and a high diffusion temperature of 1,600°C or higher is required. is necessary. Therefore, the impurity thermal diffusion method is not suitable as a process technology for silicon carbide semiconductor devices because it is difficult to control the impurity concentration and there is a risk of deterioration of the semiconductor substrate or silicon carbide single crystal layer used.

The present invention solves the 12 conventional problems, and its purpose is to provide a silicon carbide semiconductor device having a high-resistance silicon carbide single crystal layer that functions as an electrical insulating layer and a channel layer even in a high temperature region. Our goal is to provide the following.

(Means for Solving the Problems) The present invention lυj is a silicon carbide semiconductor device having an electrically insulating layer and an unoccupied layer, in which the electrically insulating layer and the channel layer are made of a single high-resistance silicon carbide monolayer. A predetermined amount of ions are implanted into a silicon carbide single crystal layer composed of a crystal layer, and the high resistance silicon carbide single crystal layer is grown on a semiconductor substrate to form an ion implantation layer in the surface region. It is formed by thermally annealing the ion-implanted layer, thereby achieving objective 1 above.

When forming the ion-implanted layer, ion implantation can be performed in one step or can be performed in multiple steps. In this case, by appropriately adjusting the injection conditions,
An ion-implanted layer having a predetermined impurity concentration and layer thickness is obtained. Examples of ions to be implanted include boron (B).
) ion, aluminum l, (A1) ion, gallium (
6a) Group I2 element ions such as ions can be mentioned, and boron ions are particularly preferred.

The obtained ion-implanted layer is then subjected to thermal annealing treatment. Thermal annealing treatment is performed using an inert gas (e.g. Ar
It is carried out at a temperature of about LOOG to 1300°C under an atmosphere of gas). This thermal annealing treatment activates the ion-implanted layer -1 to have high resistivity, forming a high-resistance silicon carbide single crystal layer that can function as an electrical insulating layer and a channel layer.

(Example) Examples of the present invention will be described below.

FIG. 1(a) shows an insulated gate field effect transistor (M-type SFET) which is an example of the silicon carbide semiconductor device of the present invention.
), the MOSFET was manufactured as follows.

First, as shown in Figure 1 (g)), vapor phase growth ([Vl
1) Using the method, the S1 single crystal substrate 1'' is non-doped 81
(: A single crystal layer 2 was grown. Next, boron ions ("B") were implanted into the surface region of the non-doped SiC single crystal layer 2 in two steps using an ion implanter. A B main injection layer 3 as shown in Figure (C) was formed.The injection conditions were as follows:
0 k e v and H) Okel, I, and the implantation amount of B ions is l XIO”cm−2 and 5
X l[]”cm-2.

And about 1. By performing thermal annealing treatment at ,000 to 1,300°C, the B ion-implanted layer 3 is activated and a high-resistance SiC single crystal layer (i.e., electrically insulating layer and A channel layer) 4 was formed.

When the resistivity of the high resistance SiC single crystal layer 4 was measured,
Almost no decrease in resistivity was observed over a wide temperature range, indicating that the high-resistance SiC single crystal layer 4 had sufficient performance as an electrical insulating layer and a channel layer.

Subsequently, a Sin film was formed on the high resistance SIC single crystal layer 4 by the [':Vfl method or plasma CVD method. Next, using potolithography. A predetermined region of the Sl02 film was opened by etching to form a field insulating film 5 (FIG. 1(C)). Note that a solution of hydrogen fluoride (1 liter) was used for etching. Then, using an ion implanter and using the field insulating film 5 as a mask, phosphorus ions (3
1P'') was injected.The injection conditions were: acceleration voltage, power, month, 00k
eV, and the amount of P ion implanted is 3 × 1014 cm-2
Met. Then, about 1,000 to 120[]℃
By performing a thermal annealing process, the P ion implanted region was activated, and a source region 6 and a drain region 7 as shown in FIG. 1(e) were formed.

Furthermore, after removing the field insulating film 5 in the portion corresponding to the gate region by etching, 1
The gate insulating film 8 was formed by performing thermal oxidation at 100° C. for 4 hours. lastly. Aluminum (81) was vacuum-deposited on the opening 11 portions corresponding to the train region 6 and the train region 7, and on the gate insulating film 1J on the gate insulating film 8 on the portion corresponding to the gate region, and then deposited using photolithography. ．． source electrode 9,
By forming the drain electrode 10 and the gate electrode l1, an M0SFIET as shown in FIG. 1(a) was obtained.

In the MOSFET thus obtained, the high resistance SiC single crystal layer 4 acts not only as an electrical insulating layer but also as a channel layer. In other words, when a voltage is applied to the gate electrode 11, a channel region is generated on the surface of the high resistance SiC single crystal layer 4, a current flows between the source region 6 and the drain region 7 through the channel region, and an FεT operation is performed. be exposed. When the transistor characteristics of this MOSFεT were investigated, a characteristic diagram as shown in FIG. 2 was obtained.

For comparison, B ion-implanted layer 3 was used instead. A MOSFET was fabricated in the same manner as in the above example except that a silicon carbide single crystal layer grown in a vapor phase while adding boron impurities was used.
BT was produced. The transistor characteristics of the obtained MOSFIET are shown in FIG.

As is clear from FIGS. 2 and 3, M
In OSFBT, as an electrical insulating layer and a channel layer,
Since the high resistance SiC single crystal layer 4 implanted with B ions is used, the characteristics of the gate insulating film 8 are improved, and
Source region 6 and drain region 7 to 8 of the channel layer
1. The leakage current to the single crystal substrate 1 was reduced. Furthermore, these good transistor characteristics were stable even in the high temperature range.

(Effects of the Invention) According to the present invention, a high-resistance silicon carbide single crystal layer that acts as an electrical insulating layer and a channel layer is formed by ion implantation. A silicon carbide semiconductor device with stable device characteristics up to a high temperature range can be obtained. Such a silicon carbide semiconductor device is particularly useful as a semiconductor device for high temperature operation. Further, the present invention makes it possible to produce various silicon carbide semiconductor devices (for example, gate insulated field effect transistors, etc.) on an industrial scale using ordinary ion implantation technology.

1? A cross-sectional view for explaining the manufacturing process of an example insulated gate field effect transistor, FIG. 2 is a diagram showing the device characteristics of the field effect transistor, and FIG. 3 is an insulated gate field effect transistor manufactured by a conventional method. FIG. 3 is a diagram showing element characteristics of an effect transistor.

1... Si single crystal substrate, 2... Non-doped SiC single crystal layer, 3... B ion implantation layer, 4... Electrical insulation layer and channel layer (high resistance SiC single crystal layer), 5... Filled insulation Film, 6... Source region, 7/ Drain region 8
...Gate insulating film, 9.. Source electrode, 10.. Drain electrode, 11. Gate electrode.

Claims (1)

[Claims] 1. A silicon carbide semiconductor device having an electrically insulating layer and a channel layer, wherein the electrically insulating layer and the channel layer are composed of a single high-resistance silicon carbide single crystal layer, and the high-resistance The silicon carbide single crystal layer is
Silicon carbide is formed by implanting a predetermined amount of ions into a silicon carbide single crystal layer grown on a semiconductor substrate, forming an ion implantation layer on the surface region, and thermally annealing the ion implantation layer. Semiconductor equipment.