JPH0228367A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To seek to improve the characteristics to maintain information of a semiconductor storage device by separating transfer MISFETs by means of a field insulating film using a groove deeper than those source and drain. CONSTITUTION:An n-type well region 2 is provided at the main face of a semiconductor substrate 1, and a field insulating film 3 is provided around a memory cell region at the main face of the n-type well region 2. Since a field insulating film 3 is constituted by burying an insulating film 4 in a groove deeper than the depths of the source 11 and the drain 12 of an n-channel MISFET at the main face of a semiconductor substrate 1, fellow transfer MISFETs are separated favorably from each other. If photoelectrons generated at the end of a drain region 11 enter a gate insulating film 10, the photoelectrons act on a channel region 20 to elevate the threshold, and they act on a source 11 and a drain 12 to reduce the leakage currents between them. Hereby, the characteristics to maintain information of a semiconductor storage device can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and is particularly effective when applied to a dynamic RAM.

[Conventional technology]

Dynamic RAM memory cells are transfer MI
It consists of an S FET and a capacitive element, but as the capacitive element becomes much smaller with miniaturization and higher integration, securing the capacitance value necessary for storing information has become an important issue. It's coming. Therefore, for example, a deep trench is dug in the main surface of a semiconductor substrate, the inner wall of this trench is covered with a silicon oxide film, and then two electrodes are placed in the trench and a dielectric film is formed to insulate between them. There is a technique of embedding a capacitive element (hereinafter referred to as a trench-type capacitive element). The technology for configuring a capacitive element in this groove is, for example, solid-state devices and materials.

Touki E, 1987, pp 15-18 (Ext
abstract of the 19th
conference on 5solid Stat
eDevices and Materials, T
OKYO, 1987, pp15-18) and SPC (
It is described as a Sheath Plate Capacitor) cell, and in the ppH-14 of the above document, S CC (Surrounded Capacitor) cell is described.
r Ce1l) The cell is written. The transfer MISFET is usually a p-channel MISFET.
In order to use an n-channel MISFET with faster operating speed, the transfer MISFET and the trench type capacitive element are formed on a p-type semiconductor substrate. The memory cell is surrounded by a field insulating film made of a silicon oxide film, and a channel stopper made of a p-type semiconductor region is provided below the field insulating film. This p-type channel stopper region.

n° type semiconductor region that is the source or drain of the transfer MISFET, and the transfer MISFET
is insulated from the Go-type semiconductor region which is the source or drain of the transfer MISFET of the adjacent memory cell.

Here, when positive charges and electrons are generated by the penetration of alpha (α) rays into the field insulating film, the easily movable electrons quickly disappear, and only the less mobile positive charges remain in the field insulating film. In this way, when positive charges are generated in the field insulating film, the two transfer MISFs that should have been insulated by the p-type channel stopper region
Leakage current begins to flow between the sources or drains of the ETs. Therefore, there is a dynamic RAM in which a p-channel MISFET is used as the transfer MISFET, and the transfer MISFET and the trench-type capacitive element are formed on an n-type semiconductor substrate. Beneath the field insulating film is an n-type region. This dynamic RAM is the source of the transfer MIS FET,
A parasitic MISFET consisting of a drain, a field insulating film, an n-type region (substrate) below it, and a word line extending over the field insulating film is a p-channel MISFET.
It is. Therefore, the positive charges generated in the field insulating film as described above act to make the parasitic p-channel MISFET non-conductive.

Leakage between transfer MISFETs can be reduced.

[Problem to be solved by the invention]

The inventor of the present invention discovered the following problem as a result of studying a semiconductor memory device using a p-channel MISFET as the transfer MISFET.

When the transfer MI 5FET is in the ON state, a strong electric field exists at the end of the drain region.

Therefore, pairs of hot electrons and hot holes are generated at the drain end. Of these hot holes and hot electrons, hot electrons more easily jump into the gate insulating film because the potential barrier between silicon and the silicon oxide film is lower. Then, the hot electrons that entered the gate insulating film are transferred to the p-channel MIS.
Since it acts to lower the threshold of the FET, leakage current between the source and drain increases.

Then, one electrode of the capacitive element is connected to the p-channel MISF
Since it is connected to the source or drain of the ET, there is a problem in that information retention characteristics deteriorate when the leakage current between the source and drain increases as described above.

An object of the present invention is to provide a technique that can improve the information retention characteristics of a semiconductor memory device.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, an n-type well region is provided on the main surface of the semiconductor substrate,
A field insulating film is provided around the memory cell region on the main surface of the n-type well region, a trench capacitor is provided in the capacitor region of the memory cell region, and the trench capacitor is provided on the main surface of the memory cell region. A p-type semiconductor region is provided in a portion adjacent to the p-type semiconductor region, and a predetermined semiconductor region serving as a source or drain is connected to a predetermined electrode of the trench-type capacitive element on the main surface of the p-type semiconductor region, and a switch of the memory cell is provided. It is provided with an n-channel region 5FET used as an element. Further, the field insulating film is formed by embedding an insulating film in a groove deeper than the source and drain of the n-channel MrsFET on the main surface of the semiconductor substrate.

[Effect]

According to the above-described means, the transfer MISFETs are separated by a field insulating film using a trench deeper than their sources and drains. Also,
Directly below the transfer MISFET is a p-type semiconductor region, and directly below the field insulating film is an n-type region (well region).

For this reason, the structure is composed of the field insulating film, an n-type region immediately below the field insulating film, the P-type semiconductor regions on both sides of the field insulating film, and a conductor (for example, a word line) extending over the field insulating film. The parasitic MISFET is a p-channel MISFET, and α
The positive charge generated by the line penetration acts to increase the absolute value of the threshold of the parasitic p-channel MISFET. Further, the transfer MISFET is an n-channel MISFET, and its source and drain regions are of the opposite conductivity type to the P-type semiconductor region that is the source and drain regions of the parasitic P-channel MISFET. For these reasons, the transfer MISFETs are well isolated.

On the other hand, the transfer MISFET is an n-channel MISFET as described above, and the carriers forming the channel are electrons. When hot electrons generated at the edge of the drain region enter the gate insulating film, the hot electrons act to increase the threshold of the channel region and reduce the leakage current between the source and drain. act. Therefore, the amount of charge in the capacitive element, that is, the amount of information flowing out is reduced.

From the above, the information retention characteristics of the semiconductor memory device can be improved.

[Embodiment I of the invention]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory device according to Embodiment I of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view showing a pattern of a semiconductor memory cell and a semiconductor region provided under a field insulating film surrounding the memory cell of a semiconductor memory device according to Example 2 of the present invention, and FIG. 2 is a cross-sectional view of a memory cell at a portion corresponding to the cutting line 1--2.

FIG. 3 is a sectional view of the memory cell at a portion corresponding to the section line ``--'' in FIG.

Note that, in order to clarify the pattern of the semiconductor region under the memory cell, FIG. 1 does not show the semiconductor regions, electrodes, etc. of the transfer MI 5FET and the capacitive element.

In FIG. 1, 1 is a semiconductor substrate made of p-type single crystal silicon. The area T surrounded by the solid line is the area where two transfer MI 5FETs are provided (hereinafter simply referred to as MI
There is a region edge in the SFET region T, and a region C surrounded by a solid line is a region in which one capacitive element is provided (hereinafter referred to as capacitive element region C).

A portion of the MISFET region T indicated by a dotted line is a portion to which a data line extending over the semiconductor substrate l is connected. The transfer MI in the middle region of the MISFET region T is bordered by the part where this data line is connected.
A SFET is provided.

Then, the transfer MISFET of the middle region blade of the MISFET region T and the capacitive element region C adjacent thereto.
One memory cell is constituted by the capacitive element provided in the . That is, the combined portion of the MISFET region T and the capacitor region C is the memory cell region. The memory cell area is surrounded by a field insulating film 3 made of a silicon oxide film.

The field insulating film 3 is indicated by a large number of black dots (.) in FIG.

Next, as shown in FIGS. 2 and 3, an n-type well region 2 is formed below the memory cell array region of the semiconductor substrate l. The lower region of the MISFET region T is a blade-type semiconductor region 9, and further below that is a p°-type semiconductor region 8. p° type semiconductor region 8 and p− type semiconductor region 9
The pattern seen from above is between the M r S FET regions. Immediately below the field insulating film 3 is an n-type well region 2. The side surfaces of the p-type semiconductor region 8 and the p--type semiconductor region 9 are surrounded by a field insulating film 3 and an insulating film 4 made of a silicon oxide film on the side surface of a trench in which a capacitive element, which will be described later, is provided. The depth from the surface of semiconductor substrate 1 to the bottom of n-type well region 2 is approximately 5 μm. Furthermore, the depth to the bottom of the P° type semiconductor region 8 is 1 μm.
The bottom of the field insulating film 3 also reaches the same depth as the p° type semiconductor region 8.

Next, the configurations of the transfer MISFET and capacitive element of the memory cell will be explained.

As shown in FIG. 2, the transfer MISFET includes a gate insulating film 10 and a gate electrode 1 that also serves as a word line WL.
4, an n-type semiconductor region 11 at the end of the source and drain on the channel region side, and a go-type semiconductor region 12 forming a portion other than the n-type semiconductor region 11 of the source and drain. The gate insulating film 10 is made of a thin silicon oxide film. The gate electrode (word line WL) 14 is made of, for example, a two-layer film in which a transition metal silicide film is laminated on an A-type polycrystalline silicon film. A pad electrode 16 made of an n° type polycrystalline silicon film is connected to the n° type semiconductor region 12 which becomes a part of the drain when reading information. It is connected to a data line 19 through a hole 18.

15 is an insulating film that insulates between the pad electrode 16 and the gate electrode 14. Next, the capacitive element is composed of one electrode 5 made of a Go-type polycrystalline silicon film, the other electrode 7 made of an n-type polycrystalline silicon film, and a dielectric film 6 insulating between them. ing. The dielectric film 6 is made of, for example, a silicon oxide film. These electrodes 5 and 7 and the dielectric film 6 are provided in a groove dug in the main surface of the semiconductor substrate 1. An insulating film 4 made of a silicon oxide film is provided on the side surface of the groove to insulate the electrode 5 from the p° type semiconductor region 8 and the p− type semiconductor region 9. Electrode 5 is connected to n-type well region 2 at the bottom of the trench.

In this way, the capacitive element includes the electrodes 5, 7 and the dielectric film 6.
This is a groove-type capacitive element provided in a groove of the semiconductor substrate 1. The electrode 7 is connected to a predetermined Go-type semiconductor region 12 via a Go-type semiconductor region 13 . An insulating film 24 made of, for example, a silicon oxide film provides insulation between the electrode 7 and the word line WL extending thereon.

The impurity concentration of the n-type well region 2 is I×101'
It is about atoms/a1. The impurity concentration of the p type semiconductor region 8 is about I x 10'' atoms/cd,
The impurity concentration of the p-type semiconductor region 9 is 5×10”a
It is about toms/aj.

Next, the potential of each semiconductor region will be described.

The potentials of the n-type semiconductor region 11, the Go-type semiconductor region 12, and the Go-type semiconductor region 13 of the transfer MISFET are as follows.
Depending on information writing or reading operations.

Ground potential Vss or high-level reference potential V for electronic circuits
c cFor example, 5 ■, or 1/2 of it, or 1/
It changes variously, such as 2Vcc. The potential of the semiconductor substrate 1 is
Ground potential Vs, which serves as a low-level reference for the operation of electronic circuits
s, for example, fixed to Ov.

and the n provided in the memory cell array area.
Like the semiconductor substrate 1, the mold well region 2 is also at the ground potential Vss.
be made into p° type semiconductor region 8 and p− type semiconductor region 9
is not supplied with a constant potential and is left floating. Therefore, the p° type semiconductor region 8 and p
The potential of the - type semiconductor region 9 is determined by the capacitive coupling between the n-type well region 2 and the n-type semiconductor region 11 of the transfer MI S FET. The potential is determined by the capacitive coupling with the ri'' type semiconductor region 12 and the capacitive coupling with the n° type semiconductor region 13. Therefore, the p゛ type semiconductor region 8 and the p− type semiconductor region 9 , always n-type semiconductor region 1
1. Go-type semiconductor region 12. The potential is lower than that of each of the r1'' type semiconductor regions 13, and a reverse bias state is maintained.

Note that the n-type well region in which the p-channel MISFET constituting the peripheral circuit is provided is provided separately from the n-type well region 2 of the memory cell array region, and its potential is a high-level basis for the operation of the electronic circuit. Potential Vcc, for example 5
Fixed to v.

Next, element isolation between memory cells will be described.

As shown in FIGS. 2 and 3, as described above, the n-type semiconductor region 11 of each transfer MISFET is
．． Below each of the r1'' type semiconductor region 12 and the n'' type semiconductor region 13 is a p- type semiconductor region 9, and there is always a reverse bias between them. Further, below the p-type semiconductor region 9 is a p゛-type half-quadruple region 8, and between each of the p-type semiconductor regions 8.

It is separated by field insulation 1113 and n-type well region 2. Here, if α rays jump into the field insulating film 3 and a positive charge is generated, the threshold value on the surface of the n-type well region 2 is radially inward to the negative side. That is, leakage current between the two p° type semiconductor regions 8 is made difficult to flow. From these facts, the two transfer M
There is good isolation between the I5FETs.

Further, the p° type semiconductor region 8 is connected to the p° type semiconductor region 8 from the n type well region 2.
The extension of the depletion layer toward the - type semiconductor region 9 is suppressed. Thereby, even if the depth from the surface of the semiconductor substrate 1 to the bottom of the p° type semiconductor region 8 is shallow.

Punch-through between the n-type well region 2 and each of the n-type semiconductor region 11, the Go-type semiconductor region 12, and the n°-type semiconductor region 13 can be prevented.

Next, if hot carriers are generated at the end of the drain region (n-type semiconductor region 11) of the transfer MISFET, and these hot electrons jump into the gate insulating film 4, these hot electrons will pass through the threshold of the n-channel MISFET. It acts to increase the value.

This reduces leakage current between the source and drain and improves information retention characteristics.

The field insulating film 3 is formed by forming a trench with a depth of about 1 μm on the surface of the semiconductor substrate 1 (main surface of the n-type well region 2).
The inner wall of this trench is thermally oxidized to form a silicon oxide film (with a thickness of approximately 1000 mm), and then a silicon oxide film is buried in the trench by, for example, CVD.

That is, in the field insulating film 3, the inner wall portion of the trench is made of a silicon oxide film formed by thermal oxidation, and the central portion is made of a silicon oxide film formed by, for example, CVD. The gate insulating film 10 is formed by thermally oxidizing the surface of the semiconductor substrate 1 (p-type semiconductor region 9). The insulating film 15 is made of, for example, a silicon oxide film formed by CVD. The interlayer insulating film 17 is formed by laminating a silicon oxide film and a phosphorus silicate glass (PSG) or borophosphosilicate glass (BPSG) film by CVD, for example. The data line is made of aluminum film.

[Embodiment of the invention■]

4 is a plan view of a memory cell of a semiconductor memory device according to the embodiment (2) of the present invention; FIG. 5 is a sectional view taken along the line (■--) of FIG. 4; FIG. It is a sectional view taken along the -VI cutting line.

The dynamic RAM of this embodiment (2) is of the -intersection type.

In FIGS. 4 to 6, Epi is an epitaxial layer formed from the p-type semiconductor region 9 to the electrode 7 of the trench type capacitive element. The epitaxial layer Epi is also formed on the insulating film 4.

Transfer MISFE is applied to this epitaxial layer EPi.
an n-type semiconductor region 11 of T, an n″-type semiconductor region 12,
A channel region (p-type) 20 is formed.

In FIG. 4, the epitaxial layer Epi is shown with diagonal lines, and the insulating film 4 and dielectric film 6 on the inner wall of the trench of the trench type capacitive element are shown with many dots (.). The field insulating film 3 is not marked with a dot (.). One of the two n° type semiconductor regions 12 is connected to the upper surface of the electrode 7. That is, unlike the memory cell of the embodiment (2), the transfer MIS is
The FET and a predetermined electrode 7 of the trench type capacitive element are connected.

The surface of the semiconductor substrate 1 (p-type semiconductor region 9) p.

The depth to the bottom of the type semiconductor region 8 is about 1 μm as in Example I above.

As described above, the configuration of the memory cell of the embodiment (2) can provide the same effect as the memory cell of the embodiment I, and furthermore, since the Go-type semiconductor region 12 is directly connected to the upper surface of the electrode 7, transfer The reliability of isolation between the MI5FET and the n-type semiconductor region 2 can be improved.

[Embodiment of the invention■]

FIG. 7 is a sectional view of a memory cell of a dynamic RAM according to Example 2 of the present invention.

In FIG. 7, 21 is a transition metal silicide film,
For example, titanium silicide (TIS i2) is used. Transfer MI with this transition metal silicide film 21
The SFET and a predetermined electrode 7 of the trench type capacitive element are connected. The transition metal silicide film 21 is also provided on the surface of the n-type semiconductor region 11 on the side opposite to the one connected to the electrode 7. Since the resistance value of the transition metal silicide film 21 is small, the source and drain of the transfer MISFET can be formed only from the n-type semiconductor region 11. However, Example 1. Similarly to the transfer MISFET of If, the source and drain may be formed of an n-type semiconductor region 11 and an n°-type semiconductor region 12.

The transition metal silicide film 21 is formed by forming a Ti film on the entire surface of the semiconductor substrate 1 by, for example, sputtering, and then performing annealing to cause the Ti film and silicon film to react. The unreacted Ti film is removed by etching.

That is, the transition total bending silicide film 21 at the self-line
is formed.

This is Salicide (Self Align 5ili)
cide).

With the configuration of the dynamic RAM of the embodiment (2) described above, the same effects as in the embodiment (2) can be obtained.

[Embodiment of the invention■]

FIG. 8 is a plan view of a memory cell of a dynamic RAM according to Example 2 of the present invention, and FIG. 9 is a cross-sectional view taken along the line IX--IX in FIG.

As shown in FIGS. 8 and 9, the memory cell of this embodiment (2) has a structure in which a trench type capacitive element surrounds a transfer MISFET. The trench type capacitive element is Example R
-Dielectric film 6 directly on the inner wall of the groove, unlike the trench type capacitor element of
has been established. The only electrode provided in the groove is the electrode 7. This electrode 7 is connected to a wiring having a predetermined potential at a predetermined portion of the memory cell array area. A thick insulating film 22 is provided under the electrode 7, and around this a thick insulating film 22 is provided.
.

A mold channel stop 23 is provided. Carriers serving as information are held at the interface between the dielectric film 6 and the n-type well region 2. The field insulating film 3 and dielectric film of the P' type semiconductor region 8 and the p- type semiconductor region 9 extend from the Go-type semiconductor region 12 on the side opposite to the side to which the data line 19 of the transfer MISFET is connected to the n-type well region 2. An n-type semiconductor region 25 is provided in a portion that is in contact with the semiconductor region 6. The dynamic RAM of this embodiment (2) is of the one-intersection type.

With the configuration of the embodiment (2) described above, the same effects as the dynamic RAM of the embodiment I can be obtained.

As explained above, according to the dynamic RAM memory cells of Examples 1 to 2, n
A type well region 2 is provided, a field insulating film 3 is provided around the memory cell region on the main surface of the n-type well region 2, and a trench type capacitive element is provided in the capacitive element region of the memory cell region,
A p-type semiconductor region (p' layer 8 and p- layer 9) is provided in a portion of the main surface of the memory cell region adjacent to the trench-type capacitive element, and the p-type semiconductor region (p'' layer 8 and p- layer On the main surface of 9), a predetermined semiconductor region 12 (n-type semiconductor region 11 in Example 2) serving as a source or drain is connected to a predetermined electrode 7 of the trench type capacitive element (Example 2 is different). Further, the field insulating film 3 is formed on the main surface of the semiconductor substrate 1 at a depth deeper than the source and drain of the n-channel MISFET. By embedding an insulating film in a deep trench, the transfer MISFETs are separated by a field insulating film 3 using a trench deeper than their sources and drains. Directly below the transfer MISFET is a p-type semiconductor region (p'' layer 8 and p- layer 9), and directly below the field insulating film 3 is an n-type semiconductor region.
This is a mold region (well region 2). For this reason, the field insulating film 3, the n-type region 2 immediately below it, the p-type semiconductor regions (8, 9) on both sides of the field insulating film 3, and extending over the field insulating film 3 The parasitic MISFET configured with a conductor (for example, a word line) is an n-channel MISFET, and α
The positive charge generated by the line penetration acts to increase the absolute value of the threshold of the parasitic n-channel MISFET. Further, the transfer MISFET is an n-channel MISFET, and its source and drain regions are of the opposite conductivity type to the p-type semiconductor regions (8, 9) that are the source and drain regions of the parasitic MISFET.

For these reasons, the transfer MISFETs are well isolated.

On the other hand, the transfer MISFET is an n-channel MISFET as described above, and the carriers forming the channel are electrons. When hot electrons generated at the end of the drain region enter the gate insulating film 10, the hot electrons act to increase the threshold of the channel region, reducing leakage current between the source and drain. It works like this. Therefore, the amount of charge in the capacitive element, that is, the amount of information flowing out is reduced.

From the above, the information retention characteristics of the semiconductor memory device can be improved.

Further, in Examples I to ■, transfer MI 5F
By providing the p° type semiconductor region 8 between the p-type semiconductor region 9 where ET is provided and the n-type well region 2, the Since the extension of the depletion layer becomes smaller, the n-type well region 2 and the n-type semiconductor region 1 of the transfer MrS FET
1. Separation from the go-type semiconductor region 12 (in Example 2, the n°-type semiconductor region 13 is also added) is ensured.

Furthermore, in Example 3, the n-type semiconductor region 11 and n° which are the source and drain of the transfer MISFET are
By forming the n-type semiconductor regions 12 in the epitaxial layer Epi grown on the semiconductor substrate 1, these n-type semiconductor regions 11. Since the distance between the n'' type semiconductor region 12 and the n type well region 2 is increased, the reliability of element isolation between them is increased.

In Examples (2) and (2), the connection between the predetermined electrode 7 of the trench-type capacitive element and the predetermined Go-type semiconductor region 12 (n-type semiconductor region 11 in Example (2)) of the transfer MISFET is made on the upper surface of the electrode 7. By doing this, since the n° type semiconductor region 13 of Example 2 is not provided, the reliability of element isolation between the transfer MISFET and the n type well region 2 can be improved.

The present invention has been specifically described above based on examples, but 1.
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

Transfer MISFETs are well isolated. In addition, the transfer MISFET is an n-channel MISFET.
Since it is made of T, hot electrons entering the gate insulating film act to reduce leakage current between the source and drain. For these reasons, the amount of charge in the capacitive element, that is, the amount of information flowing out is reduced, and the information retention characteristics are improved.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a pattern of a semiconductor region provided under a memory cell and a surrounding field insulating film of a semiconductor memory device according to Example I of the present invention, and FIG. 3 is a cross-sectional view of a memory cell in a portion corresponding to the section line ■-■ in FIG. 1; FIG. 4 is a cross-sectional view of a memory cell in a portion corresponding to the section line ■-■ in FIG. FIG. 3 is a plan view of a memory cell of the semiconductor memory device of Example (2). 5 is a cross-sectional view taken along the line ■--■ in FIG. 4, FIG. 6 is a cross-sectional view taken along the line VI-VI in FIG. 4, and FIG. 7 is a dynamic RAM according to the embodiment (■) of the present invention. FIG. 3 is a cross-sectional view of a memory cell. FIG. 8 is a plan view of a memory cell of a dynamic RAM according to the embodiment (2) of the present invention, and FIG. 9 is a cross-sectional view taken along the line (2)--(2) in FIG. In the figure, 1... semiconductor substrate, 2... n-type well region,
3...Field insulating film, 4.15.22.24...
・Insulating film, 5.7... Electrode, 6... Dielectric film, 8.
...p° type semiconductor region, 9...p-type semiconductor region, 1
4... Gate electrode, 16... Pad electrode, 10...
・Gate insulating film, 11.12... Source. Drain region, 13.25...n° type semiconductor region, E
Pi: epitaxial layer, 20: channel region, 21: transition metal silicide film, 23: Go-type channel stopper.

Claims (1)

[Claims] 1. An n-type well region is provided on the main surface of a semiconductor substrate, a field insulating film is provided around a memory cell region on the main surface of the n-type well region, and a capacitive element region in the memory cell region is provided. A trench-type capacitive element is provided in the main surface of the memory cell region, a p-type semiconductor region is provided in a portion adjacent to the trench-type capacitive element on the main surface of the memory cell region, and a predetermined region serving as a source or a drain is provided on the main surface of the p-type semiconductor region. 1. A semiconductor memory device comprising an n-channel MISFET whose semiconductor region is connected to a predetermined electrode of the trench-type capacitive element and is used as a switch element of the memory cell. 2. The field insulating film is formed by embedding the insulating film in a groove deeper than the source and drain of the n-channel MISFET on the main surface of the semiconductor substrate. The semiconductor memory device according to scope 1.