JPH02284077A - Testing device for logic integrated circuit - Google Patents

Abstract

PURPOSE:To omit the time required to read a test pattern out of an input part and stores it in a mass storage buffer memory by providing a memory part equipped with >=2 mass storage buffer memories. CONSTITUTION:The testing device is provided with the mass storage buffer memories 5a and 5b as the memory part 4, and a selection part 6 which selects the output signals of the both. Then the test pattern is stored in the mass storage buffer memory 5a from the input part 2 through a control part 1 to test the function of the integrated circuit to be tested (DUT). During the function test, the mass storage buffer memory 5 is selected and read 6. The test pattern is not transferred to a pattern generation part 7, so the test pattern read out of the input part 2 can be stored in the mass storage buffer memory 5b even during the test of DUT by using the mass storage buffer memory 5a. Consequently, the test pattern need not be read in from the input part 2 through the control p[art 1 right before a next DUT is tested, so the time is shortened.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a testing device for logic integrated circuits.

[Conventional technology]

FIG. 2 is a block diagram of an example of a conventional logic integrated circuit testing device (hereinafter referred to as a logic tester).

The control unit 1 includes a test program that describes the test conditions of the integrated circuit under test (hereinafter referred to as DUT) to be tested by the logic tester, and a test program that interprets the test program and sets the test conditions to each part of the logic tester. An interpreter that reads from the input section 2 a test pattern that describes the input pattern of the DUT or the expected output pattern from the CUT.
Store programs.

The input unit 2 reads the test program and test pattern from a storage medium such as a floppy disk or magnetic tape.

The pass line 3 transfers the test conditions obtained by interpreting the test program by the control section 1 to each section.

Large capacity buffer memory 4 temporarily stores test patterns.

The pattern generator 7 receives and stores a test pattern specified by a test program from among the test patterns previously stored in the large-capacity buffer memory 4, and generates the test pattern at a frequency specified by the test program. .

The test head section 8 outputs the test pattern from the pattern generation section 7 under input voltage conditions specified by the test program.
The output from the DUT is compared with the test pattern under the specified judgment voltage condition to determine whether they match.

To explain in more detail, when performing a functional test of the DUT, the control section 1 reads a test pattern from the input section 2 and stores it in advance in the large capacity buffer memory 51 via the pass line 3.

Further, a test program is read from the input section 2 and stored in the control section 1.

At the start of the test, the interpreter program is activated to interpret the test program, and the input voltage condition of the test pattern to the CUT and the judgment voltage of the output from the DUT to the test pattern are set in the test head section 8 via the pass line 3. do.

5. Store test patterns specified by the test program in large capacity buffer memory. The pattern generator 7 then generates a test pattern jiff at a frequency specified by the test program.

The test head section 8 inputs a test pattern to the DUT at an input voltage specified by the test program, compares the output from the DUT with the test pattern at a determination voltage, and determines whether it matches the expected pattern.

[Problem to be solved by the invention]

Recently, as the degree of integration of logic integrated circuits has increased and their functions have become more complex, test patterns have become longer and longer.

Often, it is becoming impossible to store all test patterns in the pattern generator at once.

Therefore, one type of test pattern is divided into complex parts and temporarily stored in a large-capacity buffer memory.
Then, the divided test patterns are transferred one by one from the large-capacity buffer memory as needed, and by repeating the process of generating test patterns, all the test patterns are input to the CUT and a functional test is performed.

In the conventional logic tester illustrated in FIG. 2, a long test pattern is read from the input section 2 and stored in the large-capacity buffer memory 5a, so that the test pattern reading time becomes long, ranging from several minutes to several tens of minutes.

Furthermore, as test patterns become longer and the number of output terminals also increases, the test pattern reading time is becoming longer.

During a CUT functional test, test patterns are almost always transferred from the large-capacity buffer memory to the pattern generation section, so it is not possible to read and store test patterns of other DUTs from the input section into the large-capacity buffer memory during the functional test. becomes impossible.

Therefore, when the type of DOT changes and the type of test pattern used changes, the test pattern must be read after the test of the CUT being tested is completed, and the logic tester is test must be canceled.

There has been a drawback that as the proportion of test pattern reading time in the operating time of a logic tester increases, the number of DUTs that can be tested with the logic tester also decreases.

[Means to solve the problem]

The logic tester of the present invention includes a buffer memory section that stores a test pattern output from a tester control section, and supplies the test pattern read from the buffer memory section to an integrated circuit under test via a pattern generation section and a test head section. In a test circuit for a logic integrated circuit, the buffer memory section has a plurality of internal buffer memory sections, and during a functional test, one internal buffer memory section is selected and read, and no test pattern is read out. The next test pattern and test program are stored in one internal buffer memory section.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

The logic tester is different in that a large capacity buffer memory 5m having a common input terminal with the large capacity buffer memory 5a of FIG. 2 is provided as a memory section 4, and a selection section 6 for selecting both output signals is provided. Other than this point, it is the same as the conventional logic tester.

A test pattern is stored in the large-capacity buffer memory 5a from the input section 2 via the control section 1, and a functional test of the DUT is performed.

During the functional test, large capacity buffer memory 5. is selected and read out by the selection section 6.

Since the test pattern is not transferred to the pattern generator 7 in the large capacity buffer memory 5b, even during a functional test of the DUT using the large capacity buffer memory 5a, the input unit 2
The test pattern read from the large capacity buffer memory 5
It becomes possible to store it in b.

That is, the DO to be tested next after the DUT currently being tested.
By storing the test pattern T in the large-capacity buffer memory 5b, there is no need to read the test pattern from the input section 2 via the control section 1 immediately before testing the next DUT, and the time required is reduced. .

Here, the number of large capacity buffer memories may be increased to three or more.

〔Effect of the invention〕

As explained above, by providing a memory section equipped with two or more sets of large-capacity buffer memories, the present invention can omit the time required to read the test pattern from the input section into the large-capacity buffer memory and store it. Therefore, the longer the test pattern becomes, the more effective it can be expected.

Furthermore, there is no waiting time for loading test patterns, and the number of tests per logic tester increases.
It can also be expected to reduce testing costs.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of an example of a conventional logic tester. DESCRIPTION OF SYMBOLS 1... Control part, 2... Input part, 3... Pass line, 4... Memory part, 5m, 5b... Large capacity buffer memory, 6... Selection part, 7... Bang generation part, 8・
...Test head section. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] A test circuit for a logic integrated circuit that includes a buffer memory section that stores a test pattern output from a tester control section, and supplies the test pattern read from the buffer memory section to an integrated circuit under test via a pattern generation section and a test head section. In this case, the buffer memory section has a plurality of internal buffer memory sections, and during a functional test, one internal buffer memory section is selected and read, and the test pattern is read out from the internal buffer memory section that has not been read out. A logic integrated circuit testing device characterized by storing the following test patterns and test programs.