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JPH02273923A - Manufacture of semiconductor substrate - Google Patents

Manufacture of semiconductor substrate

Info

Publication number
JPH02273923A
JPH02273923A JP9693189A JP9693189A JPH02273923A JP H02273923 A JPH02273923 A JP H02273923A JP 9693189 A JP9693189 A JP 9693189A JP 9693189 A JP9693189 A JP 9693189A JP H02273923 A JPH02273923 A JP H02273923A
Authority
JP
Japan
Prior art keywords
wafer
semiconductor substrate
bonded
outer peripheral
diameter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9693189A
Other languages
Japanese (ja)
Inventor
Tadahide Hoshi
星 忠秀
Kazuhiro Tanaka
一宏 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Priority to JP9693189A priority Critical patent/JPH02273923A/en
Publication of JPH02273923A publication Critical patent/JPH02273923A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To contrive the prevention of the generation of a break, a crack and the like in the outer peripheral part of a wafer by a method wherein the diameter of a first wafer is left without being changed and at the same time, the unbonded outer peripheral part, at which the first wafer and a second wafer oppose to each other pinching a void between them, of the wafer is removed. CONSTITUTION:A bonded semiconductor substrate (a bonded wafer) 14 is formed by a method wherein the fellow mirror-polished main surfaces of first and second semiconductor substrates (first and second wafers) 11 and 12 performed a bevel work 16 on their sidewalls are closely adhered to each other, are heat-treated and are integrally formed, and a joined semiconductor substrate 15 is formed by a method wherein the fellow main surfaces, which are mirror- polished and on the main surface of a first semiconductor substrate 11a on at least one side of which an oxide film 13 is applied, of the first substrate 11a and a second semiconductor substrate 12, which are performed a bevel work 16 on their sidewalls, are closely adhered to each other, are heat-treated and are integrally formed. The diameter of the substrate 11 of the substrate 14 is left without being changed and at the same time, the sidewall of the substrate 14 is ground so that an unbonded outer peripheral part, at which the substrates 11 and 12 oppose to each other pinching a void between them, does not exist. In such a way, the unbonded outer peripheral part, that is, the outer peripheral part, at which the first and second wafers oppose to each other pinching a void between them, is removed. Thereby, a supply of the bonded wafer, in which a break, a crack and the like are not generated in its outer peripheral part, becomes possible.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は、半導体基板の製造方法に関するもので、特に
半導体装置用の2枚の半導体基板を密着して一体化した
接着半導体基板の製造に使用されるものである。
[Detailed Description of the Invention] [Object of the Invention] (Industrial Field of Application) The present invention relates to a method for manufacturing a semiconductor substrate, and in particular to an adhesive method for closely integrating two semiconductor substrates for a semiconductor device. It is used for manufacturing semiconductor substrates.

(従来の技術) 半導体装置用の2枚の半導体基板(以下ウェーハと呼ぶ
)を密着して、一体化した接着ウェーハの従来の製造方
法について、図面を参照してその概要を説明する。 ま
ず被接着面を鏡面研磨した従来のウェーハ11は、第5
図(a)に示すように、表面の酸化膜の有無に拘らず清
浄化洗浄処理を行なう、 同図(b)に示すように、鏡
面どうしを清浄雰囲気下で密着し、物理的に接着する。
(Prior Art) An outline of a conventional manufacturing method of a bonded wafer in which two semiconductor substrates (hereinafter referred to as wafers) for semiconductor devices are brought into close contact and integrated will be explained with reference to the drawings. First, the conventional wafer 11 whose surface to be bonded is mirror-polished is
As shown in Figure (a), the cleaning process is performed regardless of the presence or absence of an oxide film on the surface. As shown in Figure (b), the mirror surfaces are brought into close contact with each other in a clean atmosphere and physically bonded. .

次に同図(c)に示すように、赤外線透過法により、被
接着面の間隙の有無を調べるボイド検査を行なう、 次
に同図(d)に示すように、200℃以上、通常は11
00℃で約2時間の熱処理を施し、一体化された1枚の
接着ウェーハ上1としている。
Next, as shown in (c) of the same figure, a void inspection is performed to check the presence or absence of gaps on the bonded surface using an infrared transmission method.Next, as shown in (d) of the same figure, the temperature is 200°C or higher, usually 11
A heat treatment was performed at 00° C. for about 2 hours to form an integrated bonded wafer 1.

しかし、第6図(a)に示すように、ウェーハ11の外
周部には、ベベル(傘状)加工が施され、外周面は本状
になっている。 更に鏡面研磨等の表面処理により、外
周面には面ダレ(破線で示す)が発生する。 このよう
なウェーハを接着すると、接着ウェーハ上上の外周部1
2は、ベベル面と面ダレのため未接着となる。 この状
態で素子製造工程に進むと、欠けや割れを誘発する原因
となるほか、工程汚染につながる。 このなめ第6図(
b)に示すように、未接着部を削り取るように、外周研
削工程を加え、ウェーハ径の小径化を行なっている。 
即ち、例えば、口径125 nnφのウェーハを第6図
に示すように接着した場合には、接着ウェーハ上上の外
周部を研削し、ベベル加工が施された口径100 in
φのウェーハに形成していた。
However, as shown in FIG. 6(a), the outer peripheral portion of the wafer 11 is beveled (umbrella-shaped) so that the outer peripheral surface is book-shaped. Furthermore, due to surface treatment such as mirror polishing, surface sag (indicated by a broken line) occurs on the outer peripheral surface. When such wafers are bonded, the outer periphery 1 on the bonded wafer
No. 2 is not bonded due to the beveled surface and surface sag. Proceeding to the element manufacturing process in this state not only causes chipping and cracking, but also leads to process contamination. This lick Figure 6 (
As shown in b), the wafer diameter is reduced by adding an outer periphery grinding process to scrape off the unbonded portion.
That is, for example, when wafers with a diameter of 125 nnφ are bonded as shown in FIG.
It was formed on a φ wafer.

ウェーハを接着した際、ベベル面や面ブレの影響で、未
接着となる部分は、外周から2〜3Ill程度のところ
までである。 外周に未接着部分がない基板にするため
には、その部分だけを削り取れば良いのだが、そうする
と通常のウェーハロ径の寸法規格、例えば100 nm
φ、125IIIIφ、1501111φ等からはずれ
、このため汎用性がなくなってしまい、例えばウェーハ
を保持又は収納する従来の治具や器具の共通使用ができ
なくなる。
When wafers are bonded, the portion that is not bonded due to the bevel surface or surface wobbling is about 2 to 3 Ill from the outer periphery. In order to create a substrate with no unbonded parts on the outer periphery, it would be sufficient to scrape off only that part, but if this is done, the standard wafer diameter size standard, for example 100 nm, would be required.
φ, 125IIIφ, 1501111φ, etc., and therefore lacks versatility, and for example, conventional jigs and instruments for holding or storing wafers cannot be used in common.

そのため従来技術においてウェーハの口径を小径化する
際、150 niφは125IIIIφに、125 i
lφは1001nφという具合に、1ランク径を小さく
している。 従って長時間の外周研削工程が必要であり
、又径を小さくすることによりチップ形成面積が減少し
、ウェーハのコスト上昇となっていた。
Therefore, when reducing the diameter of the wafer in the conventional technology, 150 niφ becomes 125IIIφ, 125 i
lφ is 1001nφ, so that the diameter of one rank is reduced. Therefore, a long outer circumferential grinding process is required, and by reducing the diameter, the chip forming area is reduced, leading to an increase in the cost of the wafer.

(発明が解決しようとする課題) これまで述べたように、接着ウェーハの外周部は、ベベ
ル面や面ダレにより未接着となり、そのままの状態で、
素子製造工程に進むとウェーハ外周部の欠けや割れを生
じ、工程汚染につながる。
(Problems to be Solved by the Invention) As described above, the outer peripheral part of the bonded wafer becomes unbonded due to the beveled surface or surface sagging, and if left as it is,
When proceeding to the element manufacturing process, chips and cracks occur on the outer periphery of the wafer, leading to process contamination.

これを防ぐために外周の未接着部のみを除去すると、ウ
ェーハの口径が標準の寸法規格からはずれ、汎用性がな
くなる。 汎用性を維持するため、更に研削して、1ラ
ンク径の小さい標準寸法とするのは、生産上無駄が多い
If only the unbonded portion on the outer periphery is removed in order to prevent this, the diameter of the wafer will deviate from the standard dimensions, resulting in loss of versatility. In order to maintain versatility, it is wasteful in terms of production to further grind the material to a standard size that is one rank smaller in diameter.

本発明の目的は、2枚の半導体ウェーハを密着一体化し
て、1枚の接着ウェーハを製造する際に、前記従来技術
の問題点を解消し、基板の口径を減少させることなく、
且つウェーハ外周部の欠け、割れ等のない接着ウェーへ
の製造方法を提供することである。
An object of the present invention is to solve the problems of the prior art when manufacturing one bonded wafer by closely integrating two semiconductor wafers, and to solve the problems without reducing the diameter of the substrate.
Further, it is an object of the present invention to provide a method of manufacturing a bonded wafer without chipping, cracking, etc. on the outer periphery of the wafer.

[発明の構成] (課題を解決するための手段) 本発明の半導体基板(ウェーハ)の製造方法は、側壁に
ベベル加工を施した第1及び第2の半導体基板の鏡面研
磨された主面どうし、又は鏡面研磨され且つ少なくとも
一方の前記基板主面に酸化膜を付けた主面どうしを密着
し、熱処理して一体化した接着半導体基板を形成する工
程と、 前記接着半導体基板の第1半導体基板の口径を
変化させないで残すと共に第1半導体基板と第2半導体
基板とが空隙を挟んで対向する未接着の外周部が存在し
ないように、前記接着半導体基板の側壁を研削する工程
とを、具備することを特徴とするものである。
[Structure of the Invention] (Means for Solving the Problems) A method for manufacturing a semiconductor substrate (wafer) of the present invention includes a method for manufacturing a semiconductor substrate (wafer) in which mirror-polished main surfaces of first and second semiconductor substrates whose side walls are bevel-processed are connected to each other. or a step of forming a bonded semiconductor substrate in which mirror-polished principal surfaces with an oxide film attached to at least one principal surface of the substrates are brought into close contact with each other and integrated by heat treatment; and a first semiconductor substrate of the bonded semiconductor substrate. a step of grinding a side wall of the bonded semiconductor substrate so that the diameter of the bonded semiconductor substrate remains unchanged and there is no unbonded outer peripheral portion where the first semiconductor substrate and the second semiconductor substrate face each other with a gap in between. It is characterized by:

(作用) 本発明では、接着ウェーへの側壁を研削する工程におい
ては、第1ウエーへの口径は研削されないでそのまま残
すので、接着ウェーハの口径は従来のウェーハの口径と
等しい、 又従来のウェーハの口径を変化しないで、未
接着の外周部即ち第1ウエーハと第2ウエー八とが空隙
を挟んで対向する外周部が除去されるので、素子製造工
程中の外周部の欠は及び割れは大幅に軽減される。
(Function) In the present invention, in the step of grinding the side wall of the bonded wafer, the diameter of the first wafer is not ground and is left as is, so the diameter of the bonded wafer is equal to that of the conventional wafer, and the diameter of the bonded wafer is the same as that of the conventional wafer. Since the unbonded outer periphery, that is, the outer periphery where the first wafer and the second wafer face each other with a gap in between, is removed without changing the diameter of the wafer, chips and cracks in the outer periphery during the device manufacturing process are eliminated. significantly reduced.

これにより接着ウェーハの口径を小径化することなしに
未接着部のないウェーハを供給でき、チップ形成面積も
増大させることができた。
This made it possible to supply wafers with no unbonded parts without reducing the diameter of the bonded wafers, and it was also possible to increase the chip formation area.

なおウェーハの口径は第1図(a>の符号d7で示すよ
うに、ウェーハの外周径d1の最大値であり、又未接着
の外周部は、断面図で示すと、空隙を挟んで対向する面
ABC又は面AB’ C’である。
The diameter of the wafer is the maximum value of the outer circumferential diameter d1 of the wafer, as shown by the symbol d7 in Figure 1 (a>), and the unbonded outer circumferences are opposite to each other with a gap in between, as shown in the cross-sectional view. This is plane ABC or plane AB'C'.

(実施例) 次に、本発明の実施例について、図面を参照して以下説
明する。
(Example) Next, an example of the present invention will be described below with reference to the drawings.

第1図のようにベベル加工16を施し、被接着面を鏡面
研磨した第1半導体基板(以下第1ウエーハと記す)1
1を20枚準備する。 第1ウエーハの仕様は、口径1
25 lnφ、厚さ625μrg、N型、面方位(10
0)及び比抵抗ρΣ10Ω・C11である。
A first semiconductor substrate (hereinafter referred to as a first wafer) 1 which has been beveled 16 and has a mirror-polished surface to be bonded as shown in FIG.
Prepare 20 pieces of 1. The specifications of the first wafer are diameter 1
25 lnφ, thickness 625μrg, N type, plane orientation (10
0) and specific resistance ρΣ10Ω·C11.

このうち10枚は熱酸化を施し、被接着面に厚さ500
0人の酸化fyA13を形成する。 酸化膜を付けた第
1ウエーハを符号11aで表わす、 次にベベル加工を
施し、被接着面を鏡面研磨した第2半導体基板(以下第
2ウエーハと記す)12を20枚準備する。 第2ウエ
ーハの仕様は、第1ウエーハ11のそれと同じである。
Ten of these sheets were thermally oxidized to a thickness of 500 mm on the surface to be adhered.
Forms 0 oxidized fyA13. A first wafer with an oxide film attached thereto is denoted by reference numeral 11a.Next, 20 second semiconductor substrates (hereinafter referred to as second wafers) 12 are prepared, which are beveled and have mirror-polished surfaces to be bonded. The specifications of the second wafer are the same as those of the first wafer 11.

 次に従来技術と同様、第1ウエーハと第2ウエーハと
を密着し、1100℃で2時間熱処理して一体化した接
着半導体基板(以下接着ウェーハと記す)を作成する。
Next, as in the prior art, the first wafer and the second wafer are closely attached and heat-treated at 1100° C. for 2 hours to create an integrated bonded semiconductor substrate (hereinafter referred to as bonded wafer).

第1図(a)のように第1ウエーハ11と第2ウエーハ
12とからなる接着ウェーハ」を10枚、同図(b)に
示すように酸化膜13を付けた第1ウエーハllaと第
2ウエーハ12とからなる接着ウェーハ1至を10枚そ
れぞれ形成した。
As shown in FIG. 1(a), there are ten bonded wafers consisting of a first wafer 11 and a second wafer 12, and as shown in FIG. Ten bonded wafers 1 to 1 each consisting of wafer 12 were formed.

次に接着ウェーハ上A及び−15(酸化膜付)の各10
枚のうちそれぞれ5枚ずつを第2図(a)に示す砥石2
1により、同図(b)に示すように外周研削を行なった
。 符号22は砥石21の研削部で、粗さ#800を使
用する。 まず接着ウェーハ上A又は1二を真空チャッ
ク台23に固定する。 符号24はウェーハを吸着する
真空溝である。 次にチャック台23のウェーハ載置面
から砥石21の下面までの距Mhが600μmになるよ
うに砥石21の高さを調整する。 この状態で砥石21
に回転と矢印方向の送りを与え、又チャック台23にも
回転を与え、上側の第2ウエーハ12の径が117■φ
になるように外周を研削する。
Next, 10 each of A and -15 (with oxide film) on the bonded wafer.
Five of the grinding wheels 2 shown in Fig. 2(a) are
1, the outer periphery was ground as shown in FIG. 1(b). Reference numeral 22 is the grinding portion of the grindstone 21, and the roughness is #800. First, the bonded wafer top A or 12 is fixed on the vacuum chuck stand 23. Reference numeral 24 is a vacuum groove that attracts the wafer. Next, the height of the grindstone 21 is adjusted so that the distance Mh from the wafer mounting surface of the chuck table 23 to the lower surface of the grindstone 21 is 600 μm. In this state, the whetstone 21
is rotated and fed in the direction of the arrow, and the chuck table 23 is also rotated until the diameter of the upper second wafer 12 is 117mmφ.
Grind the outer periphery so that

引き続き、未接着のオリエンテーションフラット部分を
同様に研削除去する。
Subsequently, the unbonded orientation flat portion is similarly ground and removed.

この実施例における研削工程の砥石の送りは、研削取り
代が半径方向4IIIlになるようにして、未接着部分
ABCを除去する。 一般に研削取り代は、予め試行に
よって決定する。
In this embodiment, the grindstone is fed in the grinding process so that the grinding allowance becomes 4III1 in the radial direction, and the unbonded portion ABC is removed. Generally, the grinding allowance is determined in advance through trials.

同図(c)は、研削実施後の、チャック台に載置された
接着ウェーハ上Aの外周部を含む一部省略断面図である
。 又同図(d)は接着ウェーハ14の一部省略平面図
である。 両国より明らかなように研削後の接着ウェー
ハの口径は、第1ウエーハの口径が研削されないでその
まま残るので、標準規格寸法を維持できる。 又未接着
の外周部はすべて除去される。
FIG. 2C is a partially omitted cross-sectional view including the outer circumferential portion of the bonded wafer A placed on the chuck stand after the grinding has been performed. FIG. 2D is a partially omitted plan view of the bonded wafer 14. As is clear from Ryogoku, the diameter of the bonded wafer after grinding can maintain the standard size because the diameter of the first wafer remains as it is without being ground. Also, all unbonded outer peripheral parts are removed.

上述のように外周研削した接着ウェーハIA及び15の
それぞれ5枚(計10枚)と、外周研削をしない接着ウ
ェーハL1及び15のそれぞれ5枚(計10枚)とを、
ラッピング装置で接着ウェーハの厚さが725μmにな
るまでラッピングして、欠け、割れ等に対する比較試験
を行なった。 その結果、外周研削をしていないウェー
ハ上A及びににはチッピングが全数発生した。 これに
対し未接着の外周部を除去した接着ウェーハ上ま及び1
5には、チッピングが皆無であった。 酸化膜を付けた
ウェーハと付けないウェーハには差が認められなかった
5 each of bonded wafers IA and 15 (10 in total) whose outer periphery was ground as described above, and 5 each (10 in total) of bonded wafers L1 and 15 whose outer periphery was not ground,
A bonded wafer was lapped using a lapping machine until the thickness of the bonded wafer became 725 μm, and a comparative test for chipping, cracking, etc. was conducted. As a result, chipping occurred on all of the wafers A and 2 on which the outer periphery had not been ground. On the other hand, the top of the bonded wafer with the unbonded outer peripheral part removed and 1
No. 5 had no chipping. No difference was observed between wafers with and without an oxide film.

又外周研削の第2の実施例として第3図に示す形がある
。 この場合、接着面から上方に厚さtAの第2ウエー
ハ12のA部分が残されている。
A second embodiment of outer circumferential grinding is shown in FIG. In this case, a portion A of the second wafer 12 with a thickness tA remains above the bonding surface.

tAが薄いと、例えば50μを以下では、チッピングが
生ずる可能性があり、第2図に示す第1の実施例の方が
好適である。
If tA is thin, for example less than 50μ, chipping may occur, so the first embodiment shown in FIG. 2 is more suitable.

更に第3の実施例として第4図に示す形がある。Furthermore, there is a shape shown in FIG. 4 as a third embodiment.

この場合、ウェーハの直径方向の研削量は上述の実施例
と同等であるが、ウェーハの深さ(厚さ)方向の研削量
を、第1ウエーハ(厚さ to)11の口径が変化しな
い深さ、即ちt。72以上の厚さが残、る深さまで外周
部を研削している。 これにより研削時の寸法精度に関
係なく、はぼ完全に未接着部分を除去することができる
In this case, the amount of grinding in the diameter direction of the wafer is the same as in the above embodiment, but the amount of grinding in the depth (thickness) direction of the wafer is changed to a depth where the diameter of the first wafer (thickness to) 11 does not change. Sa, that is, t. The outer periphery is ground to a depth that leaves a thickness of 72 mm or more. As a result, the unbonded portion can be almost completely removed regardless of the dimensional accuracy during grinding.

[発明の効果] 第1、第2の2枚のウェーハを密着して、一体止した接
着ウェーハを形成する際、ベベル面及び面ダレにより隙
間ができ、そのなめ未接着の外周部が生じ、素子製造工
程中のウェーハの欠け、割れを誘発する原因となってい
た。 本発明では、第1ウエーハの口径を変化させない
で残すと共に、第1ウエー八と第2ウエーハとが空隙を
挟んで対向する未接着の外周部を除去するので、ウェー
ハの口径を小さくすることなしに、未接着の外周部のな
いウェーハ即ち外周部の欠け、割れ等の生じない接着ウ
ェーハを供給することが可能になった。
[Effects of the Invention] When the first and second wafers are closely attached to form a bonded wafer that is fixed together, a gap is created due to the beveled surface and the surface sag, and an unbonded outer peripheral portion is created around the gap. This caused chipping and cracking of the wafer during the device manufacturing process. In the present invention, the diameter of the first wafer is left unchanged, and the unbonded outer peripheral portion where the first wafer and the second wafer face each other with a gap in between is removed, so there is no need to reduce the diameter of the wafer. In addition, it has become possible to supply a wafer without an unbonded outer periphery, that is, a bonded wafer without chipping or cracking of the outer periphery.

これにより、125 uφのウェーハの接着では、従来
100 amφに形成していたものを、125■φのま
までペレット工程投入ができるようになり、又チップ形
成面積も前記径比で約1.4倍に増やすことができた。
As a result, when bonding wafers with a diameter of 125 μΦ, it is now possible to use the pellet process with a wafer of 125 μΦ instead of the 100 amΦ in the past, and the chip forming area has also been reduced to about 1.4 in terms of the above diameter ratio. I was able to double it.

又従来10011IIφの接着ウェーハを作成するため
には、125IIIlφのウェーハ2枚使用していたも
のが、100 mmφのウェーハ2枚で済むことになり
、材料費の低減化を図ることができた。
Moreover, in order to produce a bonded wafer of 10011 IIφ, two wafers of 125III1φ were conventionally used, but now two wafers of 100 mmφ are required, and the material cost can be reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例に使用する接着ウェーへの外周
部を含む部分断面図、第2図は本発明のウェーハ外周部
研削工程を説明する図で、同図(a)は砥石、同図(b
)は研削工程、同図(c)は研削後の接着ウェーへのそ
れぞれ部分断面図、同図(d)は研削後の接着ウェーハ
の平面図、第3図及び第4図は本発明の第2及び第3実
施例の接着ウェーへの部分断面図、第5図は本発明及び
従来の接着ウェーへの製造工程を示す断面図、第6図は
従来の接着ウェーハの外周部を含む部分断面図である。 11・・・第1半導体基板、 上ユ、14.上j・・・
接着半導体基板、 12・・・第2半導体基板、13・
・・酸化膜、 16・・・ベベル加工面、  dI、i
a・・・口径、 面ABC,面AB” C’・・・未接
着の外周面。 (a) 第 図 (b) 第 図 (a) (b)
FIG. 1 is a partial sectional view including the outer periphery of a bonded wafer used in an embodiment of the present invention, FIG. The same figure (b
) is a grinding process, (c) is a partial sectional view of the bonded wafer after grinding, (d) is a plan view of the bonded wafer after grinding, and FIGS. 3 and 4 are diagrams showing the process of the present invention. 5 is a sectional view showing the manufacturing process of the bonded wafer according to the present invention and the conventional bonded wafer, and FIG. 6 is a partial sectional view of the bonded wafer of the conventional bonded wafer including its outer periphery. It is a diagram. 11...first semiconductor substrate, upper layer, 14. Above...
adhesive semiconductor substrate, 12... second semiconductor substrate, 13.
... Oxide film, 16... Beveled surface, dI, i
a...Aperture, surface ABC, surface AB''C'...Unbonded outer peripheral surface. (a) Figure (b) Figure (a) (b)

Claims (1)

【特許請求の範囲】 1 側壁にベベル加工を施した第1及び第2の半導体基
板の鏡面研磨された主面どうし、又は鏡面研磨され且つ
少なくとも一方の前記基板主面に酸化膜を付けた主面ど
うしを密着し、熱処理して一体化した接着半導体基板を
形成する工程と、前記接着半導体基板の第1半導体基板
の口径を変化させないで残すと共に第1半導体基板と第
2半導体基板とが空隙を挟んで対向する未接着の外周部
が存在しないように、前記接着半導体基板の側壁を研削
する工程とを、 具備することを特徴とする半導体基板の製造方法。
[Scope of Claims] 1. Mirror-polished main surfaces of first and second semiconductor substrates whose side walls are beveled, or mirror-polished main surfaces with an oxide film on at least one of the substrate main surfaces. A step of forming a bonded semiconductor substrate whose surfaces are brought into close contact with each other by heat treatment, and a diameter of the first semiconductor substrate of the bonded semiconductor substrate remains unchanged, and a gap is formed between the first semiconductor substrate and the second semiconductor substrate. A method for manufacturing a semiconductor substrate, comprising the step of: grinding a side wall of the bonded semiconductor substrate so that there is no unbonded outer peripheral portion facing each other with the bonded semiconductor substrate in between.
JP9693189A 1989-04-17 1989-04-17 Manufacture of semiconductor substrate Pending JPH02273923A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9693189A JPH02273923A (en) 1989-04-17 1989-04-17 Manufacture of semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9693189A JPH02273923A (en) 1989-04-17 1989-04-17 Manufacture of semiconductor substrate

Publications (1)

Publication Number Publication Date
JPH02273923A true JPH02273923A (en) 1990-11-08

Family

ID=14178091

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9693189A Pending JPH02273923A (en) 1989-04-17 1989-04-17 Manufacture of semiconductor substrate

Country Status (1)

Country Link
JP (1) JPH02273923A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0451993A2 (en) * 1990-03-29 1991-10-16 Shin-Etsu Handotai Company Limited Method for preparing a substrate for semiconductor devices
JP2010171955A (en) * 2008-12-24 2010-08-05 Ngk Insulators Ltd Method for manufacturing composite substrate and composite substrate
JP2011181919A (en) * 2010-03-02 2011-09-15 Soitec Silicon On Insulator Technologies Process for fabricating a multilayer structure with trimming using thermo-mechanical effects
JP2020096132A (en) * 2018-12-14 2020-06-18 株式会社東京精密 Edge trimming method for bonded wafer
JP2020131409A (en) * 2019-02-25 2020-08-31 株式会社Sumco Terrace processing method for laminated wafer

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0451993A2 (en) * 1990-03-29 1991-10-16 Shin-Etsu Handotai Company Limited Method for preparing a substrate for semiconductor devices
EP0451993A3 (en) * 1990-03-29 1994-03-09 Shinetsu Handotai Kk
JP2010171955A (en) * 2008-12-24 2010-08-05 Ngk Insulators Ltd Method for manufacturing composite substrate and composite substrate
US8585847B2 (en) 2008-12-24 2013-11-19 Ngk Insulators, Ltd. Composite substrate and manufacturing method thereof
JP2011181919A (en) * 2010-03-02 2011-09-15 Soitec Silicon On Insulator Technologies Process for fabricating a multilayer structure with trimming using thermo-mechanical effects
JP2020096132A (en) * 2018-12-14 2020-06-18 株式会社東京精密 Edge trimming method for bonded wafer
JP2020131409A (en) * 2019-02-25 2020-08-31 株式会社Sumco Terrace processing method for laminated wafer

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