JPH02262329A - Semiconductor device - Google Patents

Abstract

PURPOSE:To completely eliminate the cutout of a gate wiring pattern in a transistor part, by forming a taper on a step-difference part where a gate wiring passes, in order to reduce wiring resistance, and forming no tapers on step- difference parts except ones where the gate wiring passes, in order to prevent halation from being generated at the time of exposure. CONSTITUTION:In the gate wiring 14 of a semiconductor device, a taper 15 is formed in the part where the gate wiring passes on a step-difference structure, thereby reducing the wiring resistance; the taper is not formed on the step- difference structure where the gate wiring 14 does not passes, in order to prevent halation from being generated at the time of exposure. For example, after polysilicon turning to a capacitor cell electrode 13 is formed on an LOCOS 12 formed on a silicon substrate 11, the capacitor cell electrode 13 is patterned by resist 17 only in the part where the gate wiring 14 passes, and a taper is formed on the step-difference part by isotropic etching. Next, a capacitor cell electrode 13 is patterned only in the part where the gate wiring 14 does not pass, and then anisotropic etching is performed. After that, a layer turning to the gate wiring 14 is formed and a pattern is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device, and particularly to a step structure through which a gate wiring passes.

[Conventional technology]

FIG. 5 is a plan view of a conventional semiconductor device having a step structure through which gate wiring passes, FIG. 6 is a cross-sectional view taken along line C-C shown in FIG. 5, and FIG. 7 is a cross-sectional view taken along line D shown in FIG. 8(a) to 8(d) are cross-sectional views showing the manufacturing process of the semiconductor device of FIG. 5. In the figure (IJ is a silicon substrate,
(21 is LOGO8 (Loeal Oxidation
(31 is a capacitor cell electrode, (4) is a gate wiring, (5) is a taper, (6) is a chipped pattern, (7) is a transistor part, and (8) is a resist.

Next, the structural steps and structure of the semiconductor device will be explained with reference to FIG.

First, as shown in (1), a capacitor electrode (
3) Form polysilicon.

Next, as shown in (b) (resist by photolithography process)
8), install capacitor cell electrodes (
3) Pattern.

Next, as shown in (6), the patterned areas are isotropically etched to give the entire step group a taper angle.

Furthermore, as shown in (d), a layer that will become the gate wiring (4) is then formed and subjected to a photolithography process to form a pattern.

[Problem to be solved by the invention]

Conventional semiconductor devices are configured as described above, so
All the gap structures through which the gate wiring (4) passes are tapered etched, and in the exposure process when forming the gate wiring (4), the gate wiring +4) is formed by halation in the areas where the gate wiring (4) does not pass. If a part of the resist (8) is exposed unnecessarily, the formed pattern descendants will have a defect (6) in the pattern shown in FIG.
There is a problem in that transistor characteristics change due to lack of 4).

This invention was made to solve the above-mentioned problems, and aims to obtain a structure free from halation from a stepped portion through which the gate wiring (4) does not pass.

[Means to solve the problem]

In the semiconductor device according to the present invention, the stepped portion through which the gate wiring passes is tapered, and the other portions where the gate wiring does not pass are tapered to form a narrow structure.

[Effect]

In the structure of the semiconductor device according to the present invention, the step portion where the gate wire passes is tapered to lower the interconnect resistance, and the portion other than the step portion where the gate wire passes is tapered during the etching process to prevent halation. Eliminate chipping of the gate wiring pattern.

〔Example〕

An embodiment of the present invention will be shown below with reference to FIGS. 1 to 4. 1 is a plan view of the semiconductor device, FIG. 2 is a sectional view taken along line A-A in FIG. 1, FIG. 3 is a sectional view taken along line BB in FIG. 1, and FIGS. 2 is a cross-sectional view showing a manufacturing process of the semiconductor device of FIG. 1. FIG.

In the figure, wholesale is silicon substrate, ■ is LOCOS Se2
is the capacitor cell electrode, α4 is the gate wiring, (to) is the taper etch, Gl is the transistor part, and α is the resist.

Next, the manufacturing process and structure of the semiconductor device will be described with reference to FIG.

First, as shown in (a), polysilicon that will become the capacitor cell electrode 4 is formed on the LOCOS Q2 formed at a temperature of α° C. of the silicon substrate.

Next, as shown in (b) E, capacitor cell electrode openings are patterned only at the locations where the gate wiring .alpha.- passes through using resin .sigma. force using a photolithography process.

Next, as shown in (4), the above pattern is isotropically etched to taper the stepped portions.

Next, as shown in (d), the capacitor cell electrode side is patterned by a photolithography process only in areas where the gate wiring α4 does not pass.

Next, anisotropic etching is performed on the pattern obtained in (d) as shown in (ell), and the capacitor cell electrode υ in the stepped portion is not tapered.

Furthermore, as shown in (f), a layer that will become the gate wiring α4 is then formed, and a photolithography process is performed to form a pattern.

〔Effect of the invention〕

As described above, according to the present invention, the step portion where the gate wire passes is tapered to lower the wire resistance and increase the access speed of the semiconductor device, and the gate wire is chipped due to halation at the location where the transistor portion is formed. This has the effect of making it possible to obtain a high quality semiconductor device without causing any change in transistor characteristics.

[Brief explanation of drawings]

1 to 4 relate to one embodiment of the present invention, in which FIG. 1 is a plan view of a semiconductor device, and FIG.
3 is a sectional view taken along line B-H in FIG. 1, FIGS. 4(a) to (f) are sectional views showing the manufacturing process of the semiconductor device in FIG. 1, and FIG. 5 is a sectional view taken along line B-H in FIG. FIG. 6 is a cross-sectional view at C and C in FIG. 5, FIG. 7 is a cross-sectional view at line D in FIG. 5, and FIGS. 8 (a) to (d)
6 is a cross-sectional view showing the manufacturing process of the semiconductor device shown in FIG. 5. FIG. In the figure, αB is a silicon substrate, (2) is a LOCOS
1 (to) is the capacitor cell electrode, α is the gate wiring,
(to) is a taper etch, OQ is a transistor part, a7
) is a resist. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] A semiconductor device characterized in that, in a gate wiring of a semiconductor device, a portion where the gate wiring passes over a stepped structure is tapered to lower the wiring resistance, and a stepped structure where the gate wiring does not pass is not tapered to prevent halation that occurs during exposure. Device.