JPH02211428A - Active matrix substrate for liquid crystal display device - Google Patents
Active matrix substrate for liquid crystal display deviceInfo
- Publication number
- JPH02211428A JPH02211428A JP1034022A JP3402289A JPH02211428A JP H02211428 A JPH02211428 A JP H02211428A JP 1034022 A JP1034022 A JP 1034022A JP 3402289 A JP3402289 A JP 3402289A JP H02211428 A JPH02211428 A JP H02211428A
- Authority
- JP
- Japan
- Prior art keywords
- liquid crystal
- substrate
- crystal display
- film
- active matrix
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 56
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 42
- 239000011159 matrix material Substances 0.000 title claims abstract description 42
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- 239000010408 film Substances 0.000 claims description 40
- 239000010409 thin film Substances 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 13
- 239000000463 material Substances 0.000 abstract description 10
- 239000011521 glass Substances 0.000 abstract description 9
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 8
- 239000011248 coating agent Substances 0.000 abstract description 5
- 238000000576 coating method Methods 0.000 abstract description 5
- 239000000377 silicon dioxide Substances 0.000 abstract description 5
- 230000007547 defect Effects 0.000 abstract description 2
- 238000004528 spin coating Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 15
- 238000000034 method Methods 0.000 description 14
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 11
- 229910052782 aluminium Inorganic materials 0.000 description 11
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 11
- 239000012790 adhesive layer Substances 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 239000010453 quartz Substances 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 206010034972 Photosensitivity reaction Diseases 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000036211 photosensitivity Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229920003051 synthetic elastomer Polymers 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Formation Of Insulating Films (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、薄膜半導体を用いたアクティブ素子を有する
液晶表示装置用アクティブマトリクス基板に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an active matrix substrate for a liquid crystal display device having an active element using a thin film semiconductor.
近年、薄膜トランジスタ(TPT)や薄膜ダイオード(
TFD)等の薄膜半導体を用いたアクティブ素子を各画
素毎に設け、高画質化を狙ったアクティブマトリクス液
晶表示装置の開発が活発である。この様な液晶表示装置
は、液晶を2枚の基板ではさんだ構造で、一方は前記ア
クティブ素子をマトリクス状に形成したアクティブマト
リクス基板、他方は例えばガラス基板上全面に透明電極
を形成してなる対向基板から構成されている。In recent years, thin film transistors (TPT) and thin film diodes (
2. Description of the Related Art Active matrix liquid crystal display devices, in which each pixel is provided with an active element using a thin film semiconductor such as TFD, are being actively developed with the aim of achieving high image quality. Such a liquid crystal display device has a structure in which a liquid crystal is sandwiched between two substrates, one of which is an active matrix substrate in which the active elements are formed in a matrix, and the other is an opposing substrate made of, for example, a glass substrate with transparent electrodes formed on the entire surface. It consists of a substrate.
液晶としては通常コントラストの高くとれるTN型が多
く用いられるためアクティブ素子形成用基板もガラス等
の透明基板を利用した透過型液晶表示装置が開発されて
いる。Since TN type liquid crystals, which usually have high contrast, are often used as liquid crystals, transmission type liquid crystal display devices have been developed in which transparent substrates such as glass are used as substrates for forming active elements.
アクティブ素子のチャネル領域となる薄膜半導体材料と
しては、主にアモルファスシリコン(a−St)やポリ
シリコン(p −Si)が使用されている。a−5iは
、低温で膜形成が可能な事から安価なガラス基板を使用
でき、最近の多くのボケット型液晶テレビ等に応用され
ている。p−Siは、a−3iより移動度が大きく、ま
た単結晶シリコン。Amorphous silicon (a-St) and polysilicon (p-Si) are mainly used as thin film semiconductor materials that form channel regions of active elements. Since a-5i can be formed into a film at a low temperature, an inexpensive glass substrate can be used, and it has been applied to many recent pocket-type liquid crystal televisions. P-Si has higher mobility than a-3i and is single crystal silicon.
a−Stに比べ極端に光感度が鈍く、つまり光に対し非
常に安定な、高性能アクティブ素子を実現できる。この
ため次期高精細液晶表示装置等への適用が期待されてい
るが、まだ安価なガラス基板が使える程の低温で、簡便
に大面積形成が可能な技術が熟成していないのが現状で
ある。Compared to a-St, it has extremely low photosensitivity, that is, it is possible to realize a high-performance active element that is extremely stable against light. For this reason, it is expected that it will be applied to the next generation of high-definition liquid crystal display devices, but the current state is that the technology that can easily form large areas at low enough temperatures to use inexpensive glass substrates has not yet matured. .
この様なp−5iを用いたアクティブ素子を形成する方
法として通常のシリコンIC’?LSIプロセス中の高
温p−Siプロセスを利用する方法がある。ただし基板
材料としては、この様な高温プロセスに耐える石英や単
結晶シリコン基板が必要である。この中で後者の単結晶
シリコン基板を用い光入射が無くかつ高速、高性能が要
求される周辺駆動回路を単結晶シリコントランジスタ回
路で構成し、光入射のあるアクティブ素子部をp −5
tTFTで形成しアクティブマトリクス基板とする方法
が、・例えば特願昭61−246653 rアクティブ
マトリクス液晶表示装置およびその製造方法」の明細書
中に述べられている。この発明によれば、第2図に示す
様に例えば透明ガラス基板201上にエポキシまたはポ
リイミド等の透明な接着層202によりアクティブ素子
が形成されたデバイス層を接着し、アクティブマトリク
ス基板を構成している。このデバイス層の詳細は以下の
通りである。第2図には示されていないが、単結晶シリ
コン基板上に、通常のシリコンIC。Is there a way to form an active element using such p-5i using a normal silicon IC'? There is a method that utilizes a high-temperature p-Si process during the LSI process. However, the substrate material must be quartz or single crystal silicon that can withstand such high-temperature processes. Among these, the latter single-crystal silicon substrate is used, and the peripheral drive circuit, which requires no light incidence and high speed and high performance, is constructed with a single-crystal silicon transistor circuit, and the active element portion with light incidence is p -5.
A method of forming an active matrix substrate using TFTs is described, for example, in the specification of Japanese Patent Application No. 61-246653 "Active Matrix Liquid Crystal Display Device and Manufacturing Method Therefor". According to this invention, as shown in FIG. 2, a device layer in which active elements are formed is adhered to a transparent glass substrate 201 using a transparent adhesive layer 202 such as epoxy or polyimide to form an active matrix substrate. There is. Details of this device layer are as follows. Although not shown in FIG. 2, a normal silicon IC is mounted on a single crystal silicon substrate.
LSIプロセスを用い例えば二酸化シリコンからなる熱
酸化絶縁膜203を形成し、この絶縁膜上に島状のp−
Si半導体層204をマトリクス状に配列形成した後、
ゲート絶縁膜205.ゲート電極206を順次p−St
半導体層204上にパターン形成する0次に、例えばイ
オン注入等によりソース、ドレイン領域をp−5i半導
体層204に形成した後、配線分離用絶縁膜207を形
成し、この配線分離用絶縁膜207にコンタクトホール
をあけ、例えばアルミ配線で信号配線用のドレイン配線
208.ソースコンタクト209をパターン形成し、T
PTとする0表示電極210は例えばITOからなる透
明電極で、ソースコンタクト209と接続されて配線分
離用絶縁膜上に形成される。この場合、特にソースコン
タクトは無くてかまわないが、例えば厚さ500人程度
の表示電極210だけでは例えば通常深さが3000Å
以上のコンタクトホールを通じてソース領域との接続の
信頼性が無くなる。最後に、この単結晶シリコン基板を
裏面から選択ポリッシングにより熱酸化絶縁膜203ま
で研磨し、薄膜のデバイス層としている0周辺駆動回路
まで含めたアクティブマトリクス基板の模式的平面図を
第3図に示す0例えばゲート電極206を水平配線、ド
レイン配線208を垂直配線とするマトリクス配線とp
−5iTFT303および表示電極210で各々分離さ
れた画素とから形成されたアクティブマトリクス素子部
の周囲に、周辺駆動回路である例えば単結晶シリコント
ランジスタで構成された走査駆動回路301.信号駆動
回路302が設置されている0以上の様にして形成され
たアクティブマトリクス基板上に液晶配向膜211を少
なくとも表示電極210上全面に形成し、例えばITO
からなる透明性対向電極212が透明ガラス基板201
全面に形成された対向基板とで、例えばTN型液晶21
3をはさむ事により液晶表示装置が完成される。A thermally oxidized insulating film 203 made of, for example, silicon dioxide is formed using an LSI process, and island-shaped p-
After forming the Si semiconductor layers 204 in a matrix,
Gate insulating film 205. The gate electrode 206 is sequentially made of p-St
After forming a pattern on the semiconductor layer 204, source and drain regions are formed in the p-5i semiconductor layer 204 by, for example, ion implantation, and then an insulating film 207 for wiring isolation is formed. Drill a contact hole in the drain wiring 208. for signal wiring using aluminum wiring, for example. Pattern source contact 209 and T
The 0 display electrode 210, which is PT, is a transparent electrode made of, for example, ITO, and is connected to the source contact 209 and formed on the wiring isolation insulating film. In this case, there may be no need for a source contact, but if the display electrode 210 is only about 500 thick, the depth is usually 3000 Å.
The reliability of the connection with the source region through the above contact hole is lost. Finally, this single-crystal silicon substrate was selectively polished from the back side down to the thermal oxide insulating film 203, and FIG. 3 shows a schematic plan view of the active matrix substrate including the zero peripheral drive circuit, which is used as a thin-film device layer. 0 For example, matrix wiring in which the gate electrode 206 is a horizontal wiring and the drain wiring 208 is a vertical wiring and p
-5i TFT 303 and pixels separated from each other by display electrodes 210. Around the active matrix element section formed from pixels separated by the display electrodes 210, a scanning drive circuit 301. A liquid crystal alignment film 211 is formed on the entire surface of at least the display electrodes 210 on an active matrix substrate formed in the manner shown in FIG.
A transparent counter electrode 212 consisting of a transparent glass substrate 201
For example, the TN type liquid crystal 21
By sandwiching 3, the liquid crystal display device is completed.
ところで液晶配向膜211を形成する方法として何種類
か考えられるがその中で最近では、製造が非常に容易な
ラビーグ法が用いられている。これは、例えばポリイミ
ド等の有機膜を印刷等でパターン形成した後、液晶分子
が一方向に配列する様に、布等の表面の植毛で有機膜を
摩擦する方法である。この方法により、第2図に示した
様にアクティブマトリクス基板上に形成した有機膜をラ
ビングし液晶配向膜211とする場合、アルミ配線等の
段差により全域にわたり均一な配向が得られない、特に
、段差部つまり表示電極210の周辺部で顕著となる。By the way, there are several methods that can be considered for forming the liquid crystal alignment film 211, but recently, the Lavigre method, which is very easy to manufacture, has been used. This is a method in which, for example, an organic film such as polyimide is patterned by printing or the like, and then the organic film is rubbed with flocking on the surface of cloth or the like so that liquid crystal molecules are aligned in one direction. When using this method to form a liquid crystal alignment film 211 by rubbing an organic film formed on an active matrix substrate as shown in FIG. 2, uniform alignment cannot be obtained over the entire area due to steps such as aluminum wiring. This is noticeable in the step portion, that is, in the periphery of the display electrode 210.
例えばアルミ配線の膜厚による段差は、通常1μm以上
となり顕著な場合、ラビングされるのはほとんどアルミ
配線上でラビングしたい表示電極210上は無配向とな
ってしまう、また表示電極210上を良好な配向膜とす
るため摩擦力を強くしたりすると、TPTに損傷を・与
えかねない0以上の様に従来例においては、液晶配向膜
211形成のラビング時において配向膜不良をおこした
り、またTPTに損傷を与えたりする歩留りの悪い構造
であった。以上の課題は、石英基板上に直接p−5iT
FTを形成したアクティブマトリクス基板においても同
様である。For example, if the level difference due to the film thickness of aluminum wiring is usually 1 μm or more and is significant, most of the rubbing will be done on the aluminum wiring, and the display electrode 210 to be rubbed will be non-oriented. If the frictional force is increased to form an alignment film, it may damage the TPT. It was a structure with poor yield that could cause damage. The above problem is to directly produce p-5iT on a quartz substrate.
The same applies to an active matrix substrate on which FTs are formed.
本発明の目的は、この様な従来の欠点を取り除き、高歩
留りで高性能な液晶表示装置用アクティブマトリクス基
板を提供する事にある。An object of the present invention is to eliminate such conventional drawbacks and provide a high-yield, high-performance active matrix substrate for a liquid crystal display device.
上記目的を達成するためには、本発明の液晶表示装置用
アクティブマトリクス基板は、絶縁性基板上に、マトリ
クス状に形成された薄膜半導体アクティブ素子、該アク
ティブ素子に1対1に接続された表示電極、該表示電極
に前記アクティブ素子を通じ信号を制御および印加する
ためのマトリクス配線を少なくとも構成された液晶表示
装置用アクティブマトリクス基板において、該液晶表示
装置用アクティブマトリクス基板全面に透明の絶縁性平
坦化膜を設置したものである。In order to achieve the above object, the active matrix substrate for a liquid crystal display device of the present invention includes thin film semiconductor active elements formed in a matrix on an insulating substrate, and display devices connected one-to-one to the active elements. In an active matrix substrate for a liquid crystal display device comprising at least an electrode and a matrix wiring for controlling and applying a signal to the display electrode through the active element, the active matrix substrate for a liquid crystal display device is flattened with a transparent insulating material on the entire surface. A membrane is installed.
以下、本発明の一実施例について図面を参照して説明す
る。第1図は本発明の一実施例を説明するための液晶表
示装置用アクティブマトリクス基板の断面図である。第
1図において、例えば保持基板として安価な透明ガラス
基板101上に接着層102を介してマトリクス状に配
列されたp−5ET F Tからなるアクティブ素子を
有する薄膜のデバイス層が設置されている構造は前に述
べた従来例と同様である。また接着層102も従来例同
様例えばエポキシ系あるいはポリイミド系の透明性接着
材である。An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of an active matrix substrate for a liquid crystal display device for explaining one embodiment of the present invention. In FIG. 1, for example, a thin film device layer having active elements made of p-5ET F T arranged in a matrix is installed on an inexpensive transparent glass substrate 101 as a holding substrate via an adhesive layer 102. is the same as the conventional example described above. Further, the adhesive layer 102 is also made of a transparent adhesive material such as epoxy or polyimide, as in the conventional example.
以下、デバイス層について詳細に説明する。図示されて
いないが単結晶シリコン基板上に熱酸化法やCVD法等
により例えば二酸化シリコンの絶縁膜103を形成する
。厚さは特に限定は無いが後で述べるデバイス層を形成
するための研磨精度から1000Å以上が望ましい。こ
の絶縁膜103上に例えばCVD法によりp−5i半導
体層104を蒸着し、マトリクス状の各画素毎のTPT
チャネル領域となる様に島状にパターン化する。続いて
p−8t半導体層104上に例えば熱酸化による二酸化
シリコンからなるゲート絶縁膜105、p−Stゲート
電極106を通常のシリコンICのMOSFETと同等
なプロセスで順次形成、パターン化する。p−Stゲー
ト電極106はそのままマトリクス配線の例えば水平配
線を形成し、p −SiT F Tの開閉制御を行なう
。p −9i半導体層104にソース、ドレイン領域を
形成する例えばイオン注入を行なった後、ゲート電極1
06と後のアルミ配線を分離する配線分離用絶縁膜10
7を形成し、ソース、トレイン領域に相当する部分にコ
ンタクトホールをあける。絶縁膜107の上に厚さ1μ
m程度のアルミニウム膜全面蒸着後、信号印加配線とな
るドレイン配線108およびソースコンタクト109に
パターン化する。その後、ソースコンタクト109のア
ルミニウムと接続された例えばITOからなる透明の表
示電極110を形成し各画素毎にパターン分離する。こ
の時表示電極110は、ドレイン配線108、ソースコ
ンタクト109アルミ蒸着前に形成しておいてもかまわ
ない。またソースコンタクト109のアルミニウムは特
に必要としない事は従来例に述べた通りである0次に、
少なくともマトリクス状に形成された画素全面に、例え
ば二酸化シリコン系塗布膜材料(商品名:東京応化製○
CD)あるいはアリカル系樹脂被膜材料(商品名二日本
合成ゴム製JSS−451)等を1μm〜2μm程度ス
ピンコードで塗布し焼成する事により平坦化膜111を
形成する。最後に、従来例で述べた様に選択ポリッシン
グを用い、絶縁膜103が露出するまで単結晶シリコン
基板を裏面より研磨し、デバイス層が完成する。平坦化
膜111は、単結晶シリコン基板研磨後のアクティブマ
トリクス基板上に形成する方法でもがまわない
以上の様にして形成された本実施例のアクティブマトリ
クス基板においては、平坦化膜によって、マトリクス配
線等による1μm程度の段差が例えば0.1〜0.2μ
m程度に軽減される。またマトリクス配線等による段差
はフォトリソグラフィにより急峻であるが、平坦化膜1
11ではなめらかな段差の構造となっている。The device layer will be described in detail below. Although not shown, an insulating film 103 of silicon dioxide, for example, is formed on a single crystal silicon substrate by a thermal oxidation method, a CVD method, or the like. The thickness is not particularly limited, but is preferably 1000 Å or more from the viewpoint of polishing accuracy for forming a device layer, which will be described later. A p-5i semiconductor layer 104 is deposited on this insulating film 103 by, for example, the CVD method, and a TPT layer is formed for each pixel in a matrix.
Patterned into an island shape to form a channel region. Subsequently, a gate insulating film 105 made of, for example, silicon dioxide by thermal oxidation and a p-St gate electrode 106 are sequentially formed and patterned on the p-8t semiconductor layer 104 by a process similar to that of a MOSFET of a normal silicon IC. The p-St gate electrode 106 forms a matrix wiring, for example, a horizontal wiring, and controls opening and closing of the p-SiT F T. After performing, for example, ion implantation to form source and drain regions in the p-9i semiconductor layer 104, the gate electrode 1
Insulating film 10 for wiring separation that separates 06 and subsequent aluminum wiring
A contact hole is formed in a portion corresponding to the source and train regions. 1μ thick on the insulating film 107
After depositing an aluminum film of about m thickness over the entire surface, a drain wiring 108 and a source contact 109, which will serve as signal application wiring, are patterned. Thereafter, a transparent display electrode 110 made of, for example, ITO is formed and connected to the aluminum of the source contact 109, and pattern separation is performed for each pixel. At this time, the display electrode 110 may be formed before the drain wiring 108 and the source contact 109 are deposited with aluminum. Also, as stated in the conventional example, aluminum for the source contact 109 is not particularly required.
At least on the entire surface of the pixels formed in a matrix, for example, a silicon dioxide-based coating film material (trade name: Tokyo Ohka Co., Ltd.
A flattening film 111 is formed by applying a coating material such as CD) or an alical resin coating material (trade name JSS-451 manufactured by Nippon Synthetic Rubber Co., Ltd.) to a thickness of about 1 μm to 2 μm using a spin cord and baking it. Finally, as described in the conventional example, selective polishing is used to polish the single crystal silicon substrate from the back side until the insulating film 103 is exposed, thereby completing the device layer. The planarizing film 111 can be formed on the active matrix substrate after polishing the single crystal silicon substrate. For example, a level difference of about 1 μm due to
It is reduced to about m. In addition, the level difference due to matrix wiring etc. is steep due to photolithography, but the flattening film 1
11 has a smooth stepped structure.
液晶表示装置としては、第1図に示す様に液晶配向膜1
12形成後、図示されているが、対向電極を有する対向
基板とで液晶をはさんだ構造となる。従って本実施例の
アクティブマトリクス基板では、表示電極110と対向
電極間に印加された信号電圧は、液晶と平坦化膜111
に分圧され実質的に液晶にかけたい信号電圧が減少する
。この分圧比は、液晶と平坦化膜111の直列に接続さ
れた容量に依存する。従って液晶の容量を小さく平坦化
膜111のそれを大きくすればよい、容量は膜厚と誘電
率に依存するが、膜厚は、コントラストや平坦化性でそ
れ程大きくは変えられない。As a liquid crystal display device, as shown in FIG. 1, a liquid crystal alignment film 1 is used.
After forming 12, as shown in the figure, a structure is formed in which the liquid crystal is sandwiched between a counter substrate having a counter electrode. Therefore, in the active matrix substrate of this embodiment, the signal voltage applied between the display electrode 110 and the counter electrode is applied between the liquid crystal and the flattening film 110.
The signal voltage to be applied to the liquid crystal substantially decreases. This partial pressure ratio depends on the capacitance connected in series between the liquid crystal and the flattening film 111. Therefore, it is sufficient to reduce the capacitance of the liquid crystal and increase that of the flattening film 111. Although the capacitance depends on the film thickness and dielectric constant, the film thickness cannot be changed so much depending on contrast and flattening properties.
誘電率は、本実施例で述べたSiO□系、アクリル系共
3〜5で、液晶とほぼ同程度であり、例えば膜厚比、液
晶:平坦化膜=5:1で液晶の方に80%以上信号電圧
が印加される。このため特に問題は生じないが、できれ
ば平坦化膜111材料の誘電率は、高いものを選ぶ方が
好ましい。こういった材料には、例えば強誘電性のPL
ZT系塗布材料(商品名:高純度化学製アルコラード)
等が有効である。The dielectric constant is 3 to 5 for both the SiO % or more signal voltage is applied. Therefore, no particular problem arises, but it is preferable to select a material with a high dielectric constant for the planarization film 111 if possible. Such materials include, for example, ferroelectric PL.
ZT-based coating material (product name: Kojundo Kagaku Alcolade)
etc. are valid.
尚、本実施例では、周辺駆動回路を単結晶シリコン基板
上に構成するのは第3図に示す従来例と同等で、平坦化
プロセスは共用も可能である。また、本実施例では、単
結晶シリコン基板上にp−5iT F Tを形成するア
クティブマトリクス基板について説明したが、従来例で
述べた石英基板上に直接p−5iTFTを形成する場合
でもさらにa −3iT F TやTFD等のアクティ
ブマトリクス基板においても同等である。In this embodiment, the peripheral drive circuit is constructed on a single-crystal silicon substrate in the same manner as in the conventional example shown in FIG. 3, and the planarization process can also be shared. Further, in this embodiment, an active matrix substrate in which p-5i TFTs are formed on a single crystal silicon substrate has been described, but even in the case where p-5i TFTs are directly formed on a quartz substrate as described in the conventional example, the a- The same applies to active matrix substrates such as 3iTFT and TFD.
以上説明した様に、本発明の液晶表示装置用アクティブ
マトリクス基板によれば、平坦化膜11のスピンコード
という簡単なプロセスにより、アルミ配線等による急峻
な高い段差をなめらかで平坦な表面とすることができ、
ラビングにより表示電極部上においてもムラの無い良好
な液晶配向膜112が形成され、良好な液晶表示を可能
とする。また、摩擦力の強いラビングは不必要であり、
ラビング時におけるアルミ配線やTFT部へのダメージ
が少なく欠陥の無い高歩留りな構造となっている。As explained above, according to the active matrix substrate for a liquid crystal display device of the present invention, a steep and high step caused by aluminum wiring etc. can be made into a smooth and flat surface by a simple process of spin-coding the flattening film 11. is possible,
By rubbing, a good liquid crystal alignment film 112 with no unevenness is formed even on the display electrode portion, thereby enabling good liquid crystal display. Also, rubbing with strong frictional force is unnecessary,
It has a high-yield structure with no defects and little damage to the aluminum wiring and TFT parts during rubbing.
ト絶縁膜、106,206・・・ゲート電極、107゜
207・・・配線分離用絶縁膜、108,208・・・
ドレイン配線、109,209・・・ソースコンタクト
、110,210・・・表示電極、111・・・平坦化
膜、112.211・・・液晶配向膜、212・・・対
向電極、213・・・液晶、301・・・走査駆動回路
、302・・・信号駆動回路。Insulating film, 106,206...Gate electrode, 107°207...Insulating film for wiring separation, 108,208...
Drain wiring, 109,209... Source contact, 110,210... Display electrode, 111... Flattening film, 112.211... Liquid crystal alignment film, 212... Counter electrode, 213... Liquid crystal, 301...Scanning drive circuit, 302...Signal drive circuit.
第1図は本発明の一実施例を説明するための液晶表示装
置用アクティブマトリクス基板の断面図、第2図は従来
例を説明するためのアクティブマトリクス液晶表示装置
の断面図、第3図は本発明および従来例を説明するため
の液晶表示装置用アクティブマトリクス基板の模式的平
面図である。
101.201・・・ガラス基板、102.202・・
・接着層、103,203・・・絶縁膜、104゜20
4・・・p−Si半導体層、105,205・・・ゲー
代理人 弁理士 内 原 晋FIG. 1 is a cross-sectional view of an active matrix substrate for a liquid crystal display device for explaining an embodiment of the present invention, FIG. 2 is a cross-sectional view of an active matrix liquid crystal display device for explaining a conventional example, and FIG. 1 is a schematic plan view of an active matrix substrate for a liquid crystal display device for explaining the present invention and a conventional example. 101.201...Glass substrate, 102.202...
・Adhesive layer, 103,203...Insulating film, 104°20
4... p-Si semiconductor layer, 105,205... Game agent patent attorney Susumu Uchihara
Claims (1)
アクティブ素子、該アクティブ素子に1対1に接続され
た表示電極、該表示電極に前記アクティブ素子を通じ信
号を制御および印加するためのマトリクス配線を少なく
とも備えた液晶表示装置用アクティブマトリクス基板に
おいて、該液晶表示装置用アクティブマトリクス基板全
面に透明の絶縁性平坦化膜を設置した事を特徴とする液
晶表示装置用アクティブマトリクス基板。Thin film semiconductor active elements formed in a matrix on an insulating substrate, display electrodes connected one-to-one to the active elements, and matrix wiring for controlling and applying signals to the display electrodes through the active elements. 1. An active matrix substrate for a liquid crystal display device comprising at least an active matrix substrate for a liquid crystal display device, characterized in that a transparent insulating flattening film is provided on the entire surface of the active matrix substrate for a liquid crystal display device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1034022A JPH02211428A (en) | 1989-02-13 | 1989-02-13 | Active matrix substrate for liquid crystal display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1034022A JPH02211428A (en) | 1989-02-13 | 1989-02-13 | Active matrix substrate for liquid crystal display device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02211428A true JPH02211428A (en) | 1990-08-22 |
Family
ID=12402751
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1034022A Pending JPH02211428A (en) | 1989-02-13 | 1989-02-13 | Active matrix substrate for liquid crystal display device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02211428A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04317373A (en) * | 1991-04-16 | 1992-11-09 | Semiconductor Energy Lab Co Ltd | Close adhesion type image sensor |
US6693301B2 (en) | 1991-10-16 | 2004-02-17 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method of driving and manufacturing the same |
US7071910B1 (en) | 1991-10-16 | 2006-07-04 | Semiconductor Energy Laboratory Co., Ltd. | Electrooptical device and method of driving and manufacturing the same |
US7116302B2 (en) | 1991-10-16 | 2006-10-03 | Semiconductor Energy Laboratory Co., Ltd. | Process of operating active matrix display device having thin film transistors |
US7253440B1 (en) | 1991-10-16 | 2007-08-07 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having at least first and second thin film transistors |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61156025A (en) * | 1984-12-27 | 1986-07-15 | Fujitsu Ltd | Display device |
JPS63104026A (en) * | 1986-10-21 | 1988-05-09 | Nec Corp | Manufacture of liquid crystal display device |
-
1989
- 1989-02-13 JP JP1034022A patent/JPH02211428A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61156025A (en) * | 1984-12-27 | 1986-07-15 | Fujitsu Ltd | Display device |
JPS63104026A (en) * | 1986-10-21 | 1988-05-09 | Nec Corp | Manufacture of liquid crystal display device |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04317373A (en) * | 1991-04-16 | 1992-11-09 | Semiconductor Energy Lab Co Ltd | Close adhesion type image sensor |
US6693301B2 (en) | 1991-10-16 | 2004-02-17 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method of driving and manufacturing the same |
US6759680B1 (en) | 1991-10-16 | 2004-07-06 | Semiconductor Energy Laboratory Co., Ltd. | Display device having thin film transistors |
US7071910B1 (en) | 1991-10-16 | 2006-07-04 | Semiconductor Energy Laboratory Co., Ltd. | Electrooptical device and method of driving and manufacturing the same |
US7116302B2 (en) | 1991-10-16 | 2006-10-03 | Semiconductor Energy Laboratory Co., Ltd. | Process of operating active matrix display device having thin film transistors |
US7253440B1 (en) | 1991-10-16 | 2007-08-07 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having at least first and second thin film transistors |
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