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JPH02205319A - Manufacture of semiconductor element - Google Patents

Manufacture of semiconductor element

Info

Publication number
JPH02205319A
JPH02205319A JP2554889A JP2554889A JPH02205319A JP H02205319 A JPH02205319 A JP H02205319A JP 2554889 A JP2554889 A JP 2554889A JP 2554889 A JP2554889 A JP 2554889A JP H02205319 A JPH02205319 A JP H02205319A
Authority
JP
Japan
Prior art keywords
insulating film
masks
mask material
semiconductor element
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2554889A
Other languages
Japanese (ja)
Inventor
Mitsutoshi Hasegawa
光利 長谷川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2554889A priority Critical patent/JPH02205319A/en
Publication of JPH02205319A publication Critical patent/JPH02205319A/en
Pending legal-status Critical Current

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  • Drying Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)
  • Semiconductor Lasers (AREA)

Abstract

PURPOSE:To obtain a semiconductor element, a process of which is facilitated and which has excellent reproducibility, by forming an insulating film to a base material as a mask material is left as it is not removed and taking off, the insulating film in the top section of a protrusion together with the mask material. CONSTITUTION:Striped photo-masks 17 are shaped to the upper section of a semiconductor laser wafer, sections up to the upper section of approximately 0.5mum+ or -0.2mum of an active layer 14 are etched through the photo-masks 17, and polyimide LB(Langmuir-Blodgett) films 18 are formed in 200Angstrom as the masks 17 are left as they are and an insulating film is shaped. The films 18 of the top sections of ridges are lifted off by an etchant dissolving only the masks 17, and used as current injection regions. Cr-Au ohmic electrodes are formed through a vacuum deposition method as upper electrodes 102, a GaAs substrate 11 is lapped to thickness of 100mum, and an Au-Ge electrode is evaporated as an N-type ohmic electrode 103. Accordingly, a process can be simplified, and a semiconductor element having excellent reproducibility is acquired.

Description

【発明の詳細な説明】 (産業上の利用分野〕 本発明は光情報伝送装置に用いられる半導体素子等微小
突起部を有する半導体素子の製造方法に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor element having minute protrusions, such as a semiconductor element used in an optical information transmission device.

〔従来の技術〕[Conventional technology]

従来、微小突起部を有する半導体素子の突起部の頂上の
絶縁膜のみを除去するプロセス工程は、マスク合わせを
伴ったアライメント法が行われていた。
Conventionally, an alignment method involving mask alignment has been used to remove only the insulating film on the top of the protrusion of a semiconductor element having minute protrusions.

また、エッチバック法が用いられていた。これを第2図
で説明する。まず突起部のピッチが3μmで、突起部の
幅が1μm、深さ2μmになるよう半導体ウェハー基材
をマスク材301を通してエツチングする(第2図b)
Also, an etch-back method was used. This will be explained with reference to FIG. First, the semiconductor wafer substrate is etched through the mask material 301 so that the pitch of the protrusions is 3 μm, the width of the protrusions is 1 μm, and the depth is 2 μm (Figure 2b).
.

次に、マスク材をマスク材リムーバーで除去し、洗浄す
る(第2図C)。
Next, the mask material is removed with a mask material remover and washed (FIG. 2C).

続いてプラズマ・CVD法等により窒化シリコン膜30
2等の絶縁膜を形成する(第2図d)。
Next, a silicon nitride film 30 is formed using a plasma/CVD method or the like.
A second insulating film is formed (FIG. 2d).

更に、フォトマスク材303を平坦にスピンナーコート
する(第2e)。
Furthermore, the photomask material 303 is flattened by spinner coating (2nd e).

続いて、ドライエツチング法により突起部の頂き部のみ
が露出するまでマスク材を全体的にエツチングしく第2
図f)、さらに突起部の頂き部の絶縁膜をエツチングし
く第2図g)、最後に、突起部以外の残りのマスク材を
除去する(第2図h)。
Next, the entire mask material is etched using a dry etching method until only the tops of the protrusions are exposed.
Then, the insulating film on the top of the projection is etched (FIG. 2g), and finally, the remaining mask material other than the projection is removed (FIG. 2H).

〔発明が解決しようとしている課題〕[Problem that the invention is trying to solve]

しかしながら、上記従来例では、微小突起部を有する半
導体素子において突起部の頂き部のみの絶縁膜を除去す
る工程において、次のような欠点があった。
However, the conventional example described above has the following drawbacks in the process of removing the insulating film only from the top of the protrusion in a semiconductor element having minute protrusions.

まず、アライメント法においては、 1)突起幅がほぼ3μm以下の場合においてウェハーと
マスクのアライメントの精度をほぼ0.5μm以下にす
る必要があるが、これを実行することは困難であり、時
間がかかるので歩留りが悪い、 2)また、突起部の頂上のみでなく、頂き部の少し下ま
で絶縁膜が除去されやすく、制御がむずかしい、 3)ウェハーをマスクとコンタクトさせるため、クエへ
−のカケ、ワレが生じやすく、ウェハーにダメージを与
え、半導体素子の寿命を短くする等、再現性が悪い、 4)更に、突起部のピッチが3μm以下の場合にはアラ
イメントの粒度上、適用不可能である、 等がある。
First, in the alignment method, 1) When the protrusion width is approximately 3 μm or less, the accuracy of alignment between the wafer and the mask must be approximately 0.5 μm or less, but this is difficult and time-consuming. 2) In addition, the insulating film is likely to be removed not only from the top of the protrusion but also slightly below the top, making control difficult. 3) Since the wafer is brought into contact with the mask, the chipping into the square is difficult. , easy to crack, damage the wafer, shorten the life of the semiconductor element, and have poor reproducibility. 4) Furthermore, if the pitch of the protrusions is 3 μm or less, it cannot be applied due to the grain size of the alignment. There are, etc.

エッチバック法においては、 1)突起部の頂き部だけでなく、その少し側面の絶縁膜
も除去されてしまい制御性が悪い、2)プロセス工程が
長くスルーブツトが悪い、等がある。
The etch-back method has problems such as 1) poor controllability since not only the top of the protrusion but also the insulating film slightly on the sides are removed, and 2) process steps are long and throughput is poor.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は、微小突起部を有する半導体素子を製造するに
おいて、プロセスが容易で再現性が良い半導体素子の製
造方法を提供することを目的とし、ウェハープロセスの
歩留りを向上させ、かつ製造した半導体の長寿命化を実
現するものである。
An object of the present invention is to provide a method for manufacturing a semiconductor device with an easy process and good reproducibility in manufacturing a semiconductor device having microprotrusions, and to improve the yield of the wafer process and improve the yield of the manufactured semiconductor. This realizes a long life.

本発明は、基材上に所望のパターン状にマスク材を設け
て基材をエツチングし、該マスク材を除去しないまま基
材に絶縁膜を形成し、マスク材だけを除去するエツチン
グ法により突起の頂き部の絶縁膜をマスク材とともに除
去することを特徴とする微小突起部を有する半導体素子
の製造方法であり、とくには絶M膜を形成するときの温
度が、マスク材が発泡しない温度であることを特徴とす
る上記製造方法である。
In the present invention, a mask material is provided in a desired pattern on a base material, the base material is etched, an insulating film is formed on the base material without removing the mask material, and the protrusions are removed by an etching method in which only the mask material is removed. A method for manufacturing a semiconductor element having a microscopic protrusion, characterized in that the insulating film on the top of the mask is removed together with the mask material, and in particular, the temperature at which the absolute M film is formed is at a temperature at which the mask material does not foam. The above manufacturing method is characterized in that:

(実施例〕 以下、本発明の実施例について図面を参照しながら説明
する。
(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

第1図は本発明の実施例を示し、これに基づきリッジ型
半導体レーザの製造プロセスを詳細に述べる。
FIG. 1 shows an embodiment of the present invention, and based on this, the manufacturing process of a ridge type semiconductor laser will be described in detail.

まず、n型GaAs基板+1上に分子線エピタキシ法に
よって順次、バッファ層12としてn型GaAsを1μ
m、クラッド層13としてn型A1.、 、Gao。a
Asを2μm形成した。活性層14としてはノンドープ
GaAsを100人、Alo、 2Gao、 aAsを
30人交互にそれぞれ4回くり返し最後にGaAsを1
00人積層し、多重量子井戸構造のものを形成した。次
にクラッド層15としてP型A1.、  Gao、  
Asを1.5μm、キャップ層16としてGaAsを0
.5μm形成した。
First, 1 μm of n-type GaAs was sequentially deposited as a buffer layer 12 on an n-type GaAs substrate +1 by molecular beam epitaxy.
m, and n-type A1.m as the cladding layer 13. , , Gao. a
As was formed to a thickness of 2 μm. For the active layer 14, 100 people used non-doped GaAs, 30 people used Alo, 2Gao, and aAs, each of which was repeated 4 times, and finally, 1 layer of GaAs was used.
00 layers were stacked to form a multiple quantum well structure. Next, as the cladding layer 15, P type A1. , Gao,
As the cap layer 16, 1.5 μm of As and 0 μm of GaAs.
.. A thickness of 5 μm was formed.

次に、上記半導体レーザーウェハー上方にストライブ状
のフォトマスク17を設け(第1図a)、それを通して
活性層の手前約0.5μm±0.2μmまで、塩素ガス
雰囲気での反応性イオンビームエツチングによりエツチ
ングした(第1図b)。
Next, a striped photomask 17 is provided above the semiconductor laser wafer (FIG. 1a), and a reactive ion beam in a chlorine gas atmosphere is applied through the photomask 17 to about 0.5 μm±0.2 μm in front of the active layer. It was etched by etching (Fig. 1b).

次にフォトマスク17を残したまま、ポリイミドLB(
ラングミュア−プロジェット)@18を200人成膜し
たく第1図C)。続いてフォトマスク17だけを溶かす
エツチング液でリッジ頂上部のポリイミドLB膜18を
リフトオフし、電流注入域とした(1g1図d)。
Next, leaving the photomask 17, polyimide LB (
Langmuir-Prodgett) @ 18 (Fig. 1 C). Subsequently, the polyimide LB film 18 at the top of the ridge was lifted off using an etching solution that dissolved only the photomask 17, thereby forming a current injection region (1g, 1d).

更に上部電極102として、Cr−Auオーミック用電
極を真空蒸着法で形成し、GaAs基板をラッピングで
100μmの厚さまで削った後、n型用オーミック用電
極 103としてへu−Ge電極を蒸着したく第1図e
)。
Furthermore, a Cr-Au ohmic electrode is formed as the upper electrode 102 by vacuum evaporation, and the GaAs substrate is polished to a thickness of 100 μm, and then a u-Ge electrode is deposited thereon as the n-type ohmic electrode 103. Figure 1 e
).

続いてP型、N型の電極のオーミックコンタクトをとる
ための熱処理を行なった後、共振面をへき開によって形
成し、スクライブで分離し、電極はワイアーボンディン
グにより取り出した。ここで、キャビティー長は300
μmである。さらに共撮画にEB蒸着法により、Al2
O,−5iO2系の高反射膜、低反射膜をそれぞれコー
ティングした。
Subsequently, after heat treatment was performed to establish ohmic contact between the P-type and N-type electrodes, a resonant surface was formed by cleavage, separated by a scribe, and the electrodes were taken out by wire bonding. Here, the cavity length is 300
It is μm. Furthermore, Al2
A high reflection film and a low reflection film based on O, -5iO2 were coated.

これにより、しきい値電流が15mA以下、非点収差が
4μm以下、遠視野像の水平、方向のビーム拡がり角度
が15度を越える特性をもちかつ長寿命(室温で200
0時間以上レーザー発振可能)の半導体レーザーを得た
As a result, the threshold current is 15 mA or less, astigmatism is 4 μm or less, the horizontal and directional beam divergence angle of the far field image exceeds 15 degrees, and the product has a long life (up to 200 mA at room temperature).
A semiconductor laser capable of laser oscillation for more than 0 hours was obtained.

繰り返し同様な工程により半導体レーザーを形成したと
ころ、同様な特性をもつ半導体レーザーが再現性良く得
られた。
When semiconductor lasers were repeatedly formed using the same process, semiconductor lasers with similar characteristics were obtained with good reproducibility.

なお、上記共振面形成はへき開によっても良いし、共振
面の片面または両面にウェットエツチングプロセスまた
はドライエツチングプロセス等によって作製してもよい
Note that the resonant surface may be formed by cleaving, or may be formed on one or both sides of the resonant surface by a wet etching process, a dry etching process, or the like.

本発明は分布帰還型や分布反射型のレーザの製造にも有
効に適用できる。
The present invention can also be effectively applied to manufacturing distributed feedback type and distributed reflection type lasers.

また、本発明は、微小突起部を有するリッジ型半導体レ
ーザ素子の製造ばかりでなく、同様な突起部をもつ導波
路、光スィッチ、光変調器などの半導体素子の製造にも
適用できる。
Furthermore, the present invention can be applied not only to the manufacture of ridge-type semiconductor laser devices having minute protrusions, but also to the manufacture of semiconductor devices such as waveguides, optical switches, and optical modulators having similar protrusions.

更に、上記フォトマスクは多層構造でも良いし、リフト
オフは、ドライプロセス(UVアッシャ−等)によって
も同様の効果が得られる。
Furthermore, the above-mentioned photomask may have a multilayer structure, and the same effect can be obtained by lift-off using a dry process (UV asher, etc.).

また、上記LBI摸の膜厚は、〜数千人でもリフトオフ
ができる範囲なら有効である。
Further, the film thickness of the LBI sample described above is effective as long as it can be lifted off by up to several thousand people.

更に、絶縁膜はLB膜以外の真空蒸着法で形成した高分
子膜でも良いし、スピンコードした膜でもよい。
Furthermore, the insulating film may be a polymer film other than the LB film formed by vacuum evaporation, or a spin-coated film.

本発明において使用しつる絶縁膜材料は、次のものが挙
げられる。
Examples of the insulating film material used in the present invention include the following.

[1]ジアセチレン化合物 C11,−+CH2′)−1nCミC−G =C−+C
t12Th  XO<n、 jlj<20 但しn+1>10 Xは親木基で一般的には−GODHが用いられるが−叶
、−GONI(。等も使用できる。
[1] Diacetylene compound C11,-+CH2')-1nCmiC-G =C-+C
t12Th XO<n, jlj<20 where n+1>10

[11]付加重合体 1)ポリアクリル酸 6)酢酸ビニルコポリマー 2)ポリアクリル酸エステル 3)アクリル酸コポリマー [II[]縮合重合体 1)ポリアミド 4)アクリル酸エステルコポリマー 5)ポリビニルアセテート 2)ポリカーボネート [IV]開環重合体 1)ポリエチレンオキシド ここでR1は水面上で単分子膜を形成しやすくするため
に導入された長鎖アルキル基で、その炭素数nは5≦n
≦30が好適である。またR5は短鎖アルキル基であり
、炭素数nは1≦n≦4が好適である。重合度mは10
0≦m≦5000が好適である。
[11] Addition polymer 1) Polyacrylic acid 6) Vinyl acetate copolymer 2) Polyacrylic ester 3) Acrylic acid copolymer [II [] Condensation polymer 1) Polyamide 4) Acrylic ester copolymer 5) Polyvinyl acetate 2) Polycarbonate [IV] Ring-opening polymer 1) Polyethylene oxide Here, R1 is a long-chain alkyl group introduced to facilitate the formation of a monomolecular film on the water surface, and its carbon number n is 5≦n.
≦30 is suitable. Further, R5 is a short-chain alkyl group, and the number of carbon atoms n is preferably 1≦n≦4. The degree of polymerization m is 10
It is preferable that 0≦m≦5000.

尚、上記以外でもLB法に適している有機材料、有機高
分子材料であれば、本発明に好適なのは言うまでもない
It goes without saying that any organic material or organic polymer material other than those mentioned above is also suitable for the present invention as long as it is suitable for the LB method.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、微小突起部のピ
ッチ幅がアライメントできない程せまい場合にも、制御
良く微小突起部の頂上の絶縁膜のみを除去でき、また、
プロセスも簡略化できる。
As explained above, according to the present invention, even when the pitch width of the micro-projections is so narrow that alignment cannot be achieved, only the insulating film at the top of the micro-projections can be removed with good control;
The process can also be simplified.

このため、半導体装置を再現性良く製造することが可能
になり、歩留りが向上し、光情報伝送装置に極めて有効
な半導体素子が提供可能になる。
Therefore, it becomes possible to manufacture semiconductor devices with good reproducibility, the yield is improved, and it becomes possible to provide semiconductor elements that are extremely effective for optical information transmission devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の半導体製造方法の工程を示す図、第2
図は従来の半導体製造方法の工程を示す図である。
FIG. 1 is a diagram showing the steps of the semiconductor manufacturing method of the present invention, and FIG.
The figure is a diagram showing the steps of a conventional semiconductor manufacturing method.

Claims (1)

【特許請求の範囲】 1)微小突起部を有する半導体素子の製造方法において
、基材上に所望のパターン状にマスク材を設けて基材を
エッチングし、該マスク材を除去しないまま基材に絶縁
膜を形成し、マスク材だけを除去するエッチング法によ
り突起部の頂き部の絶縁膜をマスク材とともに除去する
ことを特徴とする半導体素子の製造方法。 2)絶縁膜を形成するときの温度が、マスク材が発泡し
ない温度であることを特徴とする請求項1に記載の製造
方法。
[Claims] 1) In a method of manufacturing a semiconductor device having minute protrusions, a mask material is provided in a desired pattern on a base material, the base material is etched, and the mask material is etched onto the base material without being removed. 1. A method of manufacturing a semiconductor device, comprising forming an insulating film and removing the insulating film at the top of the protrusion along with the mask material by an etching method that removes only the mask material. 2) The manufacturing method according to claim 1, wherein the temperature at which the insulating film is formed is a temperature at which the mask material does not foam.
JP2554889A 1989-02-03 1989-02-03 Manufacture of semiconductor element Pending JPH02205319A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2554889A JPH02205319A (en) 1989-02-03 1989-02-03 Manufacture of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2554889A JPH02205319A (en) 1989-02-03 1989-02-03 Manufacture of semiconductor element

Publications (1)

Publication Number Publication Date
JPH02205319A true JPH02205319A (en) 1990-08-15

Family

ID=12169022

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2554889A Pending JPH02205319A (en) 1989-02-03 1989-02-03 Manufacture of semiconductor element

Country Status (1)

Country Link
JP (1) JPH02205319A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7585688B2 (en) 2007-03-29 2009-09-08 Mitsubishi Electric Corporation Method for manufacturing semiconductor optical device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7585688B2 (en) 2007-03-29 2009-09-08 Mitsubishi Electric Corporation Method for manufacturing semiconductor optical device

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