JPH021926A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH021926A JPH021926A JP14402488A JP14402488A JPH021926A JP H021926 A JPH021926 A JP H021926A JP 14402488 A JP14402488 A JP 14402488A JP 14402488 A JP14402488 A JP 14402488A JP H021926 A JPH021926 A JP H021926A
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxidation resistant
- substrate
- oxidation
- aluminum layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 34
- 230000003647 oxidation Effects 0.000 claims abstract description 27
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 27
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 13
- 238000000059 patterning Methods 0.000 claims abstract 2
- 238000004544 sputter deposition Methods 0.000 claims description 13
- 238000000137 annealing Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims 2
- 239000010410 layer Substances 0.000 abstract description 67
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 12
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 12
- 239000011229 interlayer Substances 0.000 abstract description 9
- 238000000576 coating method Methods 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 239000011248 coating agent Substances 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 abstract description 4
- 230000002950 deficient Effects 0.000 abstract 2
- 239000004020 conductor Substances 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 8
- 238000010438 heat treatment Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- 229910052801 chlorine Inorganic materials 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は半導体装置の製造方法に関し、特に半導体装置
表面に形成する導電配線層の形成方法の改良に関する。DETAILED DESCRIPTION OF THE INVENTION (A) Industrial Application Field The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improvement in a method for forming a conductive wiring layer formed on the surface of a semiconductor device.
（ロ）従来の技術
半導体集積回路は多数の能動素子や受動素子が半導体基
板に設けられ、これらは導電配線層で接続される。この
導電配線層としてはアルミニウム層が良く用いられてお
り、このアルミニウム層は層間絶縁膜を介在させて高集
積化のため多層構造に形成されている。(B) Conventional Technology A semiconductor integrated circuit has a large number of active elements and passive elements provided on a semiconductor substrate, and these are connected by conductive wiring layers. An aluminum layer is often used as this conductive wiring layer, and this aluminum layer is formed into a multilayer structure with an interlayer insulating film interposed therebetween for high integration.
斯る多層構造のアルミニウム配線層は第２図Ａ乃至第２
図りに示す如く形成されている。The aluminum wiring layers of such a multilayer structure are shown in FIGS.
It is formed as shown in the figure.
先ず第２図Ａに示す如く、半導体基板（２１）上にアル
ミニウム層（２２）をスパッタ法で被着し、更に窒化チ
タン膜（２３）を被着している。半導体基板（２１）に
は所望の拡散領域（２４）が形成され、基板（２１）表
面はシリコン酸化膜（２５）で被覆され、拡散領域（２
４）上のシリコン酸化膜（２５）には選択エツチングに
よりコンタクト孔＜２６）が形成されている。このシリ
コン酸化膜（２５）上にはスパッタ法で約１μｍのアル
ミニウム層（２２）が全面に被着きれ、コンタクト孔（
２６）を介して拡散領域（２４）と接触している。First, as shown in FIG. 2A, an aluminum layer (22) is deposited on a semiconductor substrate (21) by sputtering, and a titanium nitride film (23) is further deposited on the semiconductor substrate (21). A desired diffusion region (24) is formed in the semiconductor substrate (21), and the surface of the substrate (21) is covered with a silicon oxide film (25).
4) A contact hole <26) is formed in the upper silicon oxide film (25) by selective etching. On this silicon oxide film (25), an aluminum layer (22) of about 1 μm is completely deposited by sputtering, and the contact hole (
26) to the diffusion region (24).
アルミニウム層（２２）上にはスパッタ法により窒化チ
タン膜（ｒｉＮ）（２３）を約２５００人の享さに被着
している。なおアルミニウム層（２２）をスパッタする
際に基板（２１）表面にダメージを生じてしまう。On the aluminum layer (22), a titanium nitride film (riN) (23) is deposited by about 2,500 coats by sputtering. Note that when sputtering the aluminum layer (22), damage is caused to the surface of the substrate (21).
次に第２図Ｂに示す如く、アルミニウム層（２２）およ
び窒化チタン膜（２３）をパターンニングして第１の配
線層（２７）を形成している。本工程では図示しないが
ホトレジスト膜をマスクとして塩素系反応ガスを用いて
窒化チタン膜（２３）およびアルミニウム層（２２）を
選択的にドライエツチングしてパターンニングし第１の
配線層（２７）を形成し、ホトレジスト膜を除去する。Next, as shown in FIG. 2B, the aluminum layer (22) and the titanium nitride film (23) are patterned to form a first wiring layer (27). In this step, although not shown, the titanium nitride film (23) and the aluminum layer (22) are selectively dry-etched and patterned using a chlorine-based reactive gas using a photoresist film as a mask to form the first wiring layer (27). and remove the photoresist film.
従って第１の配線層（２７）上のみを窒化チタン膜（２
３）のみで被覆し、第１の配線層（２７）のない基板（
２１）表面はシリコン酸化膜（２５）を露出している。Therefore, only the first wiring layer (27) is coated with the titanium nitride film (27).
3) without the first wiring layer (27) (
21) The silicon oxide film (25) is exposed on the surface.
更に第２図Ｃに示す如く、基板（２１）をアニールして
いる０本工程では加熱炉内に基板（２１）を配置し、Ｈ
，ガス１０％、Ｎ、ガス９０％の雰囲気中で４５０’Ｃ
で３０分間の加熱処理を行う、この加熱処理で■、ガス
が基板（２１）表面まで供給され、スパッタによるダメ
ージを除去する。また本工程では同時に第１の配線層（
２７）と拡散領域（２４）のオーミックコンタクトも形
成している。なお第１の配線層（２７）下ではアルミニ
ウム層（２２〉に含有されたＨ、ガスで同様にダメージ
を除去できる。なお本工程ではアルミニウム層（２２）
の表面を硬い窒化チタン膜（２３）で被覆しているので
、アルミニウム層（２２）表面が固定されてヒロックと
呼ばれる突起の形成を抑えている。Furthermore, as shown in FIG. 2C, in the zero step where the substrate (21) is annealed, the substrate (21) is placed in a heating furnace
, 450'C in an atmosphere of 10% gas, N, and 90% gas.
During this heat treatment, gas is supplied to the surface of the substrate (21) to remove damage caused by sputtering. Also, in this process, the first wiring layer (
27) and the diffusion region (24) are also formed. Note that damage can be similarly removed under the first wiring layer (27) using H and gas contained in the aluminum layer (22).In this step, the aluminum layer (22)
Since the surface of the aluminum layer (22) is coated with a hard titanium nitride film (23), the surface of the aluminum layer (22) is fixed and the formation of protrusions called hillocks is suppressed.
更に第２図りに示す如く、層間絶縁膜（２８）を全面に
付着した後、第２の配線層（２９）を形成している。層
間絶縁膜（２８）としてはポリイミド樹脂を用い、所望
の第１の配線層（２７）上にコンタクト孔（３０）を形
成した後アルミニウム層を全面に被着してパターンニン
グし第２の配線層（２９）を形成している。Further, as shown in the second diagram, after an interlayer insulating film (28) is deposited on the entire surface, a second wiring layer (29) is formed. Polyimide resin is used as the interlayer insulating film (28), and after forming a contact hole (30) on the desired first wiring layer (27), an aluminum layer is deposited on the entire surface and patterned to form the second wiring. A layer (29) is formed.
（ハ）発明が解決しようとする課題
しかしながら斯る方法では、アルミニウム層（２２）で
形成された第１の配線層（２７）の側面は露出されてお
り、アニール処理中にこの側面にアルミニウムとシリコ
ン酸化膜の熱膨張係数の違いに起因するヒロックと呼ば
れる０、５〜２μｍの高さの半球状の突起（３１）を生
ずる問題点があった。この突起（３１）は層間絶縁膜（
２８）を薄くし、第２の配線層（２９）との絶縁不良を
発生する問題点を有していた。(c) Problems to be Solved by the Invention However, in such a method, the side surface of the first wiring layer (27) formed of the aluminum layer (22) is exposed, and during the annealing process, the side surface is exposed to aluminum. There was a problem in that hemispherical protrusions (31) with a height of 0.5 to 2 μm, called hillocks, were formed due to the difference in thermal expansion coefficient of the silicon oxide film. This protrusion (31) is connected to the interlayer insulating film (
28) is made thinner, resulting in poor insulation with the second wiring layer (29).
（ニ）課題を解決するための手段
本発明は斯る問題点に鑑みてなされ、第１の配線層の側
面にも耐酸化被膜を付着することにより、従来の問題点
を解決した半導体装置・の製造方法を提供するものであ
る。(d) Means for Solving the Problems The present invention has been made in view of these problems, and is a semiconductor device which solves the conventional problems by attaching an oxidation-resistant film also to the side surface of the first wiring layer. The present invention provides a method for manufacturing.
（＊）作用
本発明に依れば、第１の配線層（７）の側面にも第２耐
酸化被膜（８）を付着することにより、アニール処理中
に第１の配線層（７）を第１および第２耐酸化被膜（３
）（８＞で完全に被覆しているので、第１の配線層（７
）の側面にもヒロックと呼ばれる突起は形成されない。(*) Effect According to the present invention, the second oxidation-resistant film (8) is also attached to the side surface of the first wiring layer (7), so that the first wiring layer (7) is protected during the annealing process. First and second oxidation-resistant coatings (3
) (8>), so the first wiring layer (7
), no protrusions called hillocks are formed on the sides.
（へ）実施例
本発明に依る一実施例を第１図Ａ乃至第１図Ｅを参照し
て詳述する。(F) Embodiment An embodiment according to the present invention will be described in detail with reference to FIGS. 1A to 1E.
本発明では第１図Ａに示す如く、半導体基板（１）上に
アルミニウム層（２）をスパッタ法で被着し、更に第１
耐酸化被膜（３）を被着している。半導体基板（１）に
は所望の拡散領域（４）が形成され、基板（１）表面は
シリコン酸化膜（５）で被覆され、拡散領域（４）上の
シリコン酸化膜（５）には選択エツチングによりコンタ
クト孔（６）が形成きれている。In the present invention, as shown in FIG. 1A, an aluminum layer (2) is deposited on a semiconductor substrate (1) by sputtering, and a first
An oxidation-resistant coating (3) is applied. A desired diffusion region (4) is formed on the semiconductor substrate (1), the surface of the substrate (1) is covered with a silicon oxide film (5), and the silicon oxide film (5) on the diffusion region (4) is coated with a selected material. A contact hole (6) has been completely formed by etching.
このシリコン酸化膜（５）上にはスパッタ法で約１μｍ
のアルミニウム層（２〉が全面に被着され、フンタクト
孔（６）を介して拡散領域（４）と接触している。アル
ミニウム層（２）上にはスパッタ法により窒化チタン膜
（ＩｉＮ）（３）を約２５００人の厚さに被着している
。なおアルミニウム層（２）をスパッタする際に基板（
１）表面にダメージを生じてしまう。On this silicon oxide film (5), about 1 μm thick is deposited by sputtering.
An aluminum layer (2) is deposited on the entire surface and is in contact with the diffusion region (4) through the contact hole (6).A titanium nitride (IiN) film (IiN) is deposited on the aluminum layer (2) by sputtering. 3) is deposited to a thickness of approximately 2,500 mm.It should be noted that when sputtering the aluminum layer (2), the substrate (
1) Damage will occur to the surface.
次に第１図Ｂに示す如く、アルミニウムＭ（２）および
第１耐酸化被膜（３）をパターンニングして第１の配線
Ｍ（７）を形成している。本工程では図示しないがホト
レジスト膜をマスクとして塩素系反応ガスを用いて窒化
チタン膜（３）およびアルミニウム層（２）を選択的に
ドライエツチングしてパターンニングし第１の配線層（
７）を形成し、ホトレジスト膜を除去する。従って第１
の配線Ｊｌ＜７）上のみを窒化チタン膜（３）のみで被
覆し、第１の配線層（７）のない基板（１）表面はシリ
コン酸化膜（５）を露出している。Next, as shown in FIG. 1B, the aluminum M(2) and the first oxidation-resistant film (3) are patterned to form the first wiring M(7). In this step, although not shown, the titanium nitride film (3) and the aluminum layer (2) are selectively dry-etched and patterned using a chlorine-based reactive gas using a photoresist film as a mask to form the first wiring layer (
7) is formed and the photoresist film is removed. Therefore, the first
Only the titanium nitride film (3) covers only the wiring Jl<7), and the silicon oxide film (5) is exposed on the surface of the substrate (1) without the first wiring layer (7).
更に第１図Ｃに示す如く、基板（１）全面に第２耐酸化
被膜（８）を被潰し、全面を異方性エツチングして第１
の配線層（７）の側面を被覆する第２耐酸化被膜（８）
を残す。本工程は本発明の特徴とするものである。基板
（１）全面に窒化チタン膜（ＴｉＮ）の第２耐酸化被膜
（８）をスパッタにより約５００人の厚みに被着する。Furthermore, as shown in FIG.
a second oxidation-resistant film (8) covering the side surface of the wiring layer (7);
leave. This step is a feature of the present invention. A second oxidation-resistant film (8) of titanium nitride film (TiN) is deposited on the entire surface of the substrate (1) by sputtering to a thickness of approximately 500 mm.
その後オーバーエツチング気味に全面を異方性エツチン
グして、第１の配線層（７〉の側面にのみ第２耐酸化被
膜（８）を残す、この結果、第１の配線層（７）は上面
を第１耐酸化被膜（３）で、側面を第２耐酸化被膜（８
）で被覆され、他は基板（１）上のシリコン酸化膜（５
）が露出される。After that, the entire surface is anisotropically etched with a slight overetching, leaving the second oxidation-resistant film (8) only on the side surfaces of the first wiring layer (7). As a result, the first wiring layer (7) is etched on the upper surface. with the first oxidation-resistant coating (3), and the side surface with the second oxidation-resistant coating (8).
), and the others are silicon oxide films (5) on the substrate (1).
) is exposed.
更に第１図りに示す如く、基板（１）をアニールしてい
る。本工程では加熱炉内に基板（１）を配置し、Ｈよガ
ス１０％、Ｎ、ガス９０％の雰囲気中で４５０°Ｃで３
０分間の加熱処理を行う。この加熱処理でＨ，ガスが基
板（１）表面まで供給され、スパッタによるダメージを
除去する。また本工程では同時に第１の配線層（７）と
拡散領域（４）のオーミックコンタクトも形成している
。なお第１の配線層（７）下ではアルミニウム層（２）
に含有されたＨ。Further, as shown in the first diagram, the substrate (1) is annealed. In this step, the substrate (1) is placed in a heating furnace and heated at 450°C in an atmosphere of 10% H gas and 90% N gas.
Heat treatment is performed for 0 minutes. During this heat treatment, H and gas are supplied to the surface of the substrate (1) to remove damage caused by sputtering. Furthermore, in this step, ohmic contact between the first wiring layer (7) and the diffusion region (4) is also formed at the same time. Note that the aluminum layer (2) is below the first wiring layer (7).
H contained in
ガスで同様にダメージを除去できる。なお本工程ではア
ルミニウム層（２）の表面および側面を第１および第２
の窒化チタン膜（３）（８）で被覆しているので、アル
ミニウム層（２）が固定されてヒロックと呼ばれる突起
の形成を抑えている。Gas can also remove damage. In this step, the surface and side surfaces of the aluminum layer (2) are
Since the aluminum layer (2) is coated with the titanium nitride films (3) and (8), the aluminum layer (2) is fixed and the formation of protrusions called hillocks is suppressed.
更に第１図Ｅに示す如く、層間絶縁膜（９〉を全面に付
着した後、第２の配線層（１０）を形成している０層間
絶縁膜（９）としてはポリイミド樹脂を用い、所望の第
１の配線Ｍ（７）上にコンタクト孔（１１）を形成した
後アルミニウム層を全面に被着してパターンニングし第
２の配線層（１０）を形成している。Furthermore, as shown in FIG. 1E, after the interlayer insulating film (9) is deposited on the entire surface, a polyimide resin is used as the interlayer insulating film (9) forming the second wiring layer (10), and a desired layer is formed. After forming a contact hole (11) on the first wiring M (7), an aluminum layer is deposited on the entire surface and patterned to form a second wiring layer (10).
（ト）発明の効果
本発明に依れば、第１および第２窒化チタン膜（３）（
８）で第１の配線層（７）の上面および側面を被覆して
アニール工程を行えるので、スパッタによるダメージの
除去とヒロックと呼ばれる突起の発生の抑制を同時に行
える利点を有する。(g) Effects of the invention According to the invention, the first and second titanium nitride films (3) (
Since the annealing process can be performed by covering the top and side surfaces of the first wiring layer (7) in step 8), it has the advantage of simultaneously removing damage caused by sputtering and suppressing the formation of protrusions called hillocks.
また第２窒化チタン膜（８）はマスク工程なしで第１の
配線層（７）の側面を被覆できるので、極めて簡便な方
法で形成できる利点を有する。Furthermore, since the second titanium nitride film (8) can cover the side surfaces of the first wiring layer (7) without a mask process, it has the advantage that it can be formed by an extremely simple method.
更に本発明に依れば、ヒロックと呼ばれる突起が発生し
ないので容易に居間絶縁膜（９）の絶縁不良のない多層
配線構造を実現できる利点を有する。Further, according to the present invention, since no protrusions called hillocks are generated, there is an advantage that a multilayer wiring structure without insulation defects in the living room insulating film (9) can be easily realized.
第１図Ａ乃至第１図Ｅは本発明に依る半導体装置の製造
方法を説明する断面図、第２図Ａ乃至第２図りは従来の
多層配線の形成方法を説明する断面図である。
（１）は半導体基板、
（３）は第１耐酸化被膜、
はシリコン酸化膜、
は第２耐酸化被膜、
は第２の配線層である。
（２）はアルミニウム層、
（４）は拡散領域、 （５）
（７〉は第１の配線層、 （８）
（９）は層間絶縁膜、 （１０）1A to 1E are cross-sectional views for explaining a method of manufacturing a semiconductor device according to the present invention, and FIGS. 2A to 2E are cross-sectional views for explaining a conventional method for forming a multilayer wiring. (1) is a semiconductor substrate, (3) is a first oxidation-resistant film, is a silicon oxide film, is a second oxidation-resistant film, and is a second wiring layer. (2) is aluminum layer, (4) is diffusion region, (5) (7> is first wiring layer, (8) (9) is interlayer insulating film, (10)
Claims (2)
に前記アルミニウム層を第１耐酸化被膜で被覆する工程
と、 前記アルミニウム層および第１耐酸化被膜をパターンニ
ングして配線層を形成する工程と、前記基板上を第２耐
酸化被膜で被着し、更に前記第２耐酸化被膜を異方性全
面エッチングして前記配線層の側面を第２耐酸化被膜で
被覆する工程と、 前記基板をアニールする工程とを具備することを特徴と
する半導体装置の製造方法。(1) Depositing an aluminum layer on a substrate by sputtering, further covering the aluminum layer with a first oxidation-resistant film, and patterning the aluminum layer and the first oxidation-resistant film to form a wiring layer. a step of depositing a second oxidation-resistant film on the substrate, and further anisotropically etching the second oxidation-resistant film to cover the side surfaces of the wiring layer with the second oxidation-resistant film; 1. A method for manufacturing a semiconductor device, comprising the step of annealing a substrate.
（ＴｉＮ）膜を用いたことを特徴とする請求項１記載の
半導体装置の製造方法。(2) The method of manufacturing a semiconductor device according to claim 1, wherein a titanium nitride (TiN) film is used as the first and second oxidation-resistant films.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14402488A JPH021926A (en) | 1988-06-10 | 1988-06-10 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14402488A JPH021926A (en) | 1988-06-10 | 1988-06-10 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH021926A true JPH021926A (en) | 1990-01-08 |
Family
ID=15352554
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14402488A Pending JPH021926A (en) | 1988-06-10 | 1988-06-10 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH021926A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62160740A (en) * | 1986-01-10 | 1987-07-16 | Fujitsu Ltd | Semiconductor device |
| JPS6373646A (en) * | 1986-09-17 | 1988-04-04 | Toshiba Corp | Semiconductor device |
| JPS63289838A (en) * | 1987-05-20 | 1988-11-28 | Nec Corp | Semiconductor device |
-
1988
- 1988-06-10 JP JP14402488A patent/JPH021926A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62160740A (en) * | 1986-01-10 | 1987-07-16 | Fujitsu Ltd | Semiconductor device |
| JPS6373646A (en) * | 1986-09-17 | 1988-04-04 | Toshiba Corp | Semiconductor device |
| JPS63289838A (en) * | 1987-05-20 | 1988-11-28 | Nec Corp | Semiconductor device |
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