JPH02191377A - Variable capacitance diode element - Google Patents
Variable capacitance diode elementInfo
- Publication number
- JPH02191377A JPH02191377A JP1088689A JP1088689A JPH02191377A JP H02191377 A JPH02191377 A JP H02191377A JP 1088689 A JP1088689 A JP 1088689A JP 1088689 A JP1088689 A JP 1088689A JP H02191377 A JPH02191377 A JP H02191377A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- layer
- variable capacitance
- diffusion layer
- diode element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 41
- 238000009792 diffusion process Methods 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 230000002093 peripheral effect Effects 0.000 claims abstract 2
- 229920006395 saturated elastomer Polymers 0.000 abstract description 7
- 230000002542 deteriorative effect Effects 0.000 abstract 1
- 239000012535 impurity Substances 0.000 description 13
- 238000005468 ion implantation Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000011084 recovery Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は、可変容量ダイオード素子に関するものであり
、可変容量ダイオード素子の容量−電圧特性の飽和傾向
を改善すると共に、高周波直列抵抗R5を低減し、且つ
、性能指数Qを向上させるものである。Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a variable capacitance diode element, and improves the saturation tendency of the capacitance-voltage characteristic of the variable capacitance diode element, and reduces high frequency series resistance R5. Moreover, the figure of merit Q is improved.
一般に、可変容量ダイオード素子は、プレーナ構造で製
造されるものが多い。以下、第3図に基づき従来の可変
容量ダイオード素子について説明する。Generally, many variable capacitance diode elements are manufactured with a planar structure. Hereinafter, a conventional variable capacitance diode element will be explained based on FIG.
第3図に於いて、N型の低抵抗の半導体基板1に気相成
長法によって、N型で半導体基板1より高比抵抗の例え
ば1Ωcm前後の比抵抗のエピタキシャル層4を厚さ4
〜5μm程度に形成して半導体基体を形成し、このエピ
タキシャルN4の主表面に熱酸化処理を施して約1〜2
μmの熱酸化膜2(Si0g膜)を形成する。その後、
エツチング工程によって開口部を設けてイオン注入によ
り、N型の不純物元素を加速電圧が130KeVであっ
て、ドーズ量が(2〜3 ) X 10 ”am−”の
条件にて開口部を通してエピタキシャル層4内に打ち込
む、尚、イオン注入工程では、100〜3000人の酸
化膜を通して不純物元素を打ち込んでもよい0次に、イ
オン注入によって生じた格子欠陥回復とキャリア回復の
為のアニールを兼ねた熱処理を施して、前記エピタキシ
ャル層より高不純物濃度のN9型の拡散層5を形成する
。次に、この拡散層5の表面露呈部を包含し、拡散層5
の拡散深さより浅いP″9型拡散拡散層8成して、P゛
型型数散層8対してN9型の拡散層5とエピタキシャル
層4とによりPN接合を形成する。その後は、半導体基
体表裏に電極を形成して可変容量ダイオード素子を形成
する。In FIG. 3, an epitaxial layer 4 having a resistivity of about 1 Ωcm, which is N-type and has a higher resistivity than the semiconductor substrate 1, is formed by vapor phase growth on a low-resistance N-type semiconductor substrate 1 to a thickness of 4.
The main surface of this epitaxial N4 is thermally oxidized to form a semiconductor substrate with a thickness of about 1 to 2 μm.
A thermal oxide film 2 (Si0g film) of μm thickness is formed. after that,
An opening is formed by an etching process, and an N-type impurity element is implanted into the epitaxial layer 4 through the opening at an acceleration voltage of 130 KeV and a dose of (2 to 3) x 10 "am-" by ion implantation. In the ion implantation process, impurity elements may be implanted through the oxide film of 100 to 3,000 layers.Next, heat treatment is performed that also serves as annealing to recover lattice defects and carrier recovery caused by ion implantation. Then, an N9 type diffusion layer 5 having a higher impurity concentration than the epitaxial layer is formed. Next, the diffusion layer 5 includes the surface exposed portion of the diffusion layer 5.
A P″9 type diffused layer 8 is formed which is shallower than the diffusion depth of , and a PN junction is formed between the P″ type diffused layer 8 and the N9 type diffused layer 5 and the epitaxial layer 4. Electrodes are formed on the front and back sides to form a variable capacitance diode element.
〔発明が解決しようとする課題]
上述の従来の可変容量ダイオード素子に於いては、P
++型の拡散層8の不純物濃度がN゛型の拡散層5やエ
ピタキシャル層4の夫々の不純物濃度より充分高いとす
れば、逆バイアス電圧vlを印加すると、P 41型拡
散層8内の空乏層の幅は、非常に狭く、N゛型の拡散層
5とエピタキシャル層4の領域内の空乏層の拡がりに較
べて無視できる程度である。可変容量ダイオード素子の
可変容量Cjは、N0型拡散層5とP++型拡散拡散層
8PN接合J1で発生する空乏層9による接合容ICJ
lと、N型のエピタキシャル層4とP ++型型数散層
8によるPN接合Jtで発生する空乏N10による接合
容量Cj2との合成容量である。エピタキシャル層4の
不純物濃度は、N0型の拡散層5のそれより低いのでエ
ピタキシャル層の空乏層10の拡がり幅は、拡散層5の
空乏rtJ9の拡がり幅より大きくなる。逆バイアス電
圧(印加電圧)■真を増減することによって空乏層9,
10の拡がり幅が増減する。従って、容量Cjl 、
CJzが可変してその合成容量である可変容@Cjが
可変する。[Problem to be solved by the invention] In the above-mentioned conventional variable capacitance diode element, P
If the impurity concentration of the ++ type diffusion layer 8 is sufficiently higher than the impurity concentration of each of the N゛ type diffusion layer 5 and the epitaxial layer 4, then when a reverse bias voltage vl is applied, the depletion in the P41 type diffusion layer 8 will be reduced. The width of the layer is very narrow and negligible compared to the spread of the depletion layer in the region of the N-type diffusion layer 5 and the epitaxial layer 4. The variable capacitance Cj of the variable capacitance diode element is the junction capacitance ICJ due to the depletion layer 9 generated in the N0 type diffusion layer 5 and the P++ type diffusion layer 8PN junction J1.
1 and a junction capacitance Cj2 due to the depletion N10 generated at the PN junction Jt formed by the N-type epitaxial layer 4 and the P++ type scattering layer 8. Since the impurity concentration of the epitaxial layer 4 is lower than that of the N0 type diffusion layer 5, the expansion width of the depletion layer 10 of the epitaxial layer is larger than the expansion width of the depletion rtJ9 of the diffusion layer 5. By increasing or decreasing the reverse bias voltage (applied voltage) ■ true, the depletion layer 9,
The spread width of 10 increases or decreases. Therefore, the capacitance Cjl,
When CJz is varied, the variable capacitance @Cj, which is the combined capacitance thereof, is varied.
一方、可変容量ダイオード素子の可変容量Cjは、次の
ような関係式で示される。On the other hand, the variable capacitance Cj of the variable capacitance diode element is expressed by the following relational expression.
但し、W、は空乏層の幅、N (x)は不純物濃度、K
、は半導体基板の誘電率、ε。は真空中の誘電率(8,
85x 10−” F/m” ) 、qは電子の電荷(
1,60X l O−” C) 、Φ、はPN接合の拡
散電位、nは不純物濃度の傾斜で決まる指数を表してい
る。However, W is the width of the depletion layer, N (x) is the impurity concentration, and K
, is the dielectric constant of the semiconductor substrate, ε. is the dielectric constant in vacuum (8,
85x 10-”F/m”), q is the electron charge (
1,60X l O-'' C), Φ represents the diffusion potential of the PN junction, and n represents an index determined by the slope of the impurity concentration.
これらの(1)(2)式がら空乏層の拡がりが、P″3
型拡散11BとPN接合を形成する半導体層4.5の不
純物濃度に依存していることが明らかである。From these equations (1) and (2), the expansion of the depletion layer is P″3
It is clear that it depends on the impurity concentration of the semiconductor layer 4.5 forming the PN junction with the type diffusion 11B.
従って、可変容量ダイオード素子に印加電圧VIIを印
加すると、拡散層5より不純物濃度の低いエピタキシャ
ルN4の空乏層10の拡がり幅W、!は、拡散層5に拡
がる空乏層9の幅WjIより大きくなり、更に、印加電
圧Vえを大きくすると、N1型拡散層5の周辺の空乏層
10が延びて半導体基板lにぶつかり、その後、印加電
圧■、を大きくしても空乏層10の拡がりがそれ以上進
まない、所謂容量−電圧特性の飽和傾向を示すことが(
1)(2)式から明らかである。Therefore, when the applied voltage VII is applied to the variable capacitance diode element, the width W of the depletion layer 10 of the epitaxial N4, which has a lower impurity concentration than the diffusion layer 5, expands, ! becomes larger than the width WjI of the depletion layer 9 extending to the diffusion layer 5, and when the applied voltage V is further increased, the depletion layer 10 around the N1 type diffusion layer 5 extends and collides with the semiconductor substrate l, and then the applied voltage Even if the voltage (2) is increased, the expansion of the depletion layer 10 does not proceed any further, showing a tendency to saturation of the capacitance-voltage characteristic (
1) It is clear from equation (2).
この状態を第4図の容量−電圧特性を示した図で説明す
れば、従来の可変容量ダイオード素子にあっては、たと
えば印加電圧■8が約15Vを過ぎると曲線の傾斜がゆ
るくなり、第4図の(イ)で示せば、印加電圧V、で飽
和傾向を示し、容量は、C8で飽和する。このように従
来の可変容量ダイオード素子では、周辺から延びている
空乏層10が半導体基板1に到達して容量が飽和して、
容量Cjの電圧変化比が小さくなる欠点がある。To explain this state using the diagram showing the capacitance-voltage characteristics in Figure 4, in the case of a conventional variable capacitance diode element, for example, when the applied voltage (1)8 exceeds about 15V, the slope of the curve becomes gentler. As shown by (A) in Figure 4, there is a tendency to saturate at the applied voltage V, and the capacitance is saturated at C8. In this way, in the conventional variable capacitance diode element, the depletion layer 10 extending from the periphery reaches the semiconductor substrate 1 and the capacitance is saturated.
There is a drawback that the voltage change ratio of the capacitor Cj becomes small.
これらの問題点を改善する為にエピタキシャル層4を厚
くすることで空乏層lOが半導体基板1にぶつかるのを
防ぐことができるが、拡散層5直下が厚くなる欠点があ
る。これでは、高周波直列抵抗R8が大きくなり、性能
指数Qが低下する欠点があり、従来のものよりエピタキ
シャル層4を厚くすることはできない。従って、高周波
直列抵抗R3が増加して、性能指数Qを損なうことなく
、容量−電圧特性の飽和傾向を改善するのが課題である
。In order to improve these problems, it is possible to prevent the depletion layer 10 from colliding with the semiconductor substrate 1 by increasing the thickness of the epitaxial layer 4, but there is a drawback that the region immediately below the diffusion layer 5 becomes thicker. This has the drawback that the high-frequency series resistance R8 increases and the figure of merit Q decreases, and the epitaxial layer 4 cannot be made thicker than the conventional one. Therefore, the problem is to improve the saturation tendency of the capacitance-voltage characteristics without increasing the high-frequency series resistance R3 and impairing the figure of merit Q.
本発明は、上述の如き課題を解消する為になされたもの
であって、その主な目的は、従来の可変容量ダイオード
素子にありがちな、容量−電圧特性の飽和傾向を改善し
、高周波直列抵抗R8が小さく、性能指数Qを低下させ
ることのない可変容量ダイオード素子を提供するもので
ある。The present invention has been made to solve the above-mentioned problems, and its main purpose is to improve the saturation tendency of capacitance-voltage characteristics that is common in conventional variable capacitance diode elements, and to improve the saturation tendency of high-frequency series resistance. The present invention provides a variable capacitance diode element with a small R8 and which does not reduce the figure of merit Q.
本発明の可変容量ダイオード素子は、第1導電型の半導
体基板に形成された該半導体基板より高比抵抗の第1導
電型のエピタキシャル層と、該エピタキシャル層に拡散
された該エピタキシャル層より低比抵抗の第1導電型の
拡散層と、該半導体基板と該エピタキシャル層との境界
部であって該第1導電型の拡散層直下を除く周辺部に形
成された該半導体基板より高比抵抗の第1導電型の埋込
層と、該第1の拡散層の主表面露呈部を覆う該第1の拡
散層とPN接合を形成する該第1の拡散層より低比抵抗
の第2導電型の第2の拡散層と、該半導体基体表裏に形
成された電極とからなる。The variable capacitance diode element of the present invention includes an epitaxial layer of a first conductivity type formed on a semiconductor substrate of a first conductivity type and having a higher resistivity than the semiconductor substrate, and an epitaxial layer of a first conductivity type having a resistivity lower than that of the epitaxial layer diffused in the epitaxial layer. A diffusion layer of the first conductivity type of the resistor and a resistor having a higher specific resistance than the semiconductor substrate formed at the boundary between the semiconductor substrate and the epitaxial layer except for directly under the diffusion layer of the first conductivity type. A buried layer of a first conductivity type, and a second conductivity type having a lower resistivity than the first diffusion layer forming a PN junction with the first diffusion layer covering the exposed main surface of the first diffusion layer. and electrodes formed on the front and back surfaces of the semiconductor substrate.
本発明の可変容量ダイオード素子は、半導体基体のPN
接合直下を除く部分のエピタキシャル層との間の半導体
基板に、エピタキシャル層と同程度の不純物濃度の埋込
層を形成して、PN接合の横側に延びる空乏層が、半導
体基板主表面より深く下方に延びるように高比抵抗の埋
込層を形成して容量−電圧特性の飽和傾向を改善したも
のである。The variable capacitance diode element of the present invention has a PN of a semiconductor substrate.
A buried layer with an impurity concentration similar to that of the epitaxial layer is formed in the semiconductor substrate between the epitaxial layer and the portion directly below the junction, so that the depletion layer extending to the side of the PN junction is deeper than the main surface of the semiconductor substrate. A buried layer with high specific resistance is formed so as to extend downward to improve the saturation tendency of the capacitance-voltage characteristics.
本発明の可変容量ダイオード素子について第1図、第2
図により製造工程に基づいて説明する。FIGS. 1 and 2 regarding the variable capacitance diode element of the present invention.
This will be explained based on the manufacturing process using figures.
N型であって低比抵抗の半導体基板1に、熱酸化膜2を
マスクとして埋込層となるN型の拡散層3をイオン注入
によって形成する。拡散層3は、次の工程で形成される
拡散層の直下を除く周辺に位置されている(第1図a)
。その半導体基体1に気相成長法によって、N型で半導
体基板1より高比抵抗の例えば1Ω口前後の比抵抗を有
するエピタキシャル層4を形成する。その厚さtは、高
周波帯域で使用するものであれば、従来のものと同じ4
〜5μm程度とする。尚、この値は、素子の電気的機能
によって異なる。この製造工程で埋込層3が形成される
。埋込N3には、N−導電型半導体層とN−導電型半導
体層が形成される(第1図b)。エピタキシャル層4の
主表面に熱酸化によって約1〜2μm程度の厚さの表面
保護の為の絶縁膜である熱酸化膜(330g膜)が形成
された後に、エツチングにより開口部6を形成する。An N-type diffusion layer 3 serving as a buried layer is formed by ion implantation in an N-type low resistivity semiconductor substrate 1 using a thermal oxide film 2 as a mask. The diffusion layer 3 is located at the periphery of the diffusion layer to be formed in the next step, except for directly below it (FIG. 1a).
. An N-type epitaxial layer 4 having a resistivity higher than that of the semiconductor substrate 1, for example, around 1Ω, is formed on the semiconductor substrate 1 by a vapor phase growth method. The thickness t is the same as the conventional one if it is used in a high frequency band.
The thickness should be approximately 5 μm. Note that this value varies depending on the electrical function of the element. A buried layer 3 is formed in this manufacturing process. An N-conductivity type semiconductor layer and an N-conductivity type semiconductor layer are formed in the buried N3 (FIG. 1b). After a thermal oxide film (330 g film) which is an insulating film for surface protection and has a thickness of about 1 to 2 μm is formed on the main surface of the epitaxial layer 4 by thermal oxidation, an opening 6 is formed by etching.
その開口部6からイオン注入によって、N型の不純物元
素(燐、砒素等)を、加速電圧が130KeV、ドーズ
量が(2〜3) x 10”ell−”(7)条件にて
開口部6を通してエピタキシャルN4に注入する。その
後、イオン注入による格子欠陥回復とキャリア回復の為
のアニールを兼ねた熱処理を施すと共に熱拡散を行って
拡散層5を形成する(第1図C参照)。この拡散工程で
開口部7に形成された熱酸化膜を用いてP型の不純物元
素(ボロン等)を加速電圧が20KeV、ドーズ量が(
5〜B ) X 10 l3cti−”の条件にてイオ
ン注入して熱処理を行って拡散層8を形成する(第1図
d)。続いて、この半導体基板表裏に導電体を被着して
電極形成を行う、このような製造工程で可変容量ダイオ
ード素子が形成される。N-type impurity elements (phosphorus, arsenic, etc.) are implanted into the opening 6 by ion implantation at an accelerating voltage of 130 KeV and a dose of (2 to 3) x 10"ell-" (7). Inject epitaxial N4 through. Thereafter, a heat treatment is performed that combines lattice defect recovery by ion implantation and annealing for carrier recovery, and thermal diffusion is performed to form a diffusion layer 5 (see FIG. 1C). Using the thermal oxide film formed in the opening 7 in this diffusion process, a P-type impurity element (boron, etc.) is applied at an accelerating voltage of 20 KeV and a dose of (
5-B) Ion implantation and heat treatment are performed under the conditions of " A variable capacitance diode element is formed through such a manufacturing process.
本発明の可変容量ダイオード素子は、第2図に示すよう
に空乏層の拡がり幅は、印加電圧によって、PNN接合
、直下の空乏層9と、P ++型型数散層8N−型エピ
タキシャル層4とのPN接合J2による空乏jW10が
、第2図に示すように発生する。空乏層10は、印加電
圧■8が増大するにつれて半導体基板1に向かって延び
て埋込層3に到達し、半導体基板1の中に面深く延びる
ので、その主表面で飽和することがない。又、エピタキ
シャル層4の厚さtを従来のものと同じ厚さとするなら
ば、拡散層5の下部のエピタキシャル層4の厚さは、従
来のものと同じ厚さであり、高周波直列抵抗R5を増す
ことなく、即ち、性能指数Qを低下させるごとく、容量
−電圧特性の飽和傾向を改善することができる。In the variable capacitance diode element of the present invention, as shown in FIG. A depletion jW10 due to the PN junction J2 is generated as shown in FIG. As the applied voltage 18 increases, the depletion layer 10 extends toward the semiconductor substrate 1, reaches the buried layer 3, and extends deep into the semiconductor substrate 1, so that it is not saturated at its main surface. Moreover, if the thickness t of the epitaxial layer 4 is the same as that of the conventional one, the thickness of the epitaxial layer 4 below the diffusion layer 5 is the same as that of the conventional one, and the high frequency series resistance R5 is It is possible to improve the saturation tendency of the capacitance-voltage characteristics without increasing the capacitance-voltage characteristics, that is, without decreasing the figure of merit Q.
従来の可変容量ダイオード素子の電圧−接合容量特性が
、第4図(イ)に示すように印加電圧■3で容量C8が
飽和状態となる。それに対して、本発明の可変容量ダイ
オード素子は、第4図(ロ)に示すように印加電圧■え
を増大して行くと空乏層lOが延び埋込N3に到達し、
半導体基板1の内部に深く延びて行く為に、印加電圧V
、では、その主表面で飽和に達することなく空乏層が延
び、半導体基板lのN”型半導体層に達する印加電圧v
Iになるまで飽和することがない。In the voltage-junction capacitance characteristic of the conventional variable capacitance diode element, as shown in FIG. 4(a), the capacitance C8 becomes saturated at the applied voltage 3. In contrast, in the variable capacitance diode element of the present invention, as the applied voltage increases, the depletion layer IO extends and reaches the buried N3, as shown in FIG. 4(b).
In order to extend deeply into the inside of the semiconductor substrate 1, the applied voltage V
, the depletion layer extends without reaching saturation on its main surface, and the applied voltage v reaches the N'' type semiconductor layer of the semiconductor substrate l.
It does not become saturated until it reaches I.
熱論、本発明の可変容量ダイオード素子によれば、高周
波直列抵抗R1と性能指数Qを改善する場合は、エピタ
キシャル層4を従来のものより薄くすればよいことは明
らかであり、埋込N3を形成することで容易に達成でき
る利点がある。According to the thermal theory, according to the variable capacitance diode element of the present invention, it is clear that in order to improve the high frequency series resistance R1 and the figure of merit Q, the epitaxial layer 4 should be made thinner than the conventional one, and the buried N3 should be formed. There are advantages that can be easily achieved by doing so.
本発明による可変容量ダイオード素子は、従来の可変容
量ダイオード素子の容量−電圧特性が、20V程度の印
加電圧で飽和傾向にあるのに対して、25Vを越えない
と飽和することのない良好な特性を示すものである。熱
論、数ボルト程度の低電圧で使用される可変容量ダイオ
ード素子にあっても同様に容量−電圧特性の飽和傾向を
抑えることができる効果を有する。The variable capacitance diode element according to the present invention has good characteristics that do not saturate unless the applied voltage exceeds 25 V, whereas the capacitance-voltage characteristics of conventional variable capacitance diode elements tend to be saturated at an applied voltage of about 20 V. This shows that. Thermal theory also has the effect of suppressing the saturation tendency of the capacitance-voltage characteristics even in variable capacitance diode elements used at low voltages of about several volts.
本発明の可変容量ダイオード素子は、エピタキシャル層
4の厚さtを変えることなく、PN接合下部を除く周辺
にN−、N−型の導電体の有する埋込層を形成すること
で、空乏層が半導体基板1の主表面で飽和することがな
いので、高周波直列抵抗R8を増加させることなく、且
つ、性能指数Qを損なうことなく容量−電圧特性の飽和
傾向を大幅に改善することができる利点を有する。The variable capacitance diode element of the present invention has a depletion layer formed by forming a buried layer having an N- or N-type conductor around the periphery except for the lower part of the PN junction without changing the thickness t of the epitaxial layer 4. does not saturate on the main surface of the semiconductor substrate 1, so the advantage is that the saturation tendency of the capacitance-voltage characteristics can be significantly improved without increasing the high frequency series resistance R8 and without impairing the figure of merit Q. has.
熱論、エピタキシャル層4の厚さtを薄くすることがで
きるので、拡散IW5と半導体基板1との間のエピタキ
シャル層4の厚さを従来のものより薄くすることが可能
である。従って、高周波直列抵抗R8を小さく設定でき
るので、性能指数Qを向上させることも可能である。Thermally, since the thickness t of the epitaxial layer 4 can be made thinner, the thickness of the epitaxial layer 4 between the diffusion IW 5 and the semiconductor substrate 1 can be made thinner than in the conventional case. Therefore, since the high frequency series resistance R8 can be set small, it is also possible to improve the figure of merit Q.
第1図a乃至dは、本発明の可変容量ダイオード素子の
製造工程を示す断面図、第2図は、本発明の可変容量ダ
イオード素子の空乏層の拡がりを説明する為の断面図、
第3図は、従来の可変容量ダイオード素子の断面図、第
4図は、可変容量ダイオード素子の容量−電圧特性を示
す為の図である。
1:半導体基板、2:熱酸化膜、3:埋込層、4:エピ
タキシャル層、5:N型拡散JW、8:P型拡散層、9
,10:空乏層、J、、J、:PN接合第 1 図1A to 1D are cross-sectional views showing the manufacturing process of the variable capacitance diode element of the present invention, FIG. 2 is a cross-sectional view for explaining the expansion of the depletion layer of the variable capacitance diode element of the present invention,
FIG. 3 is a sectional view of a conventional variable capacitance diode element, and FIG. 4 is a diagram showing the capacitance-voltage characteristics of the variable capacitance diode element. 1: Semiconductor substrate, 2: Thermal oxide film, 3: Buried layer, 4: Epitaxial layer, 5: N-type diffusion JW, 8: P-type diffusion layer, 9
, 10: Depletion layer, J, , J,: PN junction Fig. 1
Claims (1)
り高比抵抗の第1導電型のエピタキシャル層と、該エピ
タキシャル層より低比抵抗であって該エピタキシャル層
に拡散された第1導電型の拡散層と、該半導体基板と該
エピタキシャル層との境界部に位置し、該第1導電型の
拡散層直下を除く周辺部に形成された該半導体基板より
高比抵抗の第1導電型の埋込層と、該第1の拡散層の主
表面露呈部を覆う該第1の拡散層とによりPN接合を形
成する為の該第1の拡散層より低比抵抗の第2導電型の
第2の拡散層と、該半導体基体表裏に形成された電極と
からなることを特徴とする可変容量ダイオード素子。an epitaxial layer of a first conductivity type formed on a semiconductor substrate of a first conductivity type and having a resistivity higher than that of the semiconductor substrate; a diffusion layer, a first conductivity type buried layer having a higher specific resistance than the semiconductor substrate, which is located at the boundary between the semiconductor substrate and the epitaxial layer, and is formed in the peripheral area except directly under the first conductivity type diffusion layer; a second conductivity type having a lower specific resistance than the first diffusion layer for forming a PN junction by the first diffusion layer covering the exposed main surface of the first diffusion layer; A variable capacitance diode element comprising a diffusion layer and electrodes formed on the front and back surfaces of the semiconductor substrate.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1088689A JPH02191377A (en) | 1989-01-19 | 1989-01-19 | Variable capacitance diode element |
US07/466,244 US4987459A (en) | 1989-01-19 | 1990-01-17 | Variable capacitance diode element having wide capacitance variation range |
US07/466,204 US5017950A (en) | 1989-01-19 | 1990-01-17 | Variable-capacitance diode element having wide capacitance variation range |
US07/537,689 US5024955A (en) | 1989-01-19 | 1990-06-13 | Variable-capacitance diode element having wide capacitance variation range |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1088689A JPH02191377A (en) | 1989-01-19 | 1989-01-19 | Variable capacitance diode element |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02191377A true JPH02191377A (en) | 1990-07-27 |
JPH0574233B2 JPH0574233B2 (en) | 1993-10-18 |
Family
ID=11762799
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1088689A Granted JPH02191377A (en) | 1989-01-19 | 1989-01-19 | Variable capacitance diode element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02191377A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5789801A (en) * | 1995-11-09 | 1998-08-04 | Endgate Corporation | Varactor with electrostatic barrier |
-
1989
- 1989-01-19 JP JP1088689A patent/JPH02191377A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5789801A (en) * | 1995-11-09 | 1998-08-04 | Endgate Corporation | Varactor with electrostatic barrier |
Also Published As
Publication number | Publication date |
---|---|
JPH0574233B2 (en) | 1993-10-18 |
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