JPH02199564A - Fault recovery system for control memory - Google Patents

Abstract

PURPOSE:To recover a fault by processing data by another processor when a fault is generated in a control memory, comparing the processed result with positive data in a backup storage, replacing the defective memory by a substitutive memory and reconstituting the control memory. CONSTITUTION:A fault in a set 101 of a control memory 1 is read out by a register 105, an exclusive OR 6 is turned to '1' and the invalidation of an instruction stored in the register 105 is commanded to an invalidating circuit 12 through an OR gate 9. A DGU 10 reads out the contents of registers 5, 102, 105, 106 by fault information, reads out data from a memory 11 and compares both the read contents to detect a fault bit position. Writing data to the memory set 101 including the fault bit out of writing data to a control memory 1 are shifted so as to evade a memory string including the fault bit, the shifted data are reloaded to the control memory 1 and the control memory is reconstituted so that the memory storing including the fault bit is removed and a redundancy memory in the memory set including the memory string is added at the time of succeeding reading to recover the fault.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a fault handling method for an information processing device, and particularly to a fault recovery method for a control memory.

[Prior Art] Conventionally, a Hamming check using a Hamming code has been commonly used to detect control memory failures in information processing equipment, and for 1-bit failures, errors in the failed bit are corrected each time a failure is detected, and the error is corrected when the error is detected. The method used was to write the corrected data to the address in the control memory that was previously corrected.

[Problems to be Solved by the Invention] However, although the conventional methods are effective for temporary failures such as soft failures of memory elements due to alpha rays, they are not effective in cases where fixed failures occur in hardware. This has the disadvantage that the error is corrected every time a faulty address is read, which increases the control memory read cycle and requires repeating this fault processing, resulting in a significant drop in performance. Ta. Furthermore, there is no recovery means for 2-bit failures, and the hardware for the failure detection circuit and error correction circuit is quite large.

SUMMARY OF THE INVENTION In view of the above drawbacks, a technical problem of the present invention is to provide a control memory failure recovery method that reduces the burden on hardware and allows recovery without degrading performance even when a failure occurs. It is.

[Means for Solving the Problems] According to the present invention, in an information processing apparatus of a type in which a microprogram held in a backup storage is loaded into a control memory of a first processor, The second controller controls the microprogram loading operation.
A rewritable memory configured by arranging a processor of If a failure occurs in one column, the control memory is configured to include a redundant memory column to be used in place of the failed column, and if there is an error in the microinstruction read from the control memory, the contents correspond to the error. failure detection means for holding a microinstruction address and notifying the second processor of a control memory failure; the second processor, upon receiving the failure notification, detects an error in the backup memory corresponding to the erroneous microinstruction; reads the micro-instruction, identifies the erroneous bit position by comparing it with the above-mentioned erroneous contents, and avoids the memory string containing the faulty bit for data written to the memory set containing the faulty bit among the data written to the control memory. The control memory is reloaded using the shifted data as shown in FIG. A failure recovery method for a control memory is obtained, which is characterized in that it has a configuration for reconfiguring the control memory as performed in the following.

[Example] Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The control memory units 1 to 3 in the figure include a memory set 101 having 10 internal memory columns of 1 bit x 1024 words, and its write data register 1, as shown in detail in FIG.
02, a read data selector 104, and a read data register 105, and further includes a register 106 that holds the switching fg number of the selector 104. The selector 104 consists of nine switching circuits, each of which selects one of two adjacent bits of the outputs Z1 to Z1o of the memory set 101 and inputs it to the registers 1.about.5.

As switching signals, outputs S1 to S9 of register 1.6 are used.
is given corresponding to each switching circuit, and S is “0”.
When 2. When S, is "1", it operates to output z1+1.

(i-1, 2, . . . , 9) Register 1'o2 consists of 10 bits and holds data written to memory set 101. The register 105 consists of 9 bits and holds the outputs R1 to R9 of the selector 104, one bit of which is a parity pit.

The output of the register 105 is used as a microinstruction to control various parts within the information processing device. As shown in FIG. 1, a 10-bit address is input to the memory set 101 via a signal line A, and a write instruction signal is input via a signal line E.

Returning to FIG. 1, register 4 consists of 10 bits and includes memory set 10 in each of control memory sections 1 to 3.
1 address is held in common.

Further, the register 5 receives the output of the register 4 and holds the microinstruction address of the microinstruction held in each register 105. Exe I us i ve-OR
Circuits 6 to 8 are each register 105 in control memory units 1 to 3.
This is for detecting a parity error in the contents held in the memory, and the error output is logically summed by the OR gate 8 and inputted to the DGPIO.

DGPIO is an independent processor that mainly performs initial settings and troubleshooting inside the information processing device, and can control flip-flops in the information processing device using a shift bus.

In this embodiment, all the registers shown in FIG. 1 can be read or set using a series of shift buses starting from signal line SI and ending at signal line SO.

The storage device 11 is a memory device containing a microprogram storage area therein, and can be accessed arbitrarily by DGUlo. The invalidating circuit 12 is a gate circuit for invalidating the microinstruction on the signal line C when the OR gate 8 becomes "12".

Note that in FIG. 1, the memory set 101 and selector 104 in each control memory section are omitted and not shown.

Next, the operation of this embodiment will be explained in detail.

First, the microprogram initial loading operation at the time of initialization of the information processing apparatus including this embodiment is such that after the DGUIO validates the shift bus, all registers 06 in each control memory section are set to "0", and registers B to B9 of each register 02 are set to "0". The bit contains the load data (microinstruction word at microinstruction address "0") read from the storage device 11, the Blo bit of each register 102 contains 0#, and the register 4 contains the microinstruction address to be loaded. (all "0") using the shift bus, set the signal line E to a flat write enable state, write the contents set in each register 102 to each memory set 101, and then return to the write disable state. Finish loading one word of control memory. Thereafter, the microprogram is loaded into all words of the control memory in the same manner while sequentially changing the control memory load data set in register 102 and the microinstruction address set in register 4, and after all words have been loaded, the microprogram is shifted. Disable the bus.

After all words are completed, each memory set 1 of each control memory section
01 has effective microinstructions in the 1st to 9th columns;
Each column will be loaded with its parity. This means that 0'' is loaded into the 10th column, but it has no meaning.

When the initial microprogram load is completed, DGUIO
The second shift bus is disabled, and a microinstruction address to be executed is set in register 4 by a microprogram sequence control section (not shown). Next, the contents of the control memory corresponding to this microinstruction address are read out to each register 105 and used to control each part of the information processing device, and the next microinstruction address is set in the register 4. As long as a control memory failure does not occur, processing is sequentially performed by repeating this operation.

Now, suppose that a failure occurs in the fourth column of the memory set 101 in the control memory section 1 and the error data is read out to the register 105 in the control memory section 1.
The output of us 1ve-OR circuit 6 becomes “1” and OR
Instructs the invalidation circuit 12 to invalidate the microinstruction held in each register 105 via the gate 8, and
GUIO is notified of a control memory failure. Upon receiving the notification, the DGUIO first enables the shift bus and registers 5, 102, 105, and 105 of each control memory section.
The contents of the microinstruction 106 are read out, and the contents of the microinstruction corresponding to the microinstruction address obtained from the register 5 are read out from the microprogram area in the storage device 11. Next, this content and register 05 of each III memory section
Compare the microinstruction error data obtained from
Find the failed bit position.

(In this case, bit 04 of register 05 of control memory unit 1 is in error.) Furthermore, the contents of register 06 of control memory unit l, including the identified bit position, are all “0”.
”, and if it is all “0”, it is recognized as an unrecoverable failure and the recovery process is given up.

On the other hand, if all are "O", the B t -B s bits of register 02 in the control memory section 1 and the B
-13to bit and other registers in the control memory section 10
The load data (microinstruction word at microinstruction address "O") read from the storage device 11 is set in bits 81 to B9 of register 02 in control memory section 1, and bits B4 of register 02 in control memory section 1 and other control memories are set. Each of the 89 bits of register 02 in the unit is set to "0". Furthermore, the microinstruction address (all "0") to be loaded is set in register 4. These registers 4 and 102
After all settings are made using the shift path, signal line E
is set to a flat write enable state, and after writing to each memory set 101, the signal line E is returned to a write enable state to finish loading one word of the control memory. From now on, register 1
The microprogram is loaded into all words of the control memory in the same manner while changing the load data to the control memory set to 02 and the microinstruction address set to the register 4. When the loading of all words is completed, the effective microinstructions are stored in the first to third columns and the fifth to tenth columns in the memory set 101 in the control memory section 1, and the effective microinstructions are stored in the memory sets 101 in the other control memory sections. Valid microinstructions will be loaded in columns 1 to 9, respectively. This means that all "0"s are written in the remaining fourth column in the control memory section 1 and in each of the ten columns in the other control memory sections except for the faulty part, but this is meaningless. Finally, the register 106 in the control memory section 1 contains a value that will not read out the faulty memory column (in this case, "000111111"), and the register 105 in the control memory section 1 contains the correct data for the microinstruction in error. , the contents at the time of failure are set in the registers other than these using the shift path, and then the shift path is invalidated and the process ends. The example information processing device resumes processing, but of course continues to operate as if nothing had happened.

After this, the memory set 101 in the control memory section 2 or 3
Needless to say, even if a failure occurs, recovery from the failure is possible through similar processing.

[Effects of the Invention] As explained above, according to the present invention, when a control memory failure in an information processing device occurs, the processing is performed by a processor other than the failure device, and the failure data and the backup memory are retained. By comparing the data with the correct data, the location of the fault is recognized, the microprogram is reloaded into the control memory by replacing the fault location with an alternative memory, and the control memory is reconfigured. This has the effect of reducing the hardware load on the example processing device, and making it possible to recover even if multiple failures occur, as long as the alternative memory allows.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a detailed block diagram of each control memory section 1 to 3 in FIG. 1.2.3... Control memory section, 4, 5... Register, 6, 7. 8-Exclusive OR circuit, 8
-OR gate, 10... Processor for initial setting and fault processing, 11... Storage device, 12... Invalidation gate circuit, 101... Memory set, 402, 105,
106...Register, 104...Selector.

Claims (1)

[Scope of Claims] 1) In an information processing device of a type in which contents held in a microprogram area in backup storage are loaded into a control memory of a first processor, an operation of loading a microprogram into the first processor; a second processor that controls m rows by n columns (m, n
is a positive integer), the memory set is a rewritable memory in which one or more memory sets are arranged in the bit direction, and each memory set is such that a failure occurs in one column within the memory set. a control memory having a configuration including a redundant memory column for use in place of the faulty column in the event of an error in the microinstruction read from the control memory; the corresponding microinstruction address, and the second microinstruction address.
failure detection means for notifying a processor of a control memory failure, and when the second processor is notified of the control memory failure, the second processor detects an error in the backup memory corresponding to the address of the erroneous microinstruction. reads the microinstruction in the backup memory, compares the microinstruction in the backup storage with the erroneous content of the microinstruction to identify the erroneous bit position, and writes a memory set that includes the faulty bit among the data written to the control memory. As for the data written to the control memory, the data is shifted to avoid the memory column containing the faulty bit, and the data is reloaded into the control memory. A failure recovery method for a control memory, characterized in that the control memory is reconfigured so that the control memory is added with a redundant memory column in a memory set that includes the memory column.