JPH021985A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device which can be easily manufactured at a low cost by a method wherein not only a semiconductor region, possessed of a main current controlling function, is provided to one side of a breakdown strength retaining resistance semiconductor region, but also a low resistance semiconductor region and a semiconductor region of a conductivity type opposite to that of the high resistance semiconductor region are provided to the other side. CONSTITUTION:An N-type impurity is diffused into surface layer sections of both primary faces of a high resistance semiconductor mother material 1a to form low resistance semiconductor regions 7 respectively. After that, the underside of the semiconductor mother material 1a is abraded up to a position shown by a dotted line B, and a P-type semiconductor region 8 is grown on the above underside through an epitaxial growth. The upside of a high resistance region 1 is abraded up to a dotted line C so as to be as thick as required. The formed P-type epitaxial layer can be employed as a P-type semiconductor region 8 as it is, and a controllable range of the specific resistance and the thickness of the epitaxial layer by this method is extraordinary larger than that by a conventional epitaxial growth method, whereby a manufacturing cost can be remarkably reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Application of YR Chestnut) The present invention relates to a method for manufacturing a semiconductor device, and in particular to an insulated gate bipolar transistor (IGBl), a gate
Kuhn A-F Cyrisk (GTO) Electrostatic induction J(!j
Sui Risk (SIT)! :) Concerning the method used for power control.

(Prior Art) In Omi, the 6+1 electricity bill based on semiconductors is becoming more and more widespread. ``Used for gravity control''
￥ The conductor device used to be 1J when the meeting lister substituted it.
However, for small and medium capacity, bipolar 1
Herandysk is the mainstream. This is because the bipolar 1~range disk has been improved to allow high voltage operation, and its usability, such as its high speed operation and self-extinguishing function, is suitable for the usage requirements. . The demand for this trend will increase rapidly in the future, and there is a strong desire for a more sophisticated electric power semi-instrument Ia.

-・As a new electric power conductor device, highly interlocking Pl
Due to the advantage of low drive power, field effect transistors (
MO8t-transistor) is widely used in power devices. However, MOS t-
When the operating voltage of a transistor is increased, the cost increases because it is not possible to obtain 1q of ON voltage equivalent to that of a bipolar transistor unless the voltage rise is increased.
At 00V or 1000V or more, it is determined that it will not be used for a wide voltage as large as a bipolar 1 herange disk unless high-speed operation is required.

Half-j9 (
The A device is an insulated gate bipolar transistor (I
GBT) has been proposed and is beginning to be used in some areas. 6th
The figure shows a sectional view of the main parts of IG[3T. - The vicinity of the upper main surface has basically the same structure as a MOS l transistor, and has a high resistance semiconductor region 1. ] - le area, source area 3. Insulating film 4. There is a control electrode 5 that serves as a gate electrode, an upper main electrode 6 that serves as a source electrode, and the like. Although not shown in the figure, the control electrical terminal (the terminal for taking it out to the outside of the ship 5) is located on the upper main surface.

The region near the bottom ↑ is the drain region of the MOS t-transistor, which has a high concentration of impurities;
A conductive semiconductor region 8, which is responsible for the under-desk blade region 1, is formed and is connected to the lower electrode (4i9).

11 Low resistance installed between body region 1 and semiconductor region 8]
The colored region 7 has the same conductivity as the high resistance semiconductor region 1! This is a low-resistance semiconductor region with a high concentration of oxides.

Although this low acid b''iYη body region 7 is not physically essential for the operation of the IGBT itself, when a voltage is applied, the depletion layer extending from the source side extends to the semiconductor region 8 and punch-through. It is set so that it is difficult to move.MO8
I~Ran resistor (J dodehei Niro l G r3T,
In the case of high lightning pressure, the low resistance semiconductor region 7 is actually necessary in order to reduce the ON resistance while the ON resistance is small. That's what I'm talking about.

FIG. 7 shows the beginning of a conventional IGBT manufacturing process. I G [3'T" installation process is vertical M
Almost the same as OS t-transistor, vertical MOS
It differs from that of a transistor in that the conductivity of the wafer that is first processed is different, and that a low-resistance semiconductor region 7 that becomes a highly doped drain region is provided. First, as shown in FIG. 7(a), an IU U wafer (semiconductor IR material) 8a is prepared. This semiconductor base material 8a corresponds to the semiconductor region 8 in FIG. Next, as shown in FIGS. 7(b) and (C), the semiconductor base material 8a
A low-resistance Y conductor region 7 and a high-resistance semiconductor region 1 are sequentially formed on the substrate by growing 1 bit p9+. Thereafter, the process of forming the single region 2, source region 3, etc. on the high-resistance semiconductor region 1 is basically the same as the process of forming the MOS l-transistor. When the machining on the -upper main surface side is completed in this way, the lower main surface side of the semiconductor base material 8a is then cut at the position indicated by the dotted line A' in FIG. 7(C). In this way, the wrap-off process is necessary in the manufacturing process of IGBT'S semiconductor devices to prevent wafer cracking and to maintain the processing accuracy of the photolithography process. Since a certain level or more is required, the final thickness of the bl'-in-l' conductor 7N1/8a is 1.
If it is historical, it will be <' niimame ("tV>ru1,
After this, the lower nido electrode 9 is placed on the wrapped lower ↑ surface side.
is formed.

By the way, what is the reason for the P-noise in the Middle East in terms of the electronic functions of semiconductor devices? :S resistance'\conductor area 1 only (there is.This high resistance '4ζ conductor area 1's resistance is
Half 4 (a certain degree depending on the voltage resistance characteristics required of the A device): i Definitely necessary. In addition, if the thickness is too large, good T<CON characteristics cannot be obtained. - Generally speaking, for electric power 21' glue body devices-) -'C, 'The thickness of the region of the cardiac pressure holding part has a wood-like characteristic in both the width of the specific resistance. be.

Note that if there is no low-resistance semiconductor region 7, 1' pixel (
Instead of using Nord growth, it is possible to use the diffusion technique normally used in bipolar transistors. In this case, the high resistance conductors 11i and 11 are placed on the wafer base material, and the opposite side 47j is placed on the mold's 't' i.
9 off duty! ! ! 8 by diffusion of impurities, and polish the unnecessary soil surface side with 01. However, IG[31-
seaweed? The life time of t% of people needed to prevent risk behavior -1 is originally I G +3 T is 11
Low-resistance semiconductor device 1, which significantly impairs the large current carrying capacity of the device, resulting in a significant increase in ON resistance.
1! ! The presence of 7 is indispensable because of the double layer of conductor region 8 and low-resistance semiconductor region 7 (diffused wafers that are difficult to create for 14N are not used for 1G [3T]). stomach.

In addition, the introduction of life time = Vura mentioned earlier,
J, this is being done to diffuse life time killer substances and perform long-distance irradiation1.This is MOS.
This method is no different from the method used when controlling the lifetime using an L-transistor.

[Problems to be solved by the invention] IGBTs have the great advantages of high current carrying capacity at i0i voltage, high switching speed, and low driving power (J), but they are bipolar 1 -Currently, it is difficult to develop a device that can surpass transistors.This is due to the fact that the manufacturing process requires microfabrication, which, combined with delicate life-time control, results in poor yields and wafer damage. This is because the cost of materials is high due to the need for a pitaxe growth process, and the cost of bupp cannot compete with it.Although it is more difficult to manufacture, improvements are expected. However, the material cost of IG[3T is unavoidable compared to a bipolar 1-transistor that does not require epiramidity formation. By comparison, an IGBT wafer has approximately 2 'iF' + n
(There is ilI"C. Furthermore, if it becomes 1000v class,
The filli case for bipolar transistors is [
While Jdo/υ remain the same, IG[3T has a difference of about 2
8 necessary and < 2 1 pita: 1 layer thickness
Accordingly, it is nearly 12 times more expensive than C. In this way, as a high pressure element, the main element of
Semiconductor device 11'ff using a vitaxitol growth layer
However, there is a problem in that the manufacturing cost increases rapidly as the rated voltage increases.

Figure 8 shows l0 where the +tll case is currently being announced as tt+.
This is an example of BF's HakuyB method. This method does not use epitaxial layer formation. 4c Straw, Figure 8 (a
), the high-resistance semiconductor region 1 is used as the wafer material, and the eighth
As shown in FIGS. (b) and (c), there is a low resistance semiconductor region 7 on the lower surface side and a high resistance semiconductor device i! ! A semiconductor region 8 of a core type different from 1 is separately diffused and formed. When the F plane fff14i9 is formed on this lower main surface, the low resistance semiconductor device 1a7 and the semiconductor device II! It is short-circuited with t8. This shape is gate turn-off → Neurisk (
This is a structure well known as an anode short circuit in GTO). It is contradicted that if this form is adopted, it will be possible to make a simple life time control or to omit the life time control. Perform life time control, etc.
The above manufacturing method has great advantages since it necessarily results in an increase in ON resistance. But 1. However, the problem with this method is that the base material is young (the thickness of the high-resistance semiconductor region 1 is about 10Q ft m in a practical 1000V class element), and the wafer is Due to cracking and warping of the wafer, it is extremely difficult to produce a prototype, let alone produce it in humans.

Is this because of low resistance? After forming the r-conductor region 7 and the semiconductor region 8, a method is taken in which polysilicon is deposited on five sides, the thickness of the soil is increased, and after the necessary steps are performed, the polysilicon is removed. This has the problem of complicating the manufacturing process.

The present invention has been made to solve the above-mentioned conventional problems. and (b), a power conductor neck in which an IL low-resistance semiconductor region and a conductor region of the opposite conductivity type to the high-resistance semiconductor region are (respectively installed) on the other side,
Cheap and easy! ! ! ! The object of the present invention is to provide a method for constructing a conductor device.

(Method I?2 for Solving the Problems) In order to achieve the above object, the method for manufacturing a semiconductor device of the present invention includes a step of providing a high resistance semiconductor device H of a first conductivity type, and a step of providing the semiconductor device H of the first conductivity type. The first layer is placed in the layered part on the ambidextrous side of the material.
forming a low-resistance semiconductor region by diffusing conductive type impurities, and forming a second conductive type semiconductor on all or part of one surface of the semiconductor device H by epitaxy. a step of wrapping off the semiconductor base material so that the low resistance semiconductor region on the other main surface side of the semiconductor base material is removed; The method includes forming a semiconductor region that controls a main current control function, a first main electrode, and a control electrode, and also forming a second main electrode on one main surface side.

[For fishing]

According to the method of manufacturing a semiconductor device of the present invention, a high-resistance semiconductor region for maintaining breakdown voltage is formed on a semiconductor (A) base material, and a low-resistance semiconductor region of the same conductivity type as the semiconductor (Nl) material is formed. Since the semiconductor region of the opposite conductivity type to the semiconductor package is formed by the -1-pixel process, even if the rated voltage increases, the thickness of the semiconductor base material only increases. can keep manufacturing costs low.

〔Example〕

FIG. 1 shows a method for manufacturing a semiconductor device according to a first embodiment of the present invention, and here, the case of an IGBT in which the high resistance semiconductor region is of N type will be explained as an example.

First, as shown in FIG. 1(a), an N-type high-resistance semiconductor base material 10 having a predetermined ratio II (resistance I) is prepared.

This high-resistance resistor 1' conductor material 1a corresponds to the high-resistance semiconductor region 1 in FIG. Next, as shown in FIG. 1(b),
An N-type impurity is diffused into the resistive region to form a low relative resistance resistor 1 and a main region 7, respectively. (After that, position the bottom side of the conductor 1z1 material 1a as indicated by the dotted line B in Figure 1(b).
+tn polish, J shown in No. 11'A (C), -I pita 1 on the bottom side of the sea urchin! ! Perform the le formation and I) Type half-venerable realm 1
Form 11!8 Cf. , the thickness of the 1-pitch layer is as high as the thickness of the next layer (4 inches and 200 mm) so that wafer cracking is not a problem.
(approximately μyn). Next, as shown in FIG. 1(C), the upper surface is polished to the position of the dotted line C so that the high resistance region 1 has a predetermined width n (FIG. 1 fd
)reference>. The subsequent process differs from the conventional manufacturing process only in that there is no senzai process on the bottom surface.

The cross-sectional view of the completed semiconductor device is the same as that of the conventional example shown in FIG. 6, and has four parts.

The epitaxial layer of Pffl thus formed can be used as it is as the P-type semiconductor region 11!8. In this case, for a relatively low voltage element,
Since the high-resistance semiconductor region 1 is thin, a 1-pitaxy-II layer with a thickness of several tens of μm or more is required to prevent wafer cracking. Compared to the conventional method of Ebiku V-silk growth, the yield is orders of magnitude larger and the manufacturing cost is significantly lower.

In addition, an anti-semi 19 (
Since the A region 7 has a low impurity concentration in the rlIl polished layer as indicated by the dotted line B (FIG. 1(b)), the formed P-type Evita 1
: A thermal diffusion process is performed using the Schal layer as an impurity diffusion source, and P
type semiconductor region 8 is originally an N-type low resistance semiconductor region 7
It can also be easily formed inside.

In this case, the low resistance shown in Figure 1(c)! ￥ j9 body area 11!
Since the thickness of I7 can be kept at jJ, the thickness of the epitaxy 1 full layer to form a predetermined wafer 11 can be thermally expanded rIl? ：”It can be thinned by the amount of thickness it advances.

FIG. 2 shows the 7J method for manufacturing a semiconductor device, which is a second embodiment of the present invention. :L, as shown in Figure 2 (al), prepare one high resistance half-and-half RJ1a of NJ12 with a predetermined resistivity, and as shown in Figure 2(b), N-type impurities are diffused into the surface layer on both sides of the sea urchin to form low-resistance semiconductor regions 7. After that, the 9-piece r
'The lower surface side of the Nl material 1z1 is polished to the dotted line B in Fig. 2 (b) (☆).
, ゛), form a mask 10 with ly on the lower surface side from the interbody compound, and after opening ``1'' on the ``-'' part, l')
Form a T big 1 11 layer of IJ. This place,
As shown in Fig. 2(d), one L is connected to the mask opening.
The pitaxitol portion forms a P-type single crystal semiconductor region 8, and the epitaxial portion on the mask 10 forms a polycrystalline conductor region (or 11). 1'1 body chain region 11 is removed.If the Evita J: It is possible to tumble the other side of the surface, but ■ Form the mask for the tbung on the corresponding lower main surface, and use the previously formed epitaxial layer. It is desirable to use the mask 10 for etching as an etching prevention area.

After removing the semiconductor region 11, the mask 10 is removed;
As shown in Figure 3, I'3' 2-body region I! ! After forming the insulating film 12 on both sides of the part 1B, the part F J is formed on the main surface side of the part .

9 is formed.The same method as the example explained in FIG. 1 can be applied to the processing of the main surface of the tenth part.
The figure shows part of the new surface of I G nl created in this way. In the insulating film 12 in the figure, during the operation 1h of IQ[3T, current flows concentratedly at the cobblestone boundary between the low-resistance semiconductor region Vi7 and the lower L electrode 9 in the semiconductor (11 of the A region 8). In this method, the point at which the polycrystalline semiconductor region 11 is removed is from the direct 1ν of epitaxial growth to the bottom main surface electrode. Select the appropriate time until the culm is formed.If wafer p:4 is a9, (well, the later this point is, the more 1-honey 11 will have a -C right effect.

FIG. 1 shows another example, in which a P-type 1-pitch 4. A case is shown in which a thermal diffusion process is applied using the sit/ru layer 8 as an impurity diffusion source. In this case, the wafer thickness = I L' (the same effect as explained in Fig. 1 is obtained. Also, this l
G13T has a high concentration of N type ゛1 in J, ) as shown in Figure 4.
'Conductor area 1a! 13 are provided. This N type ゛1'
After removing the polycrystalline semiconductor region 11 and the mask 10 as shown in FIG. It is formed by penetrating into the surface layer of the semiconductor region 7.This N-type γ barrel 't+ region 13 LL, NJS'! ] ) jj, round wire B″c Polished invasive impurity concentration decreases, so lower part 1 city (41
This is a sign that is provided to change the a continuation of the word ``a''. Of course/υ, in the case of Fig. 3, bl this 4′η body area 1
! l! It is possible to provide 13.

FIG. 5 shows an embodiment characterized in that the conductor region 8 of the selectively formed epitaxial layer is polished by ω1. Specifically, in FIG. 2(d), after removing the polycrystalline semiconductor region 11 and the mask 10,
An N-type semiconductor region 13 having a lower electrical resistance than the low resistance semiconductor region 7 is formed over the entire lower main surface, and then the semiconductor region 8
Part of it for N¥! Wrap-off with part of the conductor region 13.

This l1II polishing can improve the coverage of the lower main electrode 9. In addition, the same lower main ', f as shown in the figure
This is to improve the connectivity with the single pole 9, but according to the 17'Jγm shown in FIG. N-type impurities can be diffused onto the lower L plane.

In addition, in the above-mentioned figures 1 to 5, Pbe°! and N
Don't worry about reversing the polarity of the mold.

Furthermore, although the above explanation has been made with respect to GBT, other GTOs, SITs, Cyrisks, etc., have conductive areas that are responsible for the men's helmet. 1′! 1 tree 1↓
Regarding the location, it is clear that there is a Sung Dynasty in 91.

(Invention 2! + 'A) This IN Ming's Ten Forces (A device's design Ij method: If J:, then resistance Jl-, C <I'J river (1) +C mouth fee b i 'l
'4 body hl 1・(/J"t-hiro [41'J shrine niyori [41'
! Low If (lA21' interrogation territory toy is spreading prostitution 1! J
, ri is formed, and 'L' 79-day INJ U and the opposite Fuden-type cliff 39-day region is L pixitol growth, ``, ri is formed, so the constant 18-dens bar is high I Ju combination C' MU Ryo 4 (Thursday 1!L 44 no 11) Mi/i: 1 So cJ (", J, <, Made because there is no need to increase Epic 1 Sittle Seiwa C11) also reduces the cost by one generation. As soon as it happens, 1
There is no need to remove the Ift product of volicilin 1 on the lower surface by applying -V and removing it, and there is no need to complicate the installation Δ process.

[Brief explanation of the drawing]

The first embodiment of this invention is a cross-sectional view of the method for making a neck on a conductor, and FIG. - A certain cliff 4) Construction of a resting device/J method showing each T culm A sectional view of the main parts of IGBT created by the method,
Fig. 5 is a cross-sectional view of the main parts of an IGBT made by Haku Zara's method, Fig. 6 is a cross-sectional view of the main parts of a conventional IGBT, Fig. 7 is a cross-sectional view showing the manufacturing process. The figure shows the conventional IG
It is a sectional view showing a culm of BT. In the figure, 1a is a high-resistance semiconductor base material, 5 is a control electrode,
6 is an upper main electrode, 7 is a low resistance semiconductor region, 8 is a semiconductor region, and 9 is a lower main electrode. In each figure, the same reference numerals refer to circuits or corresponding parts.

Claims (1)

[Claims] (1) A step of preparing a high-resistance semiconductor base material of a first conductivity type, and diffusing impurities of a first conductivity type into the surface layer portions of both main surfaces of the semiconductor base material to form low-resistance semiconductor regions. a step of forming a second conductivity type semiconductor region on all or part of one main surface of the semiconductor base material by epitaxial growth; and a step of forming a second conductivity type semiconductor region on the other main surface side of the semiconductor base material by epitaxial growth. lapping off the semiconductor base material so as to be removed; forming a semiconductor region having a main current control function, a first main electrode, and a control electrode on the other main surface side of the wrapped-off semiconductor base material; A method of manufacturing a semiconductor device, comprising: forming a second main electrode on one main surface side.