JPH02181463A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02181463A JPH02181463A JP64000330A JP33089A JPH02181463A JP H02181463 A JPH02181463 A JP H02181463A JP 64000330 A JP64000330 A JP 64000330A JP 33089 A JP33089 A JP 33089A JP H02181463 A JPH02181463 A JP H02181463A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- resin
- alloy
- semiconductor device
- moisture
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 31
- 239000011347 resin Substances 0.000 claims abstract description 24
- 229920005989 resin Polymers 0.000 claims abstract description 24
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 15
- 239000000956 alloy Substances 0.000 claims abstract description 15
- 238000007747 plating Methods 0.000 claims abstract description 15
- 229910020938 Sn-Ni Inorganic materials 0.000 claims abstract description 9
- 229910008937 Sn—Ni Inorganic materials 0.000 claims abstract description 9
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 238000000465 moulding Methods 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims 1
- 229910000990 Ni alloy Inorganic materials 0.000 claims 1
- 239000010949 copper Substances 0.000 claims 1
- 238000010438 heat treatment Methods 0.000 abstract description 8
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 abstract description 3
- 230000001590 oxidative effect Effects 0.000 abstract description 2
- 239000000853 adhesive Substances 0.000 description 16
- 230000001070 adhesive effect Effects 0.000 description 16
- 239000000463 material Substances 0.000 description 9
- 230000008595 infiltration Effects 0.000 description 4
- 238000001764 infiltration Methods 0.000 description 4
- 235000014676 Phragmites communis Nutrition 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に係り、特に、半導体素子を搭載す
るリードフレームの構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of a lead frame on which a semiconductor element is mounted.
半導体装置は、その電気的動作をする半導体素子が極め
て小さいため、パッケージ化され外的障害防止とともに
その取扱いを容易にしている。そして、パッケージには
半導体素子の各電極に接続されたリードが突出している
。Semiconductor devices have extremely small semiconductor elements that operate electrically, so they are packaged to prevent external damage and facilitate handling. Leads connected to each electrode of the semiconductor element protrude from the package.
具体的な例には、デュアルイン型の樹脂封止半導体装置
があり、その製造においては、まず、放射形状に配置さ
れる複数のリードと、これらリードの先端部に配置され
る平板と、これらを結束するフレームとからなるリード
フレームを用意し、平板上に半導体素子をダイボンディ
ングした後、半導体素子の各電極とこれらに対応する他
のリードの先端部をワイヤボンディングで接続する。そ
して、半導体素子とその周辺部をリードフレームの表裏
面から樹脂をモールドすることにより被覆し、リードフ
レームのフレーム部のみをプレス等で除去するとともに
、リード部を一定の方向に折曲げることにより完成する
。リードフレームには４２合金（Ｎｉ：４２％；Ｆｅ：
５８％）が用いられている。A specific example is a dual-in type resin-sealed semiconductor device, and in manufacturing it, first, a plurality of leads arranged in a radial shape, a flat plate arranged at the tips of these leads, and After preparing a lead frame consisting of a frame for binding together semiconductor elements and die-bonding semiconductor elements onto a flat plate, each electrode of the semiconductor element and the corresponding tip of another lead are connected by wire bonding. Then, the semiconductor element and its surrounding parts are covered by molding resin from the front and back sides of the lead frame, and only the frame part of the lead frame is removed using a press, etc., and the lead part is bent in a certain direction to complete the process. do. The lead frame is made of 42 alloy (Ni: 42%; Fe:
58%) are used.
しかし、このように構成される半導体装置は樹脂の各リ
ード部の取出口で、樹脂と各リードとの接着界面には微
小な隙間が生じている。このため。However, in a semiconductor device configured in this manner, a minute gap is created at the adhesive interface between the resin and each lead at the outlet of each lead portion of the resin. For this reason.
この隙間から水分が浸入し、半導体素子上の電極や配線
を腐食させるという問題がある。水分の浸入を防止する
には、樹脂とリードとの接着力を高めることが重要であ
る。従来技術には、４２合金リードを０２雰囲気中で約
４００℃に加熱し、表面に酸化膜を形成して接着力を高
める方法が、特開昭６２−１４５７５４号公報に記載さ
れている。There is a problem in that moisture enters through this gap and corrodes the electrodes and wiring on the semiconductor element. In order to prevent moisture from entering, it is important to increase the adhesive strength between the resin and the lead. In the prior art, JP-A-62-145754 describes a method in which a 42 alloy lead is heated to about 400° C. in an 02 atmosphere to form an oxide film on the surface to increase adhesive strength.
一方、近年、半導体は増々高集積化し、そのため半導体
素子は大形化している。しかし、素子が大形化する割に
はパッケージの外形はほとんど変化しないため、水分の
浸入径路が増々短くなり、前述の腐食が起こり易くなっ
ている。このような状況に対して、従来の方法では水分
の浸入を防ぐことができず、新しいリード材が強く望ま
れている。On the other hand, in recent years, semiconductors have become increasingly highly integrated, and as a result, semiconductor elements have become larger. However, as the size of the device increases, the outer shape of the package hardly changes, so the path for moisture to penetrate becomes shorter and shorter, making it easier for the above-mentioned corrosion to occur. In this situation, conventional methods cannot prevent moisture from entering, and new reed materials are strongly desired.
〔発明が解決しようとする課題〕
上記従来技術は近年の高集積化の半導体には考慮されて
おらず、半導体素子の電極や配線が腐食し易いという問
題があった。[Problems to be Solved by the Invention] The above-mentioned conventional technology has not been taken into consideration in recent years with highly integrated semiconductors, and there has been a problem in that the electrodes and wiring of semiconductor elements are easily corroded.
本発明の目的は、樹脂とリードとの接着力を高め・て水
分の浸入を防止して素子の耐湿信頼性を向上させ、信頼
性の高い半導体装置を提供することにある。An object of the present invention is to provide a highly reliable semiconductor device by increasing the adhesive force between a resin and a lead to prevent moisture from entering, thereby improving the moisture resistance reliability of an element.
従来、用いられているリード材は４２合金（Ｎｉ：４２
％、Ｆｅ：５８％）である。樹脂とリードとの接着強度
はリード材やその表面状態によって大きく変化する。４
２合金は樹脂との接着強度が著しく低く、従来技術であ
る酸化させる方法を用いてもそれ程強度は向上しない。Conventionally, the lead material used is 42 alloy (Ni: 42
%, Fe: 58%). The adhesive strength between the resin and the lead varies greatly depending on the lead material and its surface condition. 4
The adhesive strength of Alloy No. 2 with resin is extremely low, and even if the conventional oxidation method is used, the strength cannot be significantly improved.
第７３図は各種リード材を加熱し、表面を酸化させた場
合の樹脂との接着強度を加熱温度に対してプロットした
ものである。従来技術である４２合金を加熱した場合の
接着強度はＳｎ−Ｎｉ、Ｃｕ、 Ａｇ、および、Ｎｉ等
に比べて低いことが明らかである。FIG. 73 shows the adhesive strength with resin when various lead materials are heated to oxidize their surfaces, plotted against heating temperature. It is clear that the adhesive strength of conventional 42 alloy when heated is lower than that of Sn-Ni, Cu, Ag, Ni, etc.
第３図より、ＣｕおよびＳｎ−Ｎｉは樹脂との接着強度
が著しく高いことがわかる。また、これらを加熱し、表
面を酸化させることによって、加熱しない場合よりさら
に接着強度は高くなることもわかる。従って、Ｃｕおよ
びＳｎ−Ｎｉを４２合金上にめっきし、その表面を加熱
・酸化させることによって樹脂との接着強度を高くでき
るものと考えられる。第４図は、従来、４００℃に加熱
。From FIG. 3, it can be seen that Cu and Sn--Ni have extremely high adhesive strength with resin. It can also be seen that by heating these to oxidize the surface, the adhesive strength becomes even higher than when not heated. Therefore, it is considered that the adhesive strength with the resin can be increased by plating Cu and Sn-Ni on the 42 alloy and heating and oxidizing the surface. Figure 4 shows conventional heating at 400°C.
酸化させた４２合金の樹脂との接着強度と本発明の表面
を酸化（Ｃｕは２００℃、Ｓｎ−Ｎｉは４００℃に加熱
）させたＣｕおよびＳｎ−Ｎｉめつき膜で被われた４２
合金のそれとを比較したものである６本発明のいずれの
リード材においても従来のリード材に比べて高い接着強
度を示すことがわかる０次に、このリード材に樹脂をモ
ールドした後、加圧した水蒸気中に放置し、水分の浸入
率を調べた。すなわち、第５図（ａ）に示すような形状
のリードフレームに４２合金を加工後、リードの表裏面
にＣｕ、および、Ｓｎ−Ｎｉめつきを施こし、加熱によ
ってぬつき暎の表面を酸化させる。加熱温度は前述と同
じである。その後、トランスファモールド装置を用いて
樹脂をモールドし、高圧の水蒸気中に放置した９第５図
（ｂ）に水分が浸入したリードの割合を示した。従来の
酸化させた４２合金リードは１００％近く水分が浸入す
るのに対し、本発明のリードでは、５０％以下であり、
水分が浸入しにくいことがわかる。The adhesive strength of the oxidized 42 alloy with the resin and the surface of the 42 alloy of the present invention covered with a Cu and Sn-Ni plating film that has been oxidized (heated to 200 °C for Cu and 400 °C for Sn-Ni)
Comparison with that of alloy 6 It can be seen that all the lead materials of the present invention exhibit higher adhesive strength than conventional lead materials.Next, after molding resin on this lead material, pressure is applied. The sample was left in water vapor to examine the rate of moisture infiltration. That is, after processing 42 alloy into a lead frame having the shape shown in Fig. 5(a), Cu and Sn-Ni plating are applied to the front and back surfaces of the lead, and the plating surface is oxidized by heating. let The heating temperature is the same as above. Thereafter, the resin was molded using a transfer molding device and left in high-pressure water vapor. Figure 5(b) shows the proportion of the leads into which moisture had penetrated. While the conventional oxidized 42 alloy reed has nearly 100% moisture infiltration, the reed of the present invention has less than 50% moisture infiltration.
It can be seen that moisture is difficult to penetrate.
ｒ作用〕
酸化させたＣ’ｕおよびＳｎ−Ｎｉめっき膜は樹脂と強
固に接着する。それによって樹脂とリードとの接着界面
に隙間がなくなり、外部の水分が浸入せず、耐湿性が向
上する。r effect] The oxidized C'u and Sn-Ni plating films firmly adhere to the resin. As a result, there is no gap at the bonding interface between the resin and the lead, preventing external moisture from entering, and improving moisture resistance.
〈実施例１〉
第１図（ａ）は本発明による半導体装置の一実施例を説
明するためのリードフレームの平面図である。リードフ
レーム１は放射形状に配置されろ複数個のリード２と、
半導体素子がダイボンディングされる比較的面積の大き
いタブ３とが一体的に形成されている。このリードフレ
ームはＦｅ−Ｎｉ系合金であり、プレス成形して形成さ
れる。<Embodiment 1> FIG. 1(a) is a plan view of a lead frame for explaining an embodiment of a semiconductor device according to the present invention. A lead frame 1 has a plurality of leads 2 arranged in a radial shape,
A relatively large tab 3 to which a semiconductor element is die-bonded is integrally formed. This lead frame is made of a Fe-Ni alloy and is formed by press molding.
リード２の最先端部にはＡｇめっき４が施こされ、さら
に、このリード２の先端部は表面が酸化したＳｎ−Ｎｉ
めつき膜５が表裏面にわたって形成されている。酸化は
そのめっき膜を１００〜４００℃に加熱することにより
行なう。The leading edge of the lead 2 is coated with Ag plating 4, and the leading edge of the lead 2 is coated with Sn-Ni with an oxidized surface.
A plating film 5 is formed over the front and back surfaces. Oxidation is performed by heating the plated film to 100 to 400°C.
同図（ｂ）は（ａ）で示したリードフレームに半導体素
子を搭載し、素子６上の電極とリード２のＡｇめっき上
にワイヤ７を介して接続した後、樹脂８をモールドした
半導体装置の断面である。Figure (b) shows a semiconductor device in which a semiconductor element is mounted on the lead frame shown in (a), connected to the electrode on the element 6 and the Ag plating of the lead 2 via the wire 7, and then molded with resin 8. This is a cross section of
〈実施例２〉
第２図は第１図（ａ）のリード２の先端部分に表面が酸
化したＣｕめつき膜９が表裏面にわたって形成されてい
るリードフレームをもつ半導体装置の断面図である。<Example 2> FIG. 2 is a cross-sectional view of a semiconductor device having a lead frame in which a Cu plating film 9 with an oxidized surface is formed on the front and back surfaces of the tip portion of the lead 2 shown in FIG. 1(a). .
本発明によれば、樹脂とリードとが強固に接着できるの
で、樹脂とリードとの接着界面に隙間ができず、水分が
浸入しないため耐湿信頼性の高い半導体装置を提供でき
る。According to the present invention, since the resin and the lead can be firmly bonded, no gap is formed at the adhesive interface between the resin and the lead, and moisture does not enter, so that a semiconductor device with high moisture resistance and reliability can be provided.
第１図および第２図は本発明の一実施例の半導体装置の
断面（ａ）とリードフレームの平面図（ｂ）、第３図は
各種リード材を加熱した場合の樹脂との接着強度の関係
を示した図、第４図は本発明のリードと樹脂との接着強
度を従来のものと比較して示した図、第５図は本発明の
リード材を用いた樹脂封止品の水分浸入率を示した図で
ある。
１・・・リードフレーム、２・・・リード、３・・・タ
ブ、４・・・Ａｇめっき部、５・・・表面が酸化したＳ
ｎ−Ｎｉめつき膜、６・・・半導体素子、７・・・ワイ
ヤ、８・・・樹脂、９・・・表面が酸化したＣｕめつき
膜。
第１ （２）
茶２ 図
＃３
図
甚４
図Figures 1 and 2 show a cross section (a) of a semiconductor device according to an embodiment of the present invention and a plan view of a lead frame (b), and Figure 3 shows the adhesive strength of various lead materials with resin when heated. Figure 4 is a diagram showing the relationship between the adhesive strength of the lead and resin of the present invention in comparison with the conventional one, and Figure 5 is a diagram showing the moisture content of the resin-sealed product using the lead material of the present invention. It is a figure showing an infiltration rate. 1... Lead frame, 2... Lead, 3... Tab, 4... Ag plating part, 5... S with oxidized surface
n-Ni plating film, 6... Semiconductor element, 7... Wire, 8... Resin, 9... Cu plating film with oxidized surface. 1st (2) Tea 2 Figure #3 Figure #3 Figure 4
Claims (1)
させるリードと、前記半導体素子と前記リードとをモー
ルドする樹脂とからなる半導体装置において、 少なくとも樹脂モールドさせる内側の前記リードが表面
に酸化膜が形成されためつき膜で被われたＦｅ−Ｎｉ合
金であることを特徴とする半導体装置。 ２、前記めつき膜はＳｎ−Ｎｉ合金及び銅であることを
特徴とする特許請求項第１項記載の半導体装置。[Scope of Claims] 1. A semiconductor device comprising a lead connected via a wire to each electrode formed on a semiconductor element, and a resin for molding the semiconductor element and the lead, at least the inner part of the resin molded part. A semiconductor device characterized in that the leads are made of an Fe--Ni alloy covered with a thick film with an oxide film formed on the surface. 2. The semiconductor device according to claim 1, wherein the plating film is made of Sn-Ni alloy and copper.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP64000330A JPH02181463A (en) | 1989-01-06 | 1989-01-06 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP64000330A JPH02181463A (en) | 1989-01-06 | 1989-01-06 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02181463A true JPH02181463A (en) | 1990-07-16 |
Family
ID=11470889
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP64000330A Pending JPH02181463A (en) | 1989-01-06 | 1989-01-06 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02181463A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08167686A (en) * | 1994-07-02 | 1996-06-25 | Anam Ind Co Inc | Manufacture of electronic-device package |
| US5698899A (en) * | 1995-11-30 | 1997-12-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with first and second sealing resins |
| US5937279A (en) * | 1997-04-22 | 1999-08-10 | Kabushiki Kaisha Toshiba | Semiconductor device, and manufacturing method of the same |
| US6828052B2 (en) * | 2000-03-28 | 2004-12-07 | Ceramic Fuel Cells Limited | Surface treated electrically conductive metal element and method of forming same |
-
1989
- 1989-01-06 JP JP64000330A patent/JPH02181463A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08167686A (en) * | 1994-07-02 | 1996-06-25 | Anam Ind Co Inc | Manufacture of electronic-device package |
| US5698899A (en) * | 1995-11-30 | 1997-12-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with first and second sealing resins |
| US5937279A (en) * | 1997-04-22 | 1999-08-10 | Kabushiki Kaisha Toshiba | Semiconductor device, and manufacturing method of the same |
| KR100287414B1 (en) * | 1997-04-22 | 2001-06-01 | 도시바주식회사 | Semiconductor device and manufacturing method of the same |
| US6828052B2 (en) * | 2000-03-28 | 2004-12-07 | Ceramic Fuel Cells Limited | Surface treated electrically conductive metal element and method of forming same |
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