JPH02166651A - Data reproducing device - Google Patents

Abstract

PURPOSE:To stably and highly accurately read a data even at the time of any mode or mode transition by supplying a signal from a capture range control signal generating means to a clock regenerative PLL and controlling a capture range accordingly. CONSTITUTION:The subject device is provided with a bit rate measuring means 620 for a regenerative signal, the clock regenerating PLL (phase locked loop) 200, a PLL capture range control part 650 and a bit rate target value setting means 610, and an operation frequency of the clock regenerative PLL 200 is switched to a bit rate target value corresponding to each operation mode. In addition, a control signal based on a difference between each bit rate target value corresponding to the operation mode and the output data of the bit rate measuring means 620 is supplied to the capture range control part 650, so as to control the capture range of the clock regenerative PLL 200. By this method, even when load variations are large, and the mode transition is under its transition state, a control system can be stabilized while reproducing the data correctly.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a digital data regeneration device using a self-clocking method such as an R-DAT (rotating head type digital audio tape recorder) or a digital fist video tape recorder. In particular, the present invention relates to a data reproducing device that operates stably against bit rate fluctuations during a search and is faster.

2. Description of the Related Art In recent years, digital recording technology has been applied to many fields such as audio and video, and technologies such as R-DAT and digital VTR are being established. Among these, in addition to basic recording and reproducing technology, high-speed search technology that reads address information, control information, etc. while winding and moving the tape at high speed has become important.

Here, as a background technology, a general explanation of R-DAT will be given. Tracks recorded diagonally on the tape by the rotating head of the R-DAT include positive azimuth tracks and negative azimuth tracks. One track is composed of three data areas: a sub data area 1, a main data area, and a sub data area 2, and an ATF area 1.2 in which an ATF signal used for tracking servo is recorded. Sub data area 1
．． 2 is an area for recording data mainly used for high-speed searches such as time codes, and each block is divided into eight blocks, and a block address is recorded at a specific location in each block. The main data area is an area where PCM audio data is mainly recorded, and is divided into 128 blocks, and block addresses are recorded at specific locations within the blocks, similar to the sub data area. In each data area, block addresses are recorded at equal intervals.

Data recorded in baseband on a tape medium is reproduced by two heads, a positive azimuth and a negative azimuth, which are placed facing each other on a rotating cylinder. Generally, the diameter of the cylinder is φ301Dm, and the winding angle is 90 degrees.
The rotation speed is 2000 rpm. The reproduced signal is amplified by a head amplifier, and the waveform is equalized by an equalizer to facilitate data extraction. Extracting data requires a clock corresponding to the bit rate of the reproduced signal.

For this purpose, a clock recovery PLL is used. The reproduced data is supplied to a modulation/demodulation section, where it undergoes NRZI-NRZ conversion, 8-10 inverse conversion, and deinterleap, and then is stored in RAM. Thereafter, error correction and error detection are performed by the code processing processor, the signal is supplied to the D/A converter via the PCM control section, and is taken out to the outside as an analog signal output.

During normal reproduction, all data is extracted by keeping the tape running speed and cylinder speed constant and tracing the recorded track to reproduce a clock at a constant bit rate.

During a search, the tape is run at several hundred times the speed of normal playback. If the cylinder speed is increased several hundred times, it will be possible to trace the recorded track, but this will also increase the bit rate several hundred times, which will limit the speed of the reading circuit. Furthermore, the limit for the processing processor to complete its operations within a predetermined time is far exceeded, and data cannot be reproduced after all. When searching, it is not necessary to extract all data; it is sufficient to extract only the search control data. Therefore, it is possible to partially read out data on a diagonally recorded track without changing the cylinder speed extremely significantly from that during normal reproduction. In this way, in R-DAT, the bit rate of the signal reproduced during search is made to be almost the same as during normal reproduction. In other words, although it means crossing the track diagonally, by keeping the relative speed of the head almost constant.

It becomes possible to keep the bit rate almost constant.

Problems to be Solved by the Invention By the way, during a search, the relative speed of the head changes depending on the tape running speed and the cylinder speed, so the first problem is to suppress these fluctuations.

Techniques for solving this problem have been previously disclosed. As a conventional example, Japanese Unexamined Patent Publication No. Sho E12-121951 can be mentioned. The purpose of this technology is to improve reproduction reading ability during high-speed searches. To this end, efforts are being made to achieve mechanical control that keeps the playback bit rate constant and larger than usual. In this technology, the control signal changes the clock of the regenerative PLL by F/V (frequency/
The voltage is determined by comparing the converted voltage with a preset reference voltage. The control signal thus obtained is fed back to the cylinder speed servo in an attempt to keep the bit rate almost constant. The problem with this technique lies in the method of generating the control signal, and the reliability of the control signal is low. R-D
AT has two heads arranged opposite each other on a cylinder,
Wrap the tape at a wrap angle of 90DEG and run. Therefore, even if the signals read from the two heads are added together, the result is only intermittent data with a duty ratio of 1:1. Therefore, noise may be mixed in when data is missing, that is, when the tape and head are not in contact with each other, and the noise often causes the clock recovery PLL to make unnecessary responses. It is undesirable to use the output of the lock regeneration PLL as a control signal because of low reliability.

Further, the use of an F/V conversion circuit has problems with stability such as changes over time and variations due to analog processing.

Next, the second problem is that the PLL cab challenge is wide in order to allow and follow bit rate fluctuations to some extent.

As a conventional example, a technique has been disclosed in which when a PLL becomes unlocked, this is detected and the range of the PLL is displaced according to the amount of disengagement to follow the shift. (
(For example, Japanese Patent Application Laid-Open No. 61-45451) This technology is a method that counts known data using a regenerated clock, and can generate a control signal according to the amount of lock only when the PLL is out of lock. be.

The first problem with this method is that the shift occurs only when the clock recovery PLL loses lock, so data reproduction is interrupted until it is corrected and re-locked.

The second problem with this technique is that, for the same reason, when the lock is within the lock range, it is impossible to know the margin to the limit, so it is impossible to prevent the lock from becoming unlocked.

Moreover, the third problem with this technique is that the reliability of detection is insufficient and confirmation thereof is not possible.

Furthermore, since data is intermittent during a search, there is a third problem related to tape speed.

In R-DAT, search data such as program number data and address data are recorded on the same track as the main data. As mentioned above, when searching, the track is diagonally crossed. The speed at which the track is traversed (hereinafter referred to as traverse speed) depends on the tape speed and is generally proportional. In the data reproduction process during traverse, on-track and off-track are alternately repeated. The data that can be read is
Only during on-track time. In other words, data can be reproduced only for a time length that is inversely proportional to the traverse speed. It is at least necessary that system-specific data required for search control appear in chunks within this on-track time length.

From these facts, it becomes clear in principle that it is advantageous to increase the time density of data in order to raise the limit of the tape speed during search.

In view of the above problems, it is an object of the present invention to provide a data reproducing device that can read data stably and with high accuracy in any mode or mode transition.

Means for Solving the Problems In order to solve the above problems, the data reproducing device of the present invention includes:
A clock recovery PLL that extracts a clock from the reproduced signal, a PLL capture range control section, and a means for setting a bit rate target value, each of which corresponds to the operation mode. A clock for extracting a clock from the reproduced signal by switching the operating frequency of the clock regenerating PLL, and generating a control signal based on the difference between each bit rate target value corresponding to the operation mode and the output data of the bit rate measuring means of the reproduced signal. The clock is configured to be supplied to a capture range control section of the clock reproduction PLL to control the capture range of the clock reproduction PLL.

Preferably, the apparatus further includes means for correcting the bit rate.

According to the above-described configuration, the present invention is provided with a plurality of bit rate target value setting sections for search and normal playback in order to increase the bit rate and operate, and a control signal detection section receives a reference value from the bit rate target value setting section. Alternatively, it is applied to the capture range control unit to generate a control signal based on the difference with the reproduction bit rate in each mode. In addition, the mode range switching booter PL from the bit rate target value setting section
Supplied to L to perform global range setting. In parallel with this, a control signal based on the difference with the reproduction bit rate is applied from the capture range control section to the PLL to shift the capture range.

As a result, in each mode, the effective capture range of the clock recovery PLL can be made wider than the capture range of the PLL alone for the amount of deviation in the playback bit rate. By applying this to the control unit, it is possible to reduce the fluctuations in the playback bit rate itself.

This allows the clock recovery PLL to compensate for the bit rate fluctuations of the reproduced data in any mode or during mode transitions.
It is possible to suppress and keep it within the capture range of . These two effects work in conjunction with each other. In other words, the method of configuring the feedback control loop of the system including the mechanism and the method of expanding the dynamic range of the control signal extractor, which is a component of the control signal, that is, the playback bit rate deviation measurement section, complement each other. It has an effect. Due to this interaction, it becomes possible to measure the amount of bit rate deviation while maintaining the locked state of the Kurotsuta playback PLL and correct it to minimize the bit rate deviation, so the mechanism load fluctuation is large. This has the great effect of stabilizing the control system while correctly reproducing data even during transient states of time and mode transitions.

Furthermore, in order to obtain a control signal, the present invention uses - of the reproduced data.
By measuring the period of a block of blocks using a reference clock, it is possible to know the absolute value of the deviation from the target value. Furthermore, since the reproduced data is used to extract the period, it is guaranteed that the obtained measurement data is definitely from the data period. Furthermore, by performing error detection, the reliability of the measurement data can be further increased. It is also possible to use only measurement data when reliability is high as control information, and to retain and use previously obtained data when reliability is low. Furthermore, if a low reliability state continues for a long time, protection can be provided using a preset default value.

In this way, by knowing the bit rate of the reproduced signal with high reliability and using it as an accurate control signal, data during high-speed searches can be stored in a highly accurate and stable manner even when the mechanism load fluctuation is large or during mode transition transient states. Since control is possible, it is possible to realize a data reproducing device that can always read data stably.

Embodiments Hereinafter, embodiments of the data reproducing apparatus of the present invention will be described with reference to the drawings. FIG. 5 is a system block diagram showing the entire R-DAT (rotary head type digital audio tape recorder) suitable for realizing the data reproducing apparatus of the present invention. FIG. 6 is a diagram showing the relationship between the tape and head of R-DAT. 5 and 6, 100a and 100b are recording/reproducing heads with azimuth angles of +20 degrees and -20 degrees, respectively;
1 is a cylinder.

102 is a magnetic tape, 103a and 103b are tape 1
107 is a capstan that runs the tape at a constant speed during playback, 104 is a cassette that stores the magnetic tape, 105 is a head writing amplifier for recording and playback, 106 is an equalizer that equalizes the waveform of the playback signal, 20
0 is the reproduction clock PC for punching out from the reproduction signal
P L L (Phase Looke) to extract K
d Loop) circuit 600 demodulates the reproduced signal and
109 is a code processing processor for error detection, correction, and generation of error correction codes; 11O is a RAM unit for storing modulation/demodulation data, PCM data, etc.; 111 is reproduction PCM data. Summer 12 is an A/D converter, Summer 13 is a D/A converter, 114 is a cylinder synchronization signal to be supplied to the servo block, and various basic clocks to be supplied to other blocks. timing generator, 30G
is cylinder IO! , reels 103a, 103b, and capstan 107.

Reference numeral 400 is a system control unit that controls the overall operation of the system, such as the mode of the system.

Here, the signal flow and processing details during recording will be explained. When the system control unit 400 instructs the recording mode, the audio manual AIN controls the A/D converter 112.
The data is input to 16-bit PCM data and converted into 16-bit PCM data. This PCM data is input to the PCM control section III and sent to the RAM section 0 as 8-bit motion data to be saved. At this time, apply interleaving. Code processing processor 1 (1B is R
An error correction code is added to the PCM data saved in the AM section 110 to generate pre-modulation data, and the data is stored in the RAM section +10
Save to.

Thereafter, the modulation/demodulation section 600 performs modulation processing while reading the modulated data from the RAM section 110 at a predetermined timing, and generates the recording signal RFOUT. Recording signal RFOU
T is connected to the head 100a through the head amplifier 105,
100b. On the other hand, servo block 300
controls the rotation of the cylinder 101 based on the cylinder synchronization signal R3CP generated by the timing generator 114, and aligns the phase of the head touch section with the recording signal RFOUT. It also generates a signal HSW for head switching. This H8W is used to switch between the positive azimuth head and the negative azimuth head to which the recording current is applied. In this way, signals are recorded on tape. FIG. 7 shows the format of the recorded data.

Next, the signal flow and processing details during reproduction will be explained. When the system control unit 400 instructs the playback mode, the servo block 300 operates based on R3CP.
The rotational phase of the cylinder 101 is controlled so that the head touch period and demodulation timing can be synchronized. In addition, the tracking signal ATF (Auto
matic Track Flnding) is used to control the tape speed so that the head traces the track. The head signals RFSG reproduced from the heads 200a and 100b are supplied to the equalizer IOH through the head amplifier 105 for waveform equalization, and the signal RFSG is
It is supplied to the modulation/demodulation section 600 as N. At the same time, RFI
Supply N to P L L 200 to generate the regenerated clock PCK.
is extracted and supplied to the modulation/demodulation section 600. Modulation/demodulation section 600
writes the demodulated data into the RAM section 11 (l).

Furthermore, the code processing processor 109 reads demodulated data from the RAM section 110 and performs error detection and error correction. The PCM control unit reads the corrected 8-bit data from the RAM unit 110, deinterleaves it, and stores it as 1ll.
It is supplied to the D/A converter 113 as i-bit data. Furthermore, interpolation processing is performed on data determined by the code processing processor 109 to be uncorrectable. The D/A converter 113 converts the PCM data into an audio signal Aout and outputs it.

Finally, the signal flow and processing details during a search, which are particularly relevant to the present invention, will be explained. During a search, the servo Φ block 300 runs the tape at a high speed several hundred times faster than normal playback in response to a command from the system control unit 400. When searching, it is not necessary to extract all data; it is sufficient to extract only the search control data in the sub-data area.

According to the search control data, the system control unit 400 controls the mechanism and shifts to playback operation and the like. As shown in Figure 7, the sub data area is divided into sub data area 1 and sub data area 2, each consisting of eight blocks. FIG. 8 is a diagram showing a format that defines the logical structure of one block, and both the main data area and sub data area have the same structure. Among these, 5YNC is data for synchronization that separates blocks and starts at the beginning, Wl, W2. P forms even parity. P is parity.

The contents of the ID data Wl, W2 and the data contents are different between the sub data area and the main data area, and the search control data is included in the sub ID of the word WLW2 of the even-numbered block. 5-ID, which is control data for starting the program, is specified in the format so that continuous recording is performed for 9 seconds in the normal recording/playback time.

In order to reliably read the 5-ID defined in this way, it is necessary to satisfy the following two conditions.

The first condition for reliably reading 5-ID is that the head 100a or head 100b traces this 9-second continuous recording section at least once on the tape. As shown in Figure 9, since both sub data area 1 (SUBI) and sub data area 2 (SUB2) are traced in half a cylinder rotation, the time it takes for the green part of 5-ID to pass is longer than that time. It has to be long.

Now, if the rotation period of the cylinder is Trot, the tape speed during normal recording and reproduction is Vt, and the tape speed during search is n·Vt, the following relational expression is obtained.

Trot/2 ≦ 9 * Vt/(Inl・Vt)
Organizing this, lnl ≦ 18/Trot If the rotational speed of the cylinder is Cys (rpm), then Tr
Since ot = 60/Cys, by substituting this, Inl ≦ 0. 3*Cys...
(1) is required.

This is the first condition for reliably reading the 5-ID.

The second condition for reliably reading 5-ID- is that it is necessary to reliably read two or more blocks out of the block length of the - chunk of reproduced data. 2
The block is necessary because the 5-ID is recorded only in even-numbered blocks. FIG. 10 shows the head trajectory on the tape and the envelope of the reproduced signal during a search. In the figure, the amplitude of the envelope is small because the head is traveling on a track with an azimuth opposite to that of the head. Further, the reason why the envelope is hexagonal is because the head width is larger than the track. Thus - the length that can be reproduced as a block of mass increases in proportion to the head speed, that is, the cylinder speed,
The higher the tape speed during the search, the shorter it becomes.

Now, assuming that the bit rate of the reproduced signal is 13rs, the block length Bl of the reproduced data is expressed as follows.

B 1 = (B rs/3 [i0 house a end (V t*
3G/1000)/(I n @ Vt-Vt1
) = Brs*α/(I n-1112000) where α is the ratio of the portion of the envelope from which valid data can be obtained, and experiments have shown that α=0. (A value of 37 was obtained.

Also, by substituting the condition Bl≧2 for the block length Bl of a block of reproduced data to be 2 blocks or more, the equation is rearranged to obtain In-1t≦2. 8* 10-' *Brs・
...(2) is required.

Equation (2) is the second condition for reliably reading 5-ID.

Here, an expression representing the relationship between the bit rate Br of the reproduced signal at the time of search, the tape speed, and the cylinder speed is determined. 11th
The figure shows the relative moving speed of the tape and cylinder. In FIG. 11, vt: tape speed during normal recording and playback, v ho: cylinder speed during normal recording and playback,
Vrl: Composite vector during normal recording and playback, θ0: Inclination angle of cylinder installation (still angle), θ1: Angle of composite vector during normal recording and playback (track angle), nVt: Tape speed during search, VhOs: cylinder speed during search, Vrls: resultant vector during search, θls: angle of resultant vector during search, Vr2s: track angle component of vector Vrls, θ2S: angle of difference between angle θIs and track angle θ1. be.

From FIG. 11, the following equation can be obtained.

a = n Vt-Vt*VhO8/VhOb"a*c
osθI Vr2s = Vrl* VhOs/VhO-bIf you organize these, Vr2s = Vrl* VhOs/VhO-cosθ
1*Vt*(n-VhOs/VhO).

Here, if the bit rate and cylinder speed during normal recording and playback are Br and Cy, and the bit rate and cylinder speed during search are Brs and Cys, then B r
s/ B r= V r2s/V rlCys/ Cy
= V hOs/V hO, so substitute this and rearrange to get Brs/Br= Cys/Cy-cosθi*vt*
(n −Cys/Cy)/Vrl=Cys/Cy terminal (1+cosθ1*Vt/Vrl)−n*cosθ1*
Vt/Vrl Here, the general constants of R-DAT Vt = 8.15 nm/5 vho = 3.133 m/5 Vrl = 3.125 mis θ0 = 8.3G87 deg θ1: fi, 3822 deg Br = 9 Substitute .408 Mbps Cy = 2000 rpm and get Brs/Br:Cys/Cy*1.0025B-n 0
．． 00259・(3) is obtained.

Equation (3) expresses the relationship between tape speed and cylinder speed when the bit rate during search is constant. FIG. 12 is a diagram showing the relationship between tape speed and cylinder speed when the bit rate at the time of search is constant, based on equation (3). In FIG. 12, the horizontal axis represents the tape speed n V tl and the vertical axis represents the cylinder speed Cy. Note that the direction in which the tape speed nVt is positive is FF (fast forward) mode, and the direction in which the tape speed nVt is negative is REV.
(rewind) mode. This figure shows the general property that in order to keep the bit rate constant, the cylinder speed should be increased when the tape speed is positive, i.e., a fast forward search, and the cylinder speed must be decreased when the tape speed is negative, i.e., a rewind search. .

From the two conditional expressions found so far and equation (3), 5-I
The conditions for reliably reading D and the relationship among bit rate, tape speed, and cylinder speed have all been clarified. The summary is as follows.

Inl≦0. 3*Cys (1
)In-Ll≦2. 8*10-' *Brs
(2) Brs/Br=Cys/CyJ, 00259-n
1, 00259 (3) FIG. 13 comprehensively illustrates these relationships. In FIG. 13, the horizontal axis represents the tape speed nVt1, and the vertical axis represents the bit rate Brs. The dashed-dotted line A in the figure is a line showing the boundary of the area satisfying the condition of equation (1), and the dashed-double line B is the line showing the boundary of the area satisfying the condition of equation (2). Also, lines C1 and C2°C in the figure
3, C4 is cylinder speed Cy +ooorpm respectively
, 200Orpm, 3000rpm, and 4000ppm are constant. Here, equation (1) and (
2) The area that satisfies the condition of the equation is shown by a solid line, and the rest is shown by a dotted line.

What can be learned from this diagram is that in order to reliably read the 5-ID, the cylinder speed must be particularly increased during a fast-forward search to increase the bit rate, and when performing a rewind search, the cylinder speed must be decreased to reduce the bit rate. This means that it needs to be held high. And importantly, the tape speed limit depends on the bit rate.

For example, the bit rate Br is 9.4, which is the same as during normal playback.
The range of tape speeds that can be read at 08Mbps is -2
40 to +280, while the bit rate Br is 1
．． When increasing the speed five times to 14.112 Mbps, the readable tape speed range expands to -350 to +420.

Therefore, it can be seen that it is advantageous to increase the bit rate when searching because the reading performance limit increases. In order to realize this, it is necessary to have means for changing the frequency characteristics of the equalizer 106 and the PLL 200 in accordance with the bit rate. However, the waveform equalization characteristics of the equalizer 106 and the P L L 200
It is difficult to realize a circuit that continuously changes the capture range of , and even if it were realized, it would be expensive. Therefore, it is practical to set at least two or more bit rate target values, roughly switch the frequency responses of the equalizer 106 and the PLL 200, and operate in these two discrete regions, and this embodiment also uses this method. We are hiring.

More specifically, first of all, in order to set the bit rate during search higher than during normal recording and playback, a bit rate target value setting section is provided, and a mechanism is created so that the playback bit rate during search is close to the target value. This is a method of controlling

This control is accomplished by servo block 300 controlling tape speed and cylinder speed. Note that this control system may be an open loop or a local feedback loop, but most preferably a feedback loop that detects the bit rate and determines the error from the target value to control the mechanism. That is to say. These allow bit rate fluctuations to be suppressed to a certain extent in each area.

Also, in conjunction with this, equalizer 10G and PLL2
It is essential to switch the frequency response of 00.
Preferably, at least these endogeneities, the PLL 200 is a feedback loop that detects the bit rate, determines the error from the target value, and controls the capture range. This allows the effective capture range of the clock recovery PLL to be wider than the capture range of the PLL alone with respect to deviations in the reproduction bit rate in each mode. In this way, in any mode or mode transition, fluctuations in the bit rate of reproduced data are suppressed, and the capture range of the clock recovery PLL is effectively expanded to stabilize data reading.

A first embodiment of the present invention will now be described with reference to FIG.

In FIG. 1, the same parts as in FIG. 5 are uniformly numbered. The different parts are as follows. Special means are added to the block of the modulation/demodulation section 600. 82
0 is a bit rate detection section, 650 is a capture range control section, and 610 is a bit rate target value setting section. In addition, special functions have been added to the PLL 200 as well.

An input terminal for an external control signal is added to shift the capture range over a wide range, and an input terminal for an external control signal is added to shift the capture range over a narrow range. Also, the servo block 300 is shown in more detail, and the servo block 300 is shown in more detail.
1 is a tape speed control section, 302 is a cylinder servo control section, 303 is a cylinder driver, 304 is a reel servo control section, and 305 is a reel driver.

Next, a detailed configuration of modulation/demodulation section 600 will be explained.

FIG. 3 is a block diagram showing the configuration of modulation/demodulation section 600. In FIG. 3, IEOI is an NRZ I inverse converter that converts the NRZI-modulated playback signal RFIN into an NRZ signal, G07 is a 5YNC pattern detector that extracts the block synchronization signal 5YNC from the NRZ signal, and 604 is a playback timing generator. DSYN provides initialization timing for
At the same time as transmitting C, other signals are deformed and erroneous 5Y
This is a gate for blocking DSYNC when NC is detected. 6011i determines the detection status of 5YNC and DS
This is a synchronization protection unit that performs YNC gate control. The synchronization protection unit 60B outputs a 5YNC continuous flag 5YCNT when two consecutive blocks of valid 5YNC are detected.

602 is an S/P converter that performs serial/parallel conversion of the NR2 signal using the word clock WDCK generated by the reproduction timing generator, and 803 is an S/P converted 1
This is an 8-IO decoder that converts 0-bit data to 8-bit φ data and sets an RF error flag RFF for data that does not meet the 8-IO modulation rules.

605 is a synchronization protection unit Ei04. Initialize with the synchronization detection flag DSYNC sent from BOG, and use the reproduced clock PC
This is a reproduction timing generation section that generates timing for demodulation processing using K as a time reference. In addition, the reproduction timing generating section 6θ5 is the S/P conversion clock WDCK, and the RAM section 1
In addition to the playback word address PWAD for writing demodulated data to 10, the RAM write request signal WRRAM, the synchronization protection unit [i04, the 5YNC window SMASK used in GOe, etc., the signal TSYNC corresponding to the period in which 5YNC is detected, that is, the block period. occurs.

608 is the 3 words following block 5YNC, Wl.

W2. This is an ID data latch that latches data of P. 609 is Wl, W2. Performs a parity check on P,
RF flag RF supplied from 8-10 decoder 603
F=O (no error) and parity check OK
This is the parity check section that sets the parity OK flag PRF only when . The parity check section 609 outputs a parity continuous flag CPRF indicating that the parity OK flag PRF is successively OK. G14 is a crystal oscillator that generates a frequency that is the basis of the system's reference timing, and 615 is a crystal oscillator that drives the crystal oscillator Ei14 to oscillate, and also a clock FCH that corresponds to the bit rate during normal recording and playback and a clock FCH that is twice this. periodic clock HF
This is a reference timing generator that generates various timings including CH. Reference numeral 620 uses TSYNC from the playback timing generator 605 as a reference timing generator G15.
The count data PSYI is counted using the reference clock HFCH of
This is a block period measuring section that outputs V. 610 stores data PLOTR from the system control unit 400;
This is a target bit rate setting unit that sets a target bit rate according to LL mode data PLLMD. 851 is P
This is a subtracter that subtracts PLOTR from SYIV. 65
3 is a PWM pattern converter which inputs the output data of the subtracter G51 and converts it into a PWM pattern. 654 is PW
This is a P/S converter that serializes the parallel data of the M pattern converter 653, and outputs this signal to the PLL capture range control signal PL through the output interface section 896.
Output as L0FS. 652 is a table converter that outputs a flag for determining the reliability of measurement data from the range of output data of the subtracter 651. 855 is an AND gate, and a flag VFPLFS indicating the validity of PLL0FS from the result of the table converter 652 and the condition of PSYVF.
This is an AND gate that outputs .

The operation at the time of search in the data reproducing apparatus configured as described above will be explained below. During the search, the envelope of the reproduced signal becomes hexagonal, as shown in FIG. 10, and a noise bar is generated in which the envelope reaches almost zero. This situation is shown in FIG. In Figure 14, 5YNC can be detected within a range where the amplitude of the envelope is sufficient.
Errors are particularly likely to occur at the noise bar, so effective 5Y
In addition to the NC, other data is transformed to create an apparent 5YNC pattern. This spurious 5Y
I'll call it NC. Spurious 5YNC is an SM generated by the reproduction timing generation section 605 and the synchronization protection section 606.
Since it is gated with ASK and excluded, synchronization will not be disrupted. Only the 5YNC that is input at the correct period is taken out and playback synchronization is determined. At this time, the reproduction timing generator 605 generates a signal TSY corresponding to a period of 5YNC.
NC is output, and at the same time, a flag 5YCNT indicating that 5YNC has been correctly input consecutively is output. These are supplied to the block period measuring section G20.

The block period measuring section 620 is a reference timing generating section 61
The TSYNC period is counted using the HFCH output from 5. This count result data PSYIV is data representing the block period at the time of search, and is inversely proportional to the bit rate, so that the bit rate at the time of search can be determined. PSYIV is taken out to the system control unit 400 through the output interface unit 694. PSYIV is also supplied to the positive input terminal of subtracter G51. PLO input from system control unit 400
Once TR is stored in the target bit rate setting unit GIO, P
PLOT at the time of search selected according to LLMD data
R is supplied to the negative input terminal of subtracter 651. Subtractor 6
The output 51 is data of the difference between the actually measured PSYIV and the target value PLOTR. The output of the subtracter 651 is table-converted to convert it into PWM by a PWM pattern converter 653, and is supplied to a P/S converter 654. P/S converter 6
54 converts the parallel data into serial data and outputs it as a PLL capture range control signal PLL0FS through an output interface section 636. Furthermore, the validity of the range of the output of the subtracter 651 is determined by a table converter 652, and a flag is output to the AND gate B55. A
The ND gate 655 further includes a block period measuring section 620.
The output VFPLFS is output only when both of them satisfy the conditions. At the same time, the output interface unit fi911i is controlled by VFPLFS, and when the conditions are not met, the output PLL0FS is set to Hi.
-Z (high impedance). The signals and data auxiliary output from the modulation/demodulation unit Gl)0 for search control are the above PSYIV, PLL0FS, PSYVF, V
There is FPLFS.

PLL0FS output from the modulation/demodulation section 600 and PLLMD output from the system control section 400 are PLL20.
Supply to 0. The PLL 200 has an input terminal for an external control signal to shift the capture range in a wide range, and an input terminal for an external control signal to shift the capture range in a narrow range.

A specific example of the PLL 200 is shown in FIG.

In Fig. 4, 201 is a buffer, 202 and 203 are delay lines, 204 is a switch, and 205 and 208 are E
XOR (exclusive OR), 208 is analog switch, 212 is operation cod null amplifier, 214 is V
CO (voltage controlled frequency oscillator), 218 is a trimmer capacitor, 222 is a varactor diode, 224 is a buffer, 207.211.213.215.218.2
21.223.225 is a resistor, 209.210, 21
7, 219, 220, 226 are capacitors.

The operation of the PLL 200 will be explained below.

The output signal RFIN of the equalizer 106 is P L L 2
00, buffer 20! It is supplied internally through.

This signal is transferred to the delay line 202 and the delay line 20.
3 delay delay, EX OR2O5 supply. EXO
The other input of R205 directly inputs RFIN.

The EXOR 205 outputs a pulse of a certain length starting from the rise edge and down edge of RFIN. This time length is determined by the delay time of the delay line. During a search, the switch 204 is switched to the 1 side, and during normal playback, it is switched to the 2 side. This fixed time length pulse and V CO
The output signal PCK of the EXOR 214 is supplied to the EXOR 20G, and a pulse waveform whose duty ratio changes according to the phase difference between the output cover RFIN and PCK of the EXOR 2011i is output. The analog switch 208 transmits only the effective edge part of the pulse as a phase difference signal, and leaves the rest open to hold the charges charged in the capacitors 209 and 210, thereby improving the gain characteristics of phase detection and making it stable. It is used for the purpose of operation. Phase detection output is resistor 20f, 211 and capacitor 20i9, 21
The signal is supplied to the operational coronal amplifier 212 through a low-pass filter consisting of zero. Operation Cod Naru Amp 2
! 2 works as a voltage follower with high input impedance to enhance charge retention characteristics. This signal is supplied to the frequency control terminal FC of VCO 214.

The output PCK of V CO214 is the phase detection section EXOR20.
It is fed back to G and forms a PLL (phase locked loop). In the PLL configured in this way, the capture range is limited. Even when intentionally designed, the capture range is usually +10% to -10%. Therefore, by changing the operating range of the VCO 214 using another control means, it is possible to operate at different bit rates depending on the mode and to perform shift correction of the capture range.

Specifically, the VCO 214 uses a voltage-controlled multivibrator (manufactured by TI, product number 5N74LS824). The resistor 215...
2111i and supplies it to the range control terminal R of the VCO 214. This greatly changes the operating range of VC0214. Next, PLL0FS input from the modulation/demodulation section 600 is smoothed by a resistor 225 and a capacitor 22B, and is supplied as a bias voltage to the varactor diode 222 through resistors 223 and 221. The junction capacitance of the varactor diode 222 changes depending on this bias voltage.・Junction capacitance of varactor diode 222 1fHt
Conf' +219.22 (1??VcO214)c
It is coupled to the X 1 and CX2 terminals. The oscillation frequency can be controlled by the capacitance of the capacitors connected to the CXI and CX2 terminals.

Capacitor 217 is for damping the range of change. Trimmer capacitor 218 is also for adjustment. Therefore, PLL0FS allows the operating region of VC0214 to be slightly changed, that is, the capture range can be shifted. Equipped with such an operating range control means, the output PCK of the VCO 214 is controlled by the buffer 12.
24 from the PLL 200.

Next, the block period measuring section 620 will be explained in detail. FIG. 15 is a specific circuit diagram of the block period measuring section 620. In FIG. 15, 621 is a binary counter, 622 is a D flip-flop, 623 is a D flip-flop, 624 is an AND gate, 625 is an AND gate, 626 is a shift register, 627 is an S/R latch,
28 is a D flip-flop. FIG. 16 is a diagram showing operational waveforms of the block period measuring section 620 thus constructed.

First, the control part of the block period measuring section 620 will be described.

TS from the reproduction timing generation section 605 of the modulation/demodulation section 600
YNC is supplied to the serial input terminal of the shift register 62B, and HFCH is supplied from the reference timing generation section 615 to the clock terminal of the shift register 626, respectively. Shift register 626 allows TSYNC to be set to HF
Punch out the CH and HFCH as shown in Figure 16.
Outputs delayed outputs QA, QB, and QC for each down edge. AND gate 624 connects QB and QC to /CTR
A timing signal is generated and supplied as a clear signal to the binary counter 621. Binary counter 62! teeth/
It is cleared and reset by CTR, and the output PSYIVO is incremented by counting every rise edge of HFCH.

The output PSYENO of the AND gate 625 is the synchronization protector 6
5YCNT from 06 and parity check part G 096
) and the QA of the shift register 62B, QA is sent to the D flip-flop 62 only when 5YNC is detected continuously and the parity is successively OK.
It is transmitted to the clock terminal of No.2. The rise edge of PSYIVO, that is, the rise timing of QA, precedes /CTR by one clock of HF CI-1, so /C
Count value P one clock before cleared by TR
SYIVI can be stored in D flip-flop 622. If the bit clock during recording is FCH, and the clock whose frequency is doubled by frequency division is HFCH, then the 8th bit clock is HFCH.
As shown in the figure, the block period during normal playback is 3 on FCH.
This corresponds to 60 clocks, or 180 clocks for HFCH. Therefore, the standard count data of PSYIVI is 178 since it is based on 0. H8WEG is an edge pulse extracted from H8W supplied from the servo φ block 300. S/R latch 62
7 is reset by H8WEG, set by PSYENO, and outputs PSYENl. i.e. PSYENI
is a flag indicating whether or not the block period has been counted even once within the time interval divided by H8WEG. In the D flip-flop 623 and the D flip-flop Ei2B, the block period count data PSYIV1
The final data within the time interval delimited by H8WEG of PSYENI and the flag PSYENI indicating its validity are respectively PSYI
Output as V and PSYVF. If the block period is not counted even once within the time interval divided by H8WEG, PSYVF does not become invalid and outputs a logic level L, and PSYIV at this time becomes meaningless.

In this manner, the block period measuring section 620 performs highly reliable block period measurement, and the bit rate can be known with high reliability and flag information can be output together without reducing the reliability.

Next, the circuit for obtaining the signal PLL0FS for controlling the PLL based on the block period measurement data PSYIV obtained by the block period measurement section 620 will be described in the third section.
Return to the diagram and continue the explanation.

$10 is data PLOTR from the system control unit 400
This is a memory that stores PLL mode data PLLMD and sets a target bit rate according to PLL mode data PLLMD.

Target bit rate setting section [ilo stores two P L-OT R data for normal playback and search time,
It is selected by LLMD, outputted, and supplied to subtracter 851.

Ei51 is a subtracter that subtracts PLOTR from PSYIV. Subtractor 65! The output of block period measurement section 62
PSYIV measured at 0 and block period target value PLO
This is the difference from TR. This difference is converted into a PWM pattern converter 65.
Supply to 3. 853 is a PWM pattern converter which inputs the difference PSYIV-PLOTR and converts it into a PWM pattern. The conversion may be table conversion or conversion using logic gates. An example of the conversion is shown in Table 1. Divide the area around the area where the deviation value is close to zero, and divide each area into a representative PWM (Pulse World Modula).
tlon) into pattern data. Also PLLMD
When is 0, that is, during normal playback, a fixed PWM pattern is output and the duty is set to the central value of 50%.

654 is a P/S converter that converts parallel data from the PWM pattern converter 653 into serial data. P/S converter 6
At 54, the serial data, that is, the true PWM signal, is output as PLL0FS through the output interface section 696. 652 is a table converter that outputs a flag for determining the reliability of measurement data from the range of output data of the subtracter G51. If the difference between PSYIV and PLOTR is too large, the measured data is considered to be incorrect, so VFPLFS is set to logic level O to indicate invalid data. This determination corresponds to a case where the difference in Table 1 is too large. Furthermore 655 AN
A flag VFPLF indicating the validity of PLL0FS is determined from the result of the table converter 652 and the condition of PSYVF at the D gate.
Output S. Based on this result, when the reliability of the measurement data is low, vFPLFS is set to L to disable the output interface section 69B, and the output terminal PLL0 is disabled.
FS is set to high impedance.

FIG. 18(a) is a diagram showing the relationship between PSYIV and PLL0FS when searching with PLOTR=120,
FIG. 18(b) is a diagram showing the relationship between PSYIV and PLL0FS when searching with PLOTR: 178.

In this way, a control signal based on the difference between the bit rate measurement during the search and the set target bit rate can be generated with high reliability.

Table 1 These signals are connected to the PLL200 as shown in FIG.
is supplied to As already explained, the PLL 200 has an input terminal for an external control signal to shift the capture range in a wide range, and an input terminal for an external control signal to shift the capture range in a narrow range. FIG. 19 is a diagram showing controlled characteristics of the PLL 200. In Figure 19, the horizontal axis is PLL0F
The average voltage of S is V P L L Op s, and the vertical axis represents the frequency of the P L L capture range. V C depending on the voltage H or voltage according to the logic level 1, 0 of the PLLMD input from the system control unit 400
The operating range of O214 is greatly changed between normal playback and search. Also, PLL0 input from the modulation/demodulation section 600
The operating range of the VCO 214 can be changed by FS.

In other words, the capture range can be optimally shifted in response to a control signal based on the difference between the bit rate measurement and the set target bit rate during normal playback and during search.

FIG. 17 schematically shows a series of these operations.

In FIG. 17, PLOTR=120. Also, the change in PSYIV is 120, 110, 105, or the change in bit rate is approximately 14Mbps, 15Mbps.
bps, 16Mbl)s. At this time, PSYIV-PLOTR is ±O, +
10, +15, and the duty of the PWM pattern becomes 50%, 75%, and 100%.

Note that the portion where PSYIV is X corresponds to a case where a playback signal cannot be obtained due to dropout due to, for example, head dirt. In this case, since the reliability is low, the flag is lowered and PLL0FS is set to Hi-Z. In this way, P L L 200 is supplied, and P L L 20G
This part is held at its previous value in an analog manner, so that even if there is an abnormal input signal, the control of the entire system will not be disrupted. By controlling the capture range of the PLL 200 in this manner, the effective capture range of the clock recovery PLL can be made wider than the capture range of the PLL alone with respect to the deviation amount of the reproduction bit rate in each mode. In this way, in any mode or mode transition, it is possible to always optimally shift the capture range of the clock recovery PLL by following fluctuations in the bit rate of reproduced data.

Preferably, further comprising means for correcting the bit rate, the bit rate is corrected using the control signal based on the difference between each bit rate target value corresponding to the operation mode and the output data of the bit rate measuring means of the reproduced signal. In other words, the bit rate can be corrected by supplying the information to a means for correcting the bit rate. Bit rate correction is performed by controlling a mechanism. From equation (3), it can be seen that it is sufficient to adjust the cylinder speed or tape speed. Here, a method for correcting the bit rate by controlling the tape speed will be explained. During a search, it is difficult to use a capstan to run the tape in a constant manner as during normal playback. The tape is released from the capstan 1 and the tape is run regardless of the rotation of the capstan, so the tape speed is controlled by the reel rotation speed. As shown in Figure 20, since the winding radius of the supply reel and take-up reel changes, the tape speed is determined by the sum of the rotation periods of each reel, and the reel rotation speed is controlled so that this sum of periods remains constant. Then, the tape speed can be kept almost constant. FIG. 21 is a diagram showing the relationship between tape position and tape speed. (b) in the figure shows the characteristics when the coefficient is set so that the tape speed is 200*Vt at the central tape position and the period sum is controlled to be constant, and (C).

(a) shows the characteristics when an offset is given to the coefficients.

Fine adjustment of the tape speed, that is, correction of the bit rate, is performed by adding an offset to the period sum control coefficient. In FIG. 1, the modulation/demodulation section 600 has a rough lock period f' - PsY IV, ! :PSYVF is supplied to the tape speed control section 301 and an offset is added to the coefficient of period sum control of the reel servo control section 304. In such a configuration, the correction operation is performed as follows, for example. tape speed 2
In the fast forward search of 00*Vt, if the current target bit rate is shifted to a higher side, then PSY
A value smaller than the target value is measured for IV. Therefore, the tape speed control unit 301 controls the reel driver 305 to further increase the tape speed. As is clear from FIG. 13, as the tape speed increases, the bit rate decreases, so that the bit rate approaches the target value. The series of operations is repeated with feedback until the bit rate matches the target value.

In the search start operation, as shown in FIG. 22, the tape speed is gradually accelerated in steps. This is to reduce transient fluctuations in the bit rate when switching the tape speed and cylinder speed at the same time. The transient state at this time is shown in Figure 23. The bit rate is 14.112M which is 1.5 times that during normal playback. b I) Increase the cylinder speed to 300° rpm in advance to perform a search operation at S. From then on, 25V t and 50V t.

Increase the tape speed to 200Vt. As a result of correcting the bit rate by finely adjusting the tape speed in this manner, it is possible to suppress the bit rate to a constant deviation even during a transient change in tape speed or during a 200 times high speed search. FIG. 24 shows data of experimental results according to an example of the present invention. Since the bit rate deviation is suppressed to a range of +4% to -3%, the shift of the capture range of the clock recovery PLL is at most +2% to -2%. Therefore, by effectively utilizing the shift in the capture range of the clock reproduction PLL, it is possible to increase the speed of the tape in a rougher and faster step, and it is also possible to easily increase the maximum tape speed.

More preferably, a control signal based on the difference between each bit rate target value corresponding to the operation mode and the output data of the reproduced signal bit rate measuring means is supplied to the cylinder servo control section to correct the bit rate. It is necessary to configure it as follows. A second embodiment constructed in this manner is shown in FIG.

2 differs from FIG. 1 in that PLL0FS output from the capture range control section 650 is supplied to the cylinder servo control section 302. Similarly, the tape speed is controlled so that the sum of the reel rotation periods is kept constant. As shown in FIG. 2, PLL0FS output from the capture range control section 850 is supplied to the cylinder servo control section 302 to finely adjust the rotational speed of the cylinder and correct the bit rate. In such a configuration, the correction operation is performed as follows, for example. In a fast-forward search at a tape speed of 200*Vt, if the current bit rate is shifting higher than the target bit rate, PSYIV is measured to be smaller than the target value, and the capture range control unit 650
The duty of PLL0FS output from the PLL0FS becomes higher than 50%. This PLL0FS is supplied to the PLL 200 to expand the effective capture range, and is also supplied to the cylinder servo control section 302 to control the cylinder driver 303 to reduce the cylinder speed. As is clear from FIG. 13, when the cylinder speed is reduced, the bit rate decreases, so the bit rate operates closer to the target value. The series of operations is repeated with feedback until the bit rate matches the target value. The search start operation is the second
This can be done in the same way as in Figure 2. This is because the cylinder servo control response is generally faster than the tape speed control response. Even if there is a delay in tape speed control,
Since the cylinder speed, which responds quickly, is controlled to bring the final bit rate closer to the target, there is less deviation in interlocking control between the tape speed and cylinder speed during transitions. Therefore, the bit rate deviation can be further suppressed, and by effectively utilizing the shift in the capture range of the clock recovery PLL, the tape speed increase step can be made coarser and faster, and the maximum tape speed can be further increased. It will also become easier to do.

Effects of the Invention As described above, the data reproducing device of the present invention allows the effective capture range of the clock regeneration PLL to be larger than the capture range of the PLL alone with respect to the deviation amount of the reproduction bit rate in each of the normal reproduction and search modes. The first effect is that the playback bit rate can be made wider, and the second effect is that the variation in the playback bit rate itself can be reduced by providing control information based on the difference between the playback bit rate to the mechanism control unit. These two effects work in conjunction with each other. In other words, two methods complement each other: a method for configuring a feedback control loop for a system that includes a mechanism, and a method for expanding the dynamic range of the control signal extraction section, which is a component of the control signal, that is, the playback bit rate deviation measurement section. This interaction makes it possible to measure the amount of bit rate deviation while maintaining the locked state of the clock recovery PLL, and to correct the bit rate deviation to minimize it. Therefore, even when the mechanism load fluctuation is large or when the mode transition is in a transient state, the control system can be stabilized while correctly reproducing data, which is a great effect.

Furthermore, in order to obtain a control signal, the present invention uses - of the reproduced data.
By measuring the period of a block block using a reference clock, the absolute value of the deviation from the target value can be determined.Also, since the reproduced data is used to extract the period, the obtained measured data is unmistakably the existence of data. Guaranteed to be valid for a period of time.

Moreover, since error detection is performed, the reliability of the measurement data can be confirmed, and only the measurement data when the reliability is high is adopted as control information, and when the reliability is low, the previously obtained data can be retained and used. You can also do it. Additionally, if a low-reliability attack continues for a long time, protection can be provided using a preset default value.

In this way, by knowing the bit rate of the reproduced signal with high reliability and using it as an accurate control signal, the data during high-speed search can be kept highly accurate and stable even when there are large mechanical load fluctuations or during mode transition transients. Since the control is possible, it is possible to realize a data reproducing device that can always read data stably.

The present invention is applicable not only to R-DATs, but also to all devices that reproduce digital data, such as devices such as digital video recorders and compact discs, and streaming devices for data storage.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main parts of the configuration of a data reproducing device according to a first embodiment of the present invention, and FIG.
FIG. 3 is a block diagram showing the main part of the configuration of the data reproducing apparatus in the embodiment of the invention. FIG. 4 is a block diagram showing the configuration of the modulation/demodulation section in the second embodiment. A circuit diagram showing the configuration of the PLL in the second embodiment, FIG. 5 is a system block diagram (prior art) showing the entire R-DAT suitable for realizing the data reproducing device of the present invention, and FIG. A diagram showing the relationship between the tape and the head of R-DAT, FIG. 7 is a diagram showing the format of recording data recorded on the tape, and FIG. 8 is a diagram showing the format that defines the logical structure of one block. Fig. 9 is a diagram showing the 5-ID recording section on the tape and the timing at which the head traces this 5-ID recording section, and Fig. 10 is a diagram showing the head trajectory on the tape and the envelope of the playback signal during search. ,' Fig. 11 is a diagram showing the relative moving speed of the tape and cylinder, and Fig. 12 is a diagram showing the relationship between tape speed and cylinder speed when the bit rate is constant.
Fig. 13 is a diagram showing the conditions for reliably reading 5-ID, the relationship between bit rate, tape speed, and cylinder speed, Fig. 14 is a timing diagram showing 5YNC detection timing during search, and Fig. 16 is A specific circuit diagram of the block period measurement section, Fig. 16 is a diagram showing the operation waveforms and data timing of the block period measurement section, and Fig. 17 schematically shows the series of operations from bit rate measurement to capture range shift. Figure 18(a) shows PLOTR=1
FIG. 18(b) is a diagram showing the relationship between PSYIV and PLL0FS when PLOTR=178,
FIG. 18 is a diagram showing the controlled characteristics of the PLL, FIG. 20 is a diagram showing the winding radius of the supply reel and the take-up reel,
FIG. 21 is a diagram showing the relationship between tape position and tape speed when reel period sum constant control is performed, FIG. 22 is a flowchart showing the tape speed control procedure from the start of search to bit rate correction, and FIG. The figure is a timing diagram showing the relationship between the cylinder speed, tape speed, and bit rate from the start of the search until the tape speed is increased. Figure 24 shows the bit rate deviation data during the search based on the experimental results of the embodiment of the present invention. FIG. 1ota...plus azimuth head, 100b...
Minus azimuth head, 101...Cylinder, 10
2...Tape, IO2...Head amplifier, 106
...Equalizer, 200...PLL, 3
01... Tape speed control unit, 302... Cylinder servo control unit, 303... Cylinder driver, 304...
...Reel servo control section, 305... Reel driver, 400... System control section, 61O... Target bit rate setting section, 620... Block period measurement section, 6
50... Capture range control unit, 606... Synchronization protection unit, 607... SY, NG pattern detection unit, 60
9... Parity check section, 651... Subtractor, 6
52...Table converter, 653...PWM pattern converter, 654...P/S converter, 621...Binary counter, 822,823.828...D
Flip-flop, 626...Shift register, 62
7...S/R latch, RFIN...reproduction signal,
PCK...Regenerated clock, psyrv...Block cycle data, PSYVF...Flag indicating whether block cycle data is valid or invalid, PLOTR...
Target bit rate setting data, PLLMD...P
LL mode data, PLL0FS...PLL capture range control signal. Name of agent: Patent attorney Shigetaka Awano. 2/]) - Large Diagram No. 1'. Fig. □Tefu'Kikanhoukikaishima'Oq ('q' Fig. 16 PS'fEN1 PS'YVF ←-Up-1111 Fig. 17 5WECr ps'(r-Nt (VF/'LFδ)] (PLO Ding R=f20) 5S 18th ■) (b) PLOTL:+20 PLOTL=m 7・.,+7
〕Figure 19 ■pLLoF5 ('/] Nonoshimu6 Ve (η) (hill) Figure 22

Claims (15)

[Claims] (1) A reading means for reading a recording medium and obtaining a reproduced signal, a clock reproducing PLL for extracting a clock from the reproduced signal, a system control means for switching the operating frequency range of the clock reproducing PLL, and a bit for measuring the bit rate of the reproduced signal. A rate measuring means, a bit rate target value setting means for setting a plurality of bit rate target values, and a signal obtained by converting based on data of the difference between the bit rate target value and the output data of the bit rate measuring means. 1. A data reproducing device comprising capture range control signal generating means for controlling a capture range by supplying a signal from the capture range control signal generating means to a clock reproducing PLL. (2) The bit rate measuring means detects regular patterns or words that appear for each series of data lengths, measures the detection period using a known time base, and outputs measurement data. The data reproducing device described. (3) The bit rate measuring means includes a determining means that determines the reliability of the measurement data and outputs a determination signal to the capture range control signal generating means, and the capture range control signal generating means has a predetermined reliability. When the determination signal indicates that the bit rate is within the range of If the determination signal indicates that the bit rate is outside the range, the output data of the bit rate measuring means previously obtained is used instead of the output data of the current bit rate measuring means, and the reliability is within the predetermined range. 2. The data reproducing apparatus according to claim 1, wherein a control signal is generated based on the difference from the bit rate target value using the newest one and is supplied to the clock reproducing PLL. (4) In the determination means for determining the reliability of the measurement data, when the determination signal indicates that the reliability is outside a predetermined range, the capture range control signal generation means determines the reliability of the current bit rate measurement means. Instead of the output data, among the previously obtained output data of the bit rate measuring means, the latest one whose reliability is within a predetermined range is adopted, and a control signal is generated based on the difference from the bit rate target value. is supplied to the clock recovery PLL, and if the reliability of the determination signal continues to be outside a predetermined range, the control signal is generated so as to be changed instantaneously or gradually to a preset default control signal. 4. The data reproducing apparatus according to claim 3, wherein the data reproducing apparatus supplies the clock to the clock reproducing PLL. (5) The bit rate measuring means includes an error detection means for detecting errors using an error detection code included in the data, and a continuous detection of regular patterns or words that appear for each series of data lengths. 2. The method according to claim 1, further comprising: a continuity detection means for detecting the occurrence of an error; and a determination means for determining reliability based on the output of the continuity detection means and the result of error detection of a regular pattern or word. data playback device. (6) A reading means for reading a recording medium and obtaining a reproduced signal, a clock reproduction PLL for extracting a clock from the reproduction signal, a system control means for switching the operating frequency range of the clock reproduction PLL, and a bit for measuring the bit rate of the reproduction signal. A rate measuring means, a bit rate target value setting means for setting a plurality of bit rate target values, and a signal obtained by converting based on data of the difference between the bit rate target value and the output data of the bit rate measuring means. The capture range control signal generation means controls the capture range by supplying the signal from the capture range control signal generation means to the clock reproduction PLL, and also includes bit rate correction means for correcting the bit rate of the signal to be reproduced. data playback device. (7) The bit rate measuring means detects regular patterns or words that appear for each series of data lengths, measures the detection period using a known time base, and outputs measurement data. The data reproducing device described. (8) The bit rate measuring means includes determining means for determining the reliability of the measurement data and outputting a determination signal to the capture range control signal generating means, and the capture range control signal generating means When the determination signal indicates that the bit rate is within the range, a control signal is generated based on the difference between the bit rate target value and the output data of the bit rate measuring means, and is supplied to the clock recovery PLL, so that the reliability is within the predetermined range. When the determination signal indicates that the bit rate is out of range, instead of using the output data of the current bit rate measuring means, the output data of the previously obtained bit rate measuring means is selected whose reliability is within the predetermined range and is the highest. 9. The data reproducing apparatus according to claim 8, wherein a new control signal is used to generate a control signal based on the difference from the bit rate target value and to supply the control signal to the clock reproducing PLL. (9) In the determination means for determining the reliability of the measurement data, when the determination signal indicates that the reliability is outside a predetermined range, the capture range control signal generation means outputs the output data of the current bit rate measurement means. Instead, among the previously obtained output data of the bit rate measuring means, the latest one whose reliability is within a predetermined range is adopted, and a control signal is generated based on the difference from the bit rate target value. If the reliability of the determination signal continues to be outside the predetermined range,
A clock regeneration PLL that generates a control signal that changes instantaneously or gradually to a preset default control signal.
9. The data reproducing apparatus according to claim 8, wherein the data reproducing apparatus is configured to supply the data to the data reproducing apparatus. (10) The bit rate measuring means includes error detection means for detecting errors using an error detection code included in the data;
a continuity detection means for detecting that regular patterns or words that appear for each series of data lengths have been successively detected; 7. The data reproducing apparatus according to claim 6, further comprising determining means for determining reliability based on the result of error detection. (11) The recording medium is a tape, and the reading means for obtaining the reproduction signal includes a reel driver that drives the supply reel and take-up reel around which the tape is wound to run the tape, and a reel driver that drives the tape to run the tape at a predetermined tape speed. A reel servo control means that controls the driver, a head that contacts the tape and reads signals, a cylinder in which the head is placed, a cylinder driver that rotates the cylinder, and a tape that is pulled out from the reel and wound around the cylinder. 7. The data reproducing apparatus according to claim 6, further comprising mechanical means for causing the data to run. (12) The bit rate correction means inputs the output data of the bit rate measuring means or a signal obtained by converting data based on the difference data between the bit rate target value and the output data of the bit rate measuring means. 12. The data reproducing apparatus according to claim 11, further comprising tape speed control means for supplying a signal for adjusting the tape speed to the reel servo control means. (13) The bit rate correction means inputs the output data of the bit rate measuring means or a signal obtained by converting data based on the difference data between the bit rate target value and the output data of the bit rate measuring means. 12. The data reproducing apparatus according to claim 11, further comprising cylinder speed control means for supplying a signal for adjusting cylinder speed to cylinder servo control means. (14) A reading device that reads a recording medium to obtain a reproduced signal, a bit rate measuring device that measures the bit rate of the reproduced signal, and a clock recovery PL that extracts a clock from the reproduced signal.
L, a capture range control means for controlling the capture range of the PLL, and a capture range for supplying a signal obtained by converting based on the difference data between the bit rate target value and the output data of the bit rate measuring means to the clock regeneration PLL. The bit rate measuring means includes a means for detecting a regular pattern or word that appears for each series of data lengths, a means for timing this detection period using a known time base, and a timer. and determining means for determining the reliability of this measurement data and outputting a determination signal to the capture range control signal generating means. When the determination signal indicates that the bit rate is within the range, a control signal is generated based on the difference between the bit rate target value and the output data of the bit rate measuring means, and is supplied to the clock recovery PLL, so that the reliability is within the predetermined range. When the determination signal indicates that the bit rate is out of range, instead of using the output data of the current bit rate measuring means, the output data of the previously obtained bit rate measuring means is selected whose reliability is within the predetermined range and is the highest. A new method is adopted to generate a control signal based on the difference from the bit rate target value and supply it to the clock recovery PLL, and if the reliability of the determination signal continues to be outside the predetermined range,
A clock regeneration PLL that generates a control signal that changes instantaneously or gradually to a preset default control signal.
A data reproducing device that supplies data to (15) The determination means includes an error detection means for detecting errors using an error detection code included in the data, and a continuous detection of regular patterns or words that appear for each series of data lengths. 15. Continuity detecting means for detecting the occurrence of errors, and the reliability is determined based on the output of the continuity detecting means and the result of detecting errors in regular patterns or words. data playback device.