JPH02141837A - Microprocessor control system - Google Patents

Abstract

PURPOSE:To detect runaway of a microprocessor, and to perform the abnormality recovery processing by discriminating an abnormal state, and performing the recovery processing for abnormality at the time of referring to a part other than a normally programmed part during execution of a program. CONSTITUTION:A redundant storage area 21 is provided for each address of a main storage device 2, and discriminating information 22 to distinguish the normally programmed part from the unprogrammed part is written in this redundant storage area 21. A discriminating means 31 which refers to discriminating information 22 to discriminate the access and an abnormality processing means 32 which performs the recovery processing for abnormality in the case of abnormal access are provided. When a microprocessor 1 refers to the part other than the normally programmed part during execution of the program, the abnormal state is discriminated to perform the recovery processing for abnormality. Thus, runaway is stopped without having a bad influence upon the system execution speed.

Description

[Detailed Description of the Invention] [Summary] Regarding the control of a microprocessor, the purpose of detecting runaway of the microprocessor and performing abnormality relief processing is to provide a redundant storage area corresponding to each address of the main storage device. ,
In the redundant storage area, identification information that can distinguish between a legally programmed part and an unprogrammed part is written, and the microprocessor refers to the identification information corresponding to the address of the main memory accessed to determine if it is a legitimate part. an identification means for identifying whether the access is an abnormal access or an abnormal access; and an abnormality processing means for carrying out relief processing in the event of an abnormality when the identification result of the identification means is an abnormal access; , when a portion other than the normally programmed portion is referenced, it is determined to be in an abnormal state and a relief process is performed in the event of an abnormality.

[Industrial application field]

The present invention relates to a control method for a microprocessor, and particularly to a method for avoiding runaway of a microprocessor.

Microprocessors have become cheaper due to advances in semiconductor technology and are now widely used to control all parts of industrial machinery. A microprocessor operates according to a predetermined program stored in the main memory and performs predetermined control, but for some reason the microprocessor jumps to an area other than the predetermined program area and performs an operation completely different from the expected operation. There is. This is called a runaway of the microprocessor, and since the controlled object enters an abnormal state, it is necessary to detect this as soon as possible and release the abnormal state.

[Conventional technology]

Causes of a microprocessor running out of control include those that fall into a dynamic loop and become unable to escape, and those that jump to an area other than a predetermined program area and perform unexpected operations.

Regarding the former, a so-called watchdog timer is set up to detect a fall into a loop.

However, in conventional microprocessors, there is no appropriate means to detect this abnormal state when control is transferred to an empty area of a program that should not be accessed for some reason, resulting in a runaway state. , no countermeasures could be taken.

As shown in Figure 5, one method for detecting runaways that occur when control is transferred to an area that should not be accessed is to compare addresses that are the boundaries between addresses that the microprocessor is allowed to reference and addresses that are not. There is a way to constantly monitor the area using a device to check whether the area is being violated, and if so, to indicate an error.

Since the program area is generally divided into several areas and allocated, multiple comparisons will be made.

In FIG. 5(a), a comparator (CMP) compares the upper and lower limit addresses of an area that may be referred to (regularly programmed area) and the address AD that the processor refers to. , <ADl, ADz <AD, <AD3 , AD4
<AD, <ADs, AD&<ADr, it is identified as an access to an area that should not be referenced, and if the number of area divisions is large, the
), it requires a large number of comparators.

5, etc.), the number of comparators is reduced and each upper limit address and lower limit address are sequentially switched and compared using a multiplexer (MPX).Although the number of comparators is small, a large amount of time is required for comparison. Become.

[Problem to be solved by the invention]

As mentioned above, in the method of dividing and allocating a program area and detecting an area violation, the more areas that can be divided, the larger the hardware used for comparison becomes. If you try to do this, it has the disadvantage of negatively impacting the system's execution speed.

The problem to be solved by the present invention is to solve these conventional problems and provide a method for preventing runaway using small-scale hardware without adversely affecting the execution speed of the system.

[Means to solve the problem]

FIG. 1 is a block diagram showing the configuration of the present invention.

In the figure, 1 is a microprocessor (MPU), and 2 is a main storage device.

A redundant storage area 21 is provided for each address in the storage area of the main storage device 2.

Reference numeral 22 is identification information written in the redundant storage area 21, and is information that can distinguish between a properly programmed part and an unprogrammed part.

Reference numeral 31 denotes identification means, which refers to the identification information 22 corresponding to the address of the main storage device 1 accessed by the microprocessor 1 and identifies whether the access is a normal access or an abnormal access.

Reference numeral 32 denotes an abnormality processing means, which performs an abnormality relief process when the identification result of the identification means 11 is an abnormal access.

For example, the identification means 31 and the abnormality processing means 32 are provided as additional circuits to the microprocessor chip l,
This can be realized by adding a ROM 21 of decimal bits (one bit is enough) to the main memory ROM 2, connecting address lines of all addresses, and writing identification information.

(Function) In the present invention, a redundant storage area 21 is provided for each address of the storage area of the main storage device 2, and identification information is provided at this location to identify a properly programmed part and an unprogrammed part. 22 is written in the microprocessor 1.The microprocessor 1 includes an identification means 31 that identifies whether the access is normal or abnormal by referring to the identification information 22 in the data read from the main storage device 2, and a relief process in the event of an abnormality. An abnormality processing means 32 is provided to perform the following.

During the execution of the program, the identification means 31 always uses the identification information 22.
is monitored, and if the identification information 22 indicates an abnormal access, it is notified to the abnormality processing means 32, and the abnormality processing means 32 performs relief processing at the time of abnormality.

The identification information 22 is, for example, "1" for areas that are normally programmed, and "0" for other areas.

The abnormality processing means 32 performs relief processing in the event of an abnormality, for example, by reporting the occurrence of an abnormality to a host device, and further applying a system reset to the microprocessor 1 or issuing an abnormality interrupt.

〔Example〕

The present invention will be explained in more detail below with reference to embodiments shown in FIGS. 2 to 4.

FIG. 2 is a diagram schematically showing the configuration and operation of an embodiment of the present invention.

FIG. 3 is a flowchart showing processing according to an embodiment of the present invention.

In the figure, the part between ■-■ indicates the operation of the MPU,
2-2 indicates the operation of the identification circuit and abnormality processing circuit corresponding to the operation of the MPU.

The operation will be described below with reference to FIG. 2 and along the processing steps of the flowchart in FIG. 3.

■MPU accesses address X of main memory and data (
program code).

(2) The MPU executes instructions according to the read program code.

When @MPU accesses address X, the value of the identification information of the redundant storage area corresponding to address X is read into the identification circuit.

(2) As a result of the identification information identification by the identification circuit, if the value is "l", proceed to step (2), and if it is "0", proceed to step (2).

■The identification circuit determines that there is no abnormality and does nothing.

Therefore, execution of instructions by the MPU continues.

The [phase] identification circuit determines that the state is abnormal and notifies the abnormality processing circuit. The abnormality processing circuit performs reporting to the host device and other processing as relief processing in the event of an abnormality.

As shown in the flowchart in Figure 3, the MPU executes instructions regardless of abnormal state monitoring, and the identification circuit supports MPU memory access, performs monitoring independently of MPU operation, and detects abnormalities. Since the abnormality processing circuit performs abnormality processing only occasionally, the execution speed of the MPU is not affected at all.

FIG. 4 is a diagram showing the configuration of an embodiment of the present invention.

The MPUI of this embodiment is used in a magnetic disk device,
Hypernyms! A servo circuit 4 is controlled by a command from the disk controller 3 to perform control operations such as positioning the magnetic head.

2 is a main memory device ROM, to which a redundant area ROM 21 is connected.

31 is an identification circuit that identifies the value of the redundant area.

32 is an abnormality processing circuit, which includes a first latch 321 and a second latch 321;
It consists of a latch 322, a clock control circuit 323, and a set control circuit 324.

51 is a clock generation circuit that generates a clock to be supplied to the MPUI and others. A power-on reset circuit 52 performs necessary reset processing when the power is turned on. 53
is an MPU reset signal generation circuit, which generates a reset signal for the MPUI.

When the identification circuit 31 detects an error, the abnormality processing circuit 32
The first latch 321 is set.

The output of the first latch 321 is connected to the host device 3, the clock control circuit 323, the servo circuit 4, and the second latch 322, and is used to report errors to the host device 3, stop clock supply to the MPU 1, and send it to the servo circuit 4. A series of operations including notification of the error and setting of the second latch 322 are performed.

The servo circuit 4 takes measures to prevent damage to the mechanism.

The host device 3 receives the error report, sends an error reset signal, resets the first latch 321, controls the clock control circuit 323 to restart the clock to the MPU 1, and controls the reset signal control circuit 324. It controls and resets the MPUI.

The reset MPUI executes an initialization program. 2nd latch 3 while running initialization program
22, since the estatus signal is on, it is recognized that the cause of the reset is not due to power-on (it is due to an error), and processing is performed accordingly.If the second latch 232 If it is still set, reset it.

Through the above processing, it is possible to escape from the abnormal state and return to normal operation.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, any address can be targeted for error detection, hardware can be implemented on a small scale, and runaway can be prevented without adversely affecting system execution speed. This has a significant effect in contributing to improving the reliability of microprocessor systems.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the present invention, FIG. 2 is a schematic diagram showing the configuration and operation of an embodiment of the present invention, FIG. 3 is a flowchart showing the operation of an embodiment of the present invention, and FIG. This figure shows the configuration of an embodiment of the present invention, and FIG. 5 is a diagram showing an example of runaway detection according to a conventional example. In the figure, 1 is a microprocessor (MPU), 2 is a main memory (ROM), 3 is a host device, 4 is a servo circuit, 21 is a redundant storage area, 22 is identification information,
31 is an identification means (circuit), 32 is an abnormality processing means (circuit), 321.322 is a latch, 323 is a clock control circuit, 324 is a reset signal control circuit, 51 is a clock generation circuit, 52 is a power-on reset circuit, 53 indicates an MPU reset signal generation circuit. Flowchart showing the operation of an embodiment of the invention

Claims (1)

[Scope of Claims] A microprocessor system comprising a microprocessor (1) that executes a predetermined control operation based on a program, and a main storage device (2) that stores the program. Redundant storage area corresponding to each address (
21), and in the redundant storage area (21), identification information (22) that can identify the normally programmed part and the non-programmed part is written, and the main memory accessed by the microprocessor (1). Device(
an identification means (31) for identifying whether the access is a normal access or an abnormal access by referring to the identification information (22) corresponding to the address of 2); and the identification result of the identification means (31) is an abnormal access. an abnormality processing means (32) that performs relief processing in the event of an abnormality; when the microprocessor (1) refers to a part other than the normally programmed part during execution of the program, the microprocessor (1) determines that it is in an abnormal state; , a microprocessor control system characterized in that it is configured to perform relief processing in the event of an abnormality.