JPH02148730A - Apparatus and method for thin film deposition - Google Patents

Abstract

PURPOSE:To facilitate forming deposition thin films on both the surfaces of a wafer without producing the warpage of the wafer by a method wherein the wafer is inserted into the middle of two electrodes which are symmetrically facing to each other in a CVD chamber so as to be in parallel with the electrodes. CONSTITUTION:After a plasma CVD chamber main part 10 is evacuated by a bump to obtain a required vacuum degree, while raw gas is introduced from a first gas supply system, an AC high voltage is applied between electrodes symmetrically facing each other by an AC source 18 and, at the same time, a power is supplied to the heaters of the electrode parts by a substrate heating electric source 17. With this process, discharges are introduced between a wafer 20 connected to a ground potential and the electrodes by the AC high voltage and material corresponding to the raw gas is deposited on both the surfaces of the wafer 20 provided at the middle port between both the electrodes in parallel with them by a plasma CVD method simultaneously and similarly and warpage of the wafer is not produced. As a result, excellent deposited thin films can be formed on both the surfaces of the wafer 20 without producing the warpage of the wafer 20.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a thin film deposition apparatus and a thin film deposition method.

2. Description of the Related Art Currently, in LSIs and the like, the surface of the substrate is finally coated with a passivation film in order to cut off the elements from the outside and improve their reliability.

The materials are PSG (phosphorus glass) and plasma Si.
02. Plasma SiN and the like are used, and the plasma SiN film in particular is widely used as a passivation film in semiconductor processes because of its denseness and high reliability in water resistance and ion resistance.

Problems to be Solved by the Invention Although the plasma SiN film has the above-mentioned advantages, new problems have arisen as the wiring width of Ae wiring becomes narrower with the progress of miniaturization of wiring in LSI and the like.

The plasma SiN film has a different coefficient of thermal expansion from the underlying Si substrate and has high hardness (no elasticity), so it bends the silicon wafer and applies stress to the Ae wiring formed on the wafer.

Stressed l wiring becomes Ae above a certain temperature.
This has the problem of causing movement of constituent particles (stress migration), forming voids and slits, and eventually leading to wire breakage.

In view of the above, an object of the present invention is to provide a method for forming a passivation film and a film deposition apparatus that do not apply stress to Ae wiring.

Means for Solving the Problems The present invention provides a method of depositing thin films of the same type and quality on both the front and back surfaces of a wafer by plasma chemical vapor deposition, and two symmetrical and opposing electrodes. In this device, a wafer is inserted into the center of the two electrodes parallel to the electrodes in a vacuum chamber equipped with a vacuum chamber, and a film can be deposited on both sides of the wafer using plasma chemical vapor deposition.

Function The present invention reduces stress on the wafer and eliminates warpage by depositing films on both sides of the wafer using the method and apparatus described above.

Embodiment FIG. 1 shows an external configuration diagram of a plasma CVD deposition apparatus of the present invention.

A load lock chamber 11 is connected to the main body chamber 10, and a gate valve 12 separates the two chambers. The main chamber 10 includes a main pump 13 having a mechanical booster pump and a rotary pump.
Then, material gas and cleaning gas can be introduced. A first gas introduction system 15 and a substrate heating power source 17.
An AC power source 18 is added.

Added to the load lock chamber 11 are a load lock pump 14 having a mechanical booster pump and a rotary pump, and a second gas introduction system 16 into which N N 2 gas can be introduced. The wafer 20 to be deposited is inserted through the wafer inlet 19 on the end face of the load lock chamber 11 and transferred to the load lock chamber 11 by the wafer transport system 13.
From there, it is transported to the main body chamber 10.

After the wafer 20 is fixed at the center of the main body chamber 10, the wafer transport system 13 returns to the load lock chamber 11,
The gate valve 12 is closed and the deposition process is performed in the body chamber 10.

FIG. 2 shows details of the main body chamber 10. An upper electrode 23a is attached to the upper surface of the main body chamber 10 via a grinding stone 22.

Further, a lower electrode 23b is similarly attached to the lower surface, and both electrodes are placed parallel to each other and facing each other. Electrode 2
The electrodes 3a and 23b are connected to the AC power source 18 outside the main chamber 10, and the electrodes 23a, 23b are connected to the AC power source 18.
The heater 26 inside the heater 23b is electrically insulated from the electrode itself and connected to the substrate heating power source 17 outside the main chamber 10. Also, the electrode 23a.

23b is surrounded as shown in the figure by a shield plate 25 which is connected to the side wall of the main body chamber 10, and to the upper and lower surfaces thereof and to the ground a27 to prevent discharge.

The wafer 20 is fixed by a susceptor 24 connected to earth b28 exactly in the middle between the upper electrode 23a and the lower electrode 23b. In the apparatus used in this experiment, the distance between the upper electrode 23a and the wafer 20 is 3CI11, but this distance can be changed as necessary. The features of this device are centered around the wafer 20.
The upper electrode 23a and the lower electrode 23b are completely symmetrical.

In FIG. 3, it is inserted into the main body chamber 10.

The state of the wafer 20 is shown in a top view. The wafer 20 has the direction of the facet 29 aligned with the gate valve 12.
It is placed facing in the direction of , and is fixed at three places by the susceptor 24.

An extremal 1 cm of the wafer 20 is etched in advance so that the silicon surface is exposed, and the etched portion is sandwiched between the susceptors 24. This allows the wafer to
20 itself becomes a ground potential and can cause discharge with the electrodes 23a and 23b.

An example of actually depositing a SiN film using this apparatus is shown below. After the wafer 20 is set in the main body chamber 10, the main body chamber is evacuated to 10 −5 Torr or less, and the wafer 10 is heated to 300° C. by thermal radiation from the electrodes 23 a and 23 b. Next, from the first gas introduction system, SiSiH420se, N H350SCCI1.
N2100sccm is flowed respectively, 0.30To
The degree of vacuum in the main chamber is maintained at r r. The discharge is from an AC power source of 400KHz.

Deposition is performed by power injection of 100 W into the two electrodes.

The wafer after depositing a 5000A plasma SiN film was measured using a Ueno\-warpage measuring device using the Newton ring method. The results are shown in FIG.

The contour lines seen on the wafer indicate the warp state of the wafer at 1 μm height intervals, and if calculated by comparing it with the amount of warp before deposition, the total 5tress2 x 10
' (dyn/cm ) compressive stress, and when converting the film thickness assuming that it is deposited on only one side, the S stress value is 5
The result is 10B (dye/cd) or less. Compared to the stress value X 109 (dyn/c+J) of the conventional P-8iN film deposited on only one side, the apparent stress value is lowered by nearly one digit.

Similarly, on the 6-inch wafer Si substrate 30,
After μm accumulation for NSCSC film deposited by atmospheric CVD, A
An e-8i film is deposited to a thickness of 0.8 μm by sputtering, and an Ae-3i wiring 32 is formed using photolithography. Ae-
The 8i wiring 32 has a wiring width of 1 μm and a total length of 30 cI when folded back.
It has measurement pads at both ends.

A plasma SiN film 33 (
0.8 μm) was deposited only on the top surface (A) and one was deposited on both the back and front surfaces (B) at the same time, and a high temperature holding test was conducted for 1000 hours at 150° C. in a N2 gas atmosphere.

In FIG. 6, the horizontal axis represents the resistance of the Ae wiring, and the vertical axis represents the frequency of the 65 measurement wirings within the wafer. From the above figure,
Reference sample without SiN (Ref, ),
The middle row shows the sample (A) in which the SiN film was deposited only on the top surface, and the bottom row shows the sample (B) in which the SiN film was deposited on both sides. As shown in the figure, compared to the sample (Ref), the sample (A) has
Approximately 25% of wiring breaks (OPEN)
There are many cases where the resistance value has increased. On the other hand, in the sample (B), there were no failures due to disconnection, and the distribution of resistance values was almost the same as the sample (Re f ).

In addition to the effects of the invention, as shown above, a plasma CV with a completely symmetrical structure
In the D apparatus, it is possible to uniformly deposit a deposit on both sides of a wafer, and it is possible to deposit any film type and film thickness without causing warpage on the wafer. Further, since both sides are deposited simultaneously, there is no condition that causes the wafer to bend, and there is no possibility that the wafer will bend even under thermal stress at any temperature after deposition.

As a result, when miniaturized elements such as LSIs are formed on the wafer, it is possible to reduce wiring breakage and damage to oxide films caused by warping of the wafer.

Further, according to unexpected experimental results, the present invention significantly improves the reliability of wiring in which plasma SiN films are passivated on both sides of a wafer, and its practical effects are extremely large.

[Brief explanation of the drawing]

Fig. 1 is a configuration diagram of the device according to the present invention, Fig. 2 is a detailed cross-sectional structural diagram of the main body chamber of the device, Fig. 3 is a top view inside the main body chamber of the device according to the present invention, and Fig. 4 is a Si
FIG. 5 is a schematic cross-sectional structure diagram showing the amount of warpage of a Si wafer substrate, and FIG. 6 is a frequency distribution diagram for wiring resistance. 10... Main body chamber, 27... Earth a, 11... Load lock chamber, 28...
...Earth b112...Gate valve, 29
...Facet, 13...Wafer transport system, 30...6-inch wafer Si substrate, 1
4...Loadlock pump, 31...
NSG, 15...First gas introduction system, 32...
...Ae-3i wiring, 16...Second gas introduction system, 33...Plasma SiN film, 17...
...Power supply for substrate heating, 18... AC power supply, 19
...Wafer outlet, 20...Wafer, 21...Matching coil. Name of agent: Patent attorney Shigetaka Awano and one other person Figure 6 inch Figure (A (B)

Claims (2)

[Claims] (1) In a vacuum chamber equipped with a vacuum exhaust system, a gas introduction system, and two symmetrical and opposing electrodes, insert a wafer parallel to the center of the two electrodes, and insert the wafer inside the two electrodes. a mechanism for heating the wafer with a heater embedded in the vacuum chamber; a mechanism for transmitting power into the vacuum chamber from an AC power source externally connected to the two electrodes; and a source gas, which is the material for the thin film, from the gas introduction system. A thin film deposition device equipped with a mechanism for introducing (2) A deposition method in which thin films of the same type and quality are deposited simultaneously on both the front and back surfaces of a wafer by plasma chemical vapor deposition.