JPH0213962B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a multi-channel radio device that employs a PLL synthesizer system, and more particularly to a multi-channel radio device that is equipped with a device that assists in adjustment operations of its receiving section and transmitting section.

BACKGROUND TECHNOLOGY Although the frequency range covered by commercial radio equipment is as wide as 20 MHz, for example, multiple transmission and reception frequencies are assigned to one user within a relatively narrow frequency range. This assignment is
In the case of a multi-channel radio device that employs the PLL synthesizer method, this is done by limiting the frequencies that can be transmitted and received by key input operations to a plurality of transmitting frequencies and a plurality of receiving frequencies that are stored in advance in a non-volatile memory such as ROM. Normally, in radio equipment, a tuning circuit that tunes to the reception frequency is built into the high-frequency stage such as the reception high-frequency amplifier section, and the variable adjustment components (variable capacitor, tuning coil), etc. of the tuning circuit are adjusted according to the reception frequency. , to obtain the necessary tuning characteristics. Generally, this adjustment is made to optimize the reception sensitivity at a certain reception frequency, so the reception sensitivity deteriorates at frequencies distant from this adjustment frequency. For this reason, if a radio has one reception frequency, adjustment can be made at this frequency, but with a multi-channel receiver that has multiple reception frequencies, reception sensitivity decreases at frequencies far from the adjustment frequency. There is a problem with it. This is the same in the case of transmission, and there is a problem of a drop in the transmission level etc. at frequencies far from the adjustment frequency.

By the way, a specific receiving frequency for a specific radio,
When transmitting frequencies are assigned, it is important that performance deviations such as reception sensitivity deviations between the plurality of assigned reception frequencies and performance deviations such as transmission output deviations between the plurality of assigned transmission frequencies be small. For this reason, adjustment to reduce the above-mentioned performance deviation is usually performed after frequency allocation.

For example, if we take reception sensitivity as an example, this adjustment is performed using one of the assigned frequencies, for example, the highest reception frequency.
If the adjustment points of each part are adjusted so that the reception sensitivity is maximized at fRH, the deviation from the lowest reception frequency fRL will become too large as shown in Figure 5, so the maximum reception frequency fRH will be adjusted as shown in Figure 6. A method is adopted in which the deviation between the assigned frequencies is made as small as possible by adjusting the receiving frequency fRO which is intermediate between the lowest receiving frequency fRL.

This adjustment is possible in receivers that use the PLL synthesizer method by setting the frequency division ratio in the PLL circuit so that the reception frequency is fRO, but when setting the radio to this intermediate frequency fRO, Since there are many different combinations of frequencies to be assigned to each radio, it is relatively troublesome to calculate the intermediate frequency. Additionally, in the past, the adjuster had to manually set the frequency of the radio so that the PLL synthesizer section would operate at the calculated intermediate frequency, which was also a factor in reducing work efficiency.

Problems to be Solved by the Invention The present invention is an improvement over such conventional problems, and an object of the present invention is to make it possible to easily perform the above-mentioned adjustment of a multi-channel radio device.

Means to solve the problem In general, PLL synthesizer type radio equipment
By simply setting the frequency division ratio data corresponding to the frequency in the PLL controller, the voltage-controlled oscillator can be used to set any channel frequency within the band used by the radio.On the other hand, the microcomputer system built into the radio It is possible to send arbitrary data to the controller, and the frequency data can be processed using the arithmetic function of the microcomputer. The present invention has focused on such points, and in order to improve the above problems, as shown in FIG. and limited to multiple reception frequencies.
A multi-channel radio device adopting the PLL synthesizer method is provided with a switch means 2 for setting the radio device to an adjustment mode, and a switch means 2 for setting the radio device to an adjustment mode, and a switch means 2 for setting the radio device to an adjustment mode, and a switch means 2 for switching between the highest transmission frequency and the lowest transmission frequency specified by the data stored in the memory 1 in the adjustment mode. Intermediate transmission frequency calculation means 3 that calculates a settable intermediate transmission frequency closest to the frequency or data related thereto, and a maximum receiving frequency and a minimum receiving frequency specified by data stored in the memory 1 in the adjustment mode. Intermediate reception frequency calculation means 4 that calculates a settable intermediate reception frequency closest to the intermediate frequency of or data related thereto.
Then, when transmitting in the adjustment mode, the PLL synthesizer section 5 is operated at the calculated intermediate transmission frequency, and this intermediate transmission frequency or data related thereto is displayed on the display 6, and when receiving in the adjustment mode, the PLL synthesizer section 5 is operated at the calculated intermediate transmission frequency. An adjustment assisting device is added, which includes a control means 7 that operates the synthesizer section 5 at the calculated intermediate reception frequency and displays this intermediate reception frequency or data related thereto on the display 6.

Operation When the switch means 2 is operated to put the radio into the adjustment mode, the intermediate transmission frequency calculation means 3 selects the frequency closest to the intermediate frequency of the plurality of transmission frequencies stored in the memory 1 in advance, and the PLL synthesizer section 5
The frequency that can be set is calculated, and the frequency that is closest to the intermediate frequency of the plurality of reception frequencies stored in advance in the memory 1 by the intermediate reception frequency calculation means 4, and
A frequency that can be set by the PLL synthesizer section 5 is calculated. Then, when the radio device is put into a transmitting state, such as by turning on the press talk switch, the control means 7 causes the PLL synthesizer section 5 to operate at the determined intermediate transmission frequency, and the intermediate transmission frequency is displayed on the display 6, and the press talk switch is turned on. When the wireless device is placed in a reception state, such as by turning off a switch, the control means 7 causes the PLL synthesizer section 5 to operate at the determined intermediate reception frequency, and the intermediate reception frequency is displayed on the display 6.

Embodiment FIG. 2 shows a PLL having the adjustment assisting device of the present invention.
A block diagram of the main parts of a multi-channel radio device using a synthesizer method is shown. In the same figure, 10 is PLL
In the synthesizer section, a voltage controlled oscillator (VCO)
10a, and a PLL controller 10b that generates a voltage according to the phase difference between a signal obtained by dividing this output signal by a frequency division ratio given by the interface 11 and a reference signal of the reference oscillation circuit 12. PLL
The output of the synthesizer section 10 is input by the switching circuit 13 to the transmitting section 14 at the time of transmission, and is inputted to the receiving section 16 via the local section 15 at the time of reception.
The transmitting section 14 voltage-amplifies and power-amplifies the output of the PLL synthesizer section 10 which has been frequency-modulated by the audio signal from the microphone 17, and emits the transmitted radio wave from the antenna 19 via the switching circuit 18. The switching circuit 18 switches to the receiving section 16 side during reception,
The received radio wave received by the antenna 19 is input to the receiving section 16 via this switching circuit 18, where it is mixed with the signal from the local section 15, and a demodulated signal is sent to the speaker 20.

The interface 11 is connected to a microcomputer 21, a display section 24, an operation section 25, a mode changeover switch 26, and a press talk switch 27.
Connected to RAM23. The ROM 22 is a memory that stores frequency division ratio data corresponding to a plurality of transmission frequencies and a plurality of reception frequencies assigned to the radio device, and for example, 4 waves (fT1>
fT2>fT3>fT4), and frequency division ratio data (NT1 to NT4, NR1 to NR4) corresponding to four waves (fR1>fR2>fR3>fR4) as reception frequencies are stored. The operation unit 25 has transmit and receive channel buttons, and the microcomputer 21 stores frequency division ratio data corresponding to the pressed channel button in the ROM.
22 and via interface 11.
By feeding the signal to the PLL synthesizer section 10, the transmitting frequency and receiving frequency of the radio device are controlled.
Further, the microcomputer 21 displays a frequency corresponding to the frequency division ratio given to the PLL synthesizer section 10 on the display section 24 via the interface 11. Press talk switch 2 to switch between sending and receiving.
When the press talk switch 27 is turned off, the microcomputer 2
1 switches the switching circuits 13 and 18 to the receiving side, and when the pre-talk switch 27 is on, switches them to the transmitting side. At the same time, the transmitter 14 and the receiver 16
Also switch the power supply to. Mode selector switch 2
Reference numeral 6 denotes a switch for setting whether the radio is in a normal operating state or in an adjustment mode, and is read by the microcomputer 21 via the interface 11.

As shown in FIG. 3, when the power is turned on and the mode selector switch 26 is not on, the microcomputer 21 first operates in the normal mode and controls the original operation of the radio. When the mode changeover switch 26 is turned on, the microcomputer 21
moves to the adjustment mode and executes the processing shown in FIG. That is, when entering the adjustment mode, the microcomputer 21 first selects frequency division ratio data NT1 corresponding to the highest frequency fTH (fT1 in the above example) and the lowest frequency fTL (fT4 in the above example) from the transmission frequency group stored in the ROM 22. Find frequency division ratio data NT4 corresponding to , and calculate frequency division ratio data NTM corresponding to an intermediate frequency between the highest frequency fTH and the lowest frequency fTL. However, since the frequency variable steps of the PLL synthesizer section 10 are discrete, such as 25KHz, the highest frequency fTH and the lowest frequency
Since it is not always possible to obtain a frequency division ratio corresponding to the intermediate frequency fT0 of fTL, if it cannot be obtained, the frequency division ratio closest to that frequency division ratio is found and used. Similarly, the microcomputer 21 selects the highest frequency from the reception frequency group stored in the ROM 22.
Frequency division ratio data corresponding to fRH (fR1 in the above example)
NR1 and frequency division ratio data NR4 corresponding to the lowest frequency fRL (fR4 in the above example) are searched, and frequency division ratio data NRM corresponding to the intermediate frequency fR0 between the highest frequency fRH and the lowest frequency fRL is calculated. However, in this case as well, if there is no frequency division ratio corresponding to the frequency fR0 intermediate between the highest frequency fRH and the lowest frequency fRL, the frequency division ratio closest to that frequency division ratio is found and used.

Next, the microcomputer 21 determines whether the pre-talk switch 27 is on or not. If it is on, the microcomputer 21 sends the frequency division ratio data NTM corresponding to the intermediate transmission frequency fT0 obtained above to the PLL synthesizer section via the interface 11. 10 and which corresponds to the frequency division ratio data NTM is calculated, this is displayed on the display section 24, and the switching circuits 13 and 18 are switched to the transmitting side to turn on transmission. In addition, when the pre-talk switch 27 is off, the frequency division ratio data corresponding to the intermediate reception frequency fR0 obtained above is
The NRM is given to the PLL synthesizer section 10 via the interface 11, and the frequency corresponding to the frequency division ratio data NRM is calculated and displayed on the display section 24, and the switching circuits 13 and 18 are switched to the receiving side to transmit the frequency to the PLL synthesizer section 10. is in the receiving state.

Since this embodiment has such a configuration, when the mode changeover switch 26 is turned on and the pre-talk switch 27 is off, the mode is automatically changed to a state in which reception is performed at an intermediate frequency among the allocated reception frequencies preset in the ROM 22. Since the intermediate frequency is displayed on the display section 24, the adjuster can easily set the frequency of the measurement system equipment, such as the standard signal generator, by looking at this display.
When the adjuster completes the reception performance adjustment by, for example, adjusting the bandpass filter before the first mixer and the voltage-controlled oscillator 10a, and turns on the pre-talk switch 27, the ROM
22, and the intermediate frequency is displayed on the display section 24. Therefore,
The adjuster can easily set the frequency of the measuring instrument system by looking at the display, and can, for example, adjust the power stage of the transmitter 14. In other words,
When adjusting the receiving section 16, set the oscillation frequency of the standard signal generator to the frequency displayed on the display section 24 with the press talk switch 27 turned off and input it to the receiving section 16. When adjusting the transmitter 14 by adjusting the adjustment element to achieve the maximum sensitivity, the frequency displayed on the display 24 with the press talk switch 27 turned on,
What is necessary is to set the measurement frequency of the measuring device and adjust the adjustment element so that the maximum level is output. It should be noted that once the adjustment is completed, the mode is shifted to the normal mode by turning off the power or turning off the mode changeover switch 26.

In the above embodiment, the intermediate transmission frequency and the intermediate reception frequency are displayed on the display unit 24, but data related thereto such as frequency division ratio data or channel number may also be displayed.
Furthermore, the above-mentioned adjustment state occurs only in the adjustment mode, and no frequency change occurs in the normal mode, which is the general reception and transmission state.

Effects of the Invention As explained above, according to the present invention, by simply setting the adjustment mode, it becomes possible to transmit and receive at a frequency intermediate between a plurality of pre-assigned transmission frequencies and reception frequencies, and the intermediate frequency or reception frequency becomes possible. Since related data such as frequency division ratio data and channel numbers are displayed on the display, the adjuster can easily know the frequency to be adjusted and can easily perform adjustment work. Become.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of the configuration of the present invention, FIG. 2 is a block diagram of the main parts of a multi-channel radio device adopting a PLL synthesizer method and having an adjustment assisting device of the present invention, and FIG.
5 and 4 are flowcharts showing an example of the software configuration of the present invention, and FIGS. 5 and 6 are diagrams illustrating differences in performance deviation due to differences in frequency to be adjusted. 10 is a PLL synthesizer section, 10a is a voltage controlled oscillator, 10b is a PLL controller, 11
is an interface, 12 is a reference oscillation circuit, 13,
18 is a switching circuit, 14 is a transmitting section, 15 is a local section, 16 is a receiving section, 17 is a microphone, 19
is an antenna, 20 is a speaker, 21 is a microcomputer, 22 is a ROM, 23 is a RAM, 24
25 is a display section, 25 is an operation section, 26 is a mode changeover switch, 27 is a press talk switch, and 28 is an audio amplification circuit.

[Claims]

1. The output of the latch is connected to an output buffer via an inverter, and the output of the output buffer is connected to an external terminal, and the latch is configured so that the data bus is connected to the first inverter via a first transfer gate. The output of the first inverter is connected to the latch output and one end of the second transfer gate via the second inverter, and the other end of the second transfer gate is connected to the first inverter. a latch write control signal is applied to the control terminal of the first transfer gate and also to the input of the third inverter, and the latch write control signal and the output of the third inverter are connected to the input of the third inverter at power-up. is the first
and a level that turns off the second transfer gate, and the output of the third inverter is supplied to the control terminal of the second transfer gate, and the output of the third inverter is supplied to the control terminal of the second transfer gate.
Between the input of the inverter and the power supply, a resistor means having a lower resistance than that between this input and the ground power supply is connected, and the output buffer is composed of a pull-up resistor and a driver. A semiconductor integrated circuit characterized by being made up of transistors.