JPH02135944A - Bit buffer circuit - Google Patents

Abstract

PURPOSE:To always perform buffering at a safe phase by providing a discrimination point on an intermediate point between the positive phase and the negative phase of an internal clock, and monitoring the phase near to the intermediate point of the time slot of an external clock out of the rise of the positive phase or that of the negative phase. CONSTITUTION:Firstly, a discrimination clock (e) is prepared to control the phase of a readout clock (g) by a gate 2 which inputs the internal clock (b) and a double internal clock (d). Next, a select signal (f) is generated by latching the external clock (a) with the discrimination clock (e) at a flip-flop 3. The readout clock (g) goes to the one in which an appropriate phase is outputted selectively at a selector 4 which inputs the positive phase (b) and the negative phase (c) of the internal clock by the select signal. Data in a readout buffer 6 is read out to a readout buffer 7 synchronizing with the positive phase (b) of the internal clock for duty correction. In such a way, it is possible to obtain internal data 8 by switching the data 1 synchronized with the external clock (a) to the internal clock (b) in interlocking manner.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a bit buffer circuit.

[Conventional technology]

As shown in FIG. 4, the conventional bit buffer circuit writes external data 30 to a write buffer 35 in synchronization with an external clock 27, and reads it in bits in synchronization with an internal clock 28 that is asynchronous to the external clock 27. In this case, the external clock 27 is read out to the buffer 36, and the external clock differential pulse obtained by differentiating the rising edge of the tarock by the differentiating circuit 31, and the positive phase 28 and negative phase 2 of the internal clock are read out.
A comparator 33 verifies whether or not the phases of these two differential pulses overlap with the internal clock differential pulse obtained by similarly differentiating the rising edge of the clock 9 and output by the selector 34 by the differentiating circuit 32. If there is phase overlap, it is determined that the phases of the external clock (write clock) and the output clock (read clock) of the selector 34 match, and the comparator 33 switches the select signal of the selector 34 and inverts the read clock. This ensures that data is always transferred to the internal clock with the correct phase.

[Problem to be solved by the invention]

The conventional bit buffer circuit described above controls the phase of the read clock by monitoring the phase overlap of the rising differential pulses of the external clock and the internal clock, so the phases of the write clock and read clock do not get very close. Otherwise, phase inversion of the read clock will not occur.

Therefore, if the amount of phase fluctuation of the external clock is large,
The disadvantage is that no overlap of the differential pulses occurs and there is a risk of double reading of bits or bit slips.

[Means to solve the problem]

According to the present invention, there is provided a buffer for writing external data in synchronization with an external clock, a selector for selecting positive phase or negative phase of the internal clock, and a first buffer for reading data in the write buffer in synchronization with the output clock of the selector. a read buffer, a second read buffer that reads data from the first read ratio buffer in synchronization with the positive phase of the internal clock, a gate that receives the internal clock and twice the internal clock as input, and a gate output and an external clock. A bit buffer circuit is obtained which includes a flip-flop that receives a clock as an input and outputs a select signal of a selector.

〔Example〕

Next, the present invention will be described in more detail with reference to the drawings showing embodiments of the present invention.

Referring to FIGS. 1 and 2, in the first embodiment of the present invention, external data 1 synchronized with external clock a is first written into write buffer 5 using external clock a as the write clock. The data that has not been written is read out to the read buffer 6 in synchronization with the read clock g. In order to control the phase of the read clock g, we first use the internal clock b and the double internal clock d.
The determination clock e is created by the gate 2 which receives the input signal.

Next, in the flip-flop 3, a select signal f is created by latching the external clock a with the discrimination clock e. The appropriate phase of the read clock g is selected and outputted by the selector 4 which inputs the positive phase and negative phase C of the internal clock according to this select signal. Finally, the data in read buffer 6 is put on duty.
For correction, by reading data to the read buffer 7 in synchronization with the positive phase of the internal clock, internal data 8 is obtained by interlockingly replacing the data 1 synchronized with the external clock a with the internal clock b.

Referring to FIG. 3, in a second embodiment of the invention,
Duty correction counter 9 is triggered by the rising edge of external clock a, which is a write clock, and counts up to the midpoint of one time slot of external clock b using n times the internal clock (nXb), and holds "1" during that time. are doing.

In this second embodiment, since the duty correction counter 9 always sends a clock with a duty of -50% to the flip-flop 3, the duty of the external clock is reduced.
This has the advantage that the intermediate point of the external clock can always be used as the monitoring point without depending on the phase, and the most appropriate phase can be selected.

〔Effect of the invention〕

As explained above, according to the present invention, in a bit buffer circuit that transfers data synchronized with an external clock to an internal clock, when comparing the phases of the external clock and the internal clock, the positive phase and negative phase of the internal clock are By setting a discrimination point at the midpoint and monitoring in real time the rising edge of the positive phase and the rising edge of the negative phase, whichever is closer to the midpoint of the external clock time slot, buffering can always be performed with a safe phase. Therefore, there is no bit slip at the time of data transfer, and because of the double buffer configuration, it is possible to always obtain data synchronized with the internal clock with the same data length.

[Brief Description of the Drawings] Fig. 1 is a block diagram of the first embodiment of the present invention, Fig. 2 is a signal waveform diagram of each part of the first embodiment shown in Fig. 1, and Fig. 3 is a block diagram of the first embodiment of the present invention.
The figure is a block diagram of a second embodiment of the present invention, and FIG. 4 is a block diagram of a conventional bit buffer circuit. a: external clock, b: internal clock (positive phase) C: internal clock (negative phase), d: double internal clock, 1: external data, 2: gate, 3: flip-flop, 4: selector, 5: write Buffer, 6: Read buffer, 7
: Read buffer, 8: Internal data, 9: Duty correction counter, 27: External clock, 28: Internal clock (positive phase), 19: Internal clock (negative phase), 30: External data, 31: Differential circuit, 32: Differential circuit, 33: Phase comparator, 34: Selector, 35: Write buffer,
36: Read buffer, 37: Internal data. Agent: Susumu Uchihara, patent attorney Figure 1 Figure 2

Claims (1)

[Claims] a buffer for writing external data in synchronization with an external clock, a selector for selecting a positive phase or a negative phase of an internal clock, and a first read buffer for reading data from the write buffer in synchronization with an output clock of the selector; a second read buffer that reads data from the first read buffer in synchronization with the positive phase of an internal clock;
1. A bit buffer circuit comprising: a gate receiving an internal clock and a double internal clock; and a flip-flop receiving the gate output and an external clock and outputting a select signal of the selector.