JPH02114353A - Main storage initializing system - Google Patents

Abstract

PURPOSE:To shorten the time required for main storage initializing processing by adding one signal line for inquiring whether it is initializing processing or not and providing a mask circuit for masking an unused upper bit in the address space of each main storage. CONSTITUTION:The title system is provided with the inquiring signal line 5 and the mask circuits 6. The signal line 5 is connected in parallel with a common bus 2 to inquire whether plural main storages 3, 4 connected to the common bus 2 are in the initializing processing or not. The mask circuits 6 are included in the plural main storage 3, 4 to mask an unused upper bit in the address space of each main storage 3, 4 and to neglect the module number of each main storage 3, 4 during the period of initializing processing. Consequently, the initializing processing of the whole main storages can be executed within the time required for the initializing processing of one module of the main storage with the maximum capacity, so that the time required for the initializing processing of the main storages can be required for the initializing processing of the main storages can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to main memory initialization processing, and particularly to a method for speeding up the processing.

(Prior Art) Conventionally, this type of main memory initialization processing has adopted a method in which the initialization processing of the next main memory is started only after the initialization processing of the memory of a certain module is completed.

FIG. faa is a block diagram showing an example of a main memory initialization method according to the prior art. In Figure 8,
7 is a CPU, 8 is a common path, and 9 and 10 are main memories, respectively. In FIG. 8, for example, the main memory 9 is initialized by the CPU 7, and then the main memory 10 is initialized by the CPU 7.

In Figure 8, the main memory 9 is 2MB, and the main memory 10 is 4MB.
Let it be B. Let Nα represent a number of 1,000 joules. On the other hand, FIG. 4 is an explanatory diagram showing an example of the use of addresses in the main memory.

Next, the conventional main memory initialization process shown in FIG. 8 will be briefly explained with reference to FIG. 4.

First, 01H is specified as the module number, /QH/ is specified as the address, and address IOH/ of the main memory 9 is specified.
K/OOH/ is written. Thereafter, the main memory $lK10OH/ is written while incrementing the address, and the address becomes /IFFFFFFH/, and the main memory 90
/Q Q H/ is written to all 2MB. After that, 102H/ is specified as the module number and /QH/ is specified as the address, and the same process is executed on the main memory 10, the address becomes /8FFFF'FH/, and 10OH/ is written to all of the main memory 1010O4. The main memory initialization process is completed. As can be seen, the initialization process for the main memory 10 is executed only after the initialization process for the main memory 9 is completed, and the main memory initialization process as a whole is the sum of the time required for the initialization process for each main memory. There is.

(Problem to be solved by the invention) In the conventional main memory initialization processing described above,
There is a drawback that as the number of main memory modules increases, the time required to initialize the main memory increases accordingly.

The purpose of the present invention is to mask the unused high-order bits to /Q/ in the address space of each main memory, and to notify the CPU of this fact during initialization processing for each main memory of different capacity. Eliminate the above deficiencies by notifying the
To provide a main memory initialization system configured to perform seven initialization processes by simultaneously performing initialization processing on all memories, ignoring module numbers.

(Means for Solving the Problems) The main memory initialization method according to the present invention includes an inquiry signal line for making one inquiry and a mask circuit.

An inquiry signal line for making inquiries is installed along with the common path.

This is a type of inquiry for inquiring whether or not initial processing is being performed on a plurality of main memories connected to a common path.

The mask circuit is provided inside multiple main memories, and masks the upper bits that are not used inside the address space of the main memories, and also masks the initial bits. A/During processing, the module number tm of the main memory is rounded.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the main memory initialization method according to the present invention.

In FIG. 1, 1 is a CPU, 2 is a common path, 3 and 4 are main memories, 5 is an inquiry signal line for inquiring whether or not initialization processing is to be performed, and 6 is a mask circuit.

In FIG. 1, the CPUI is connected to a main memory 3 and a main memory 4 through a common path 2, and an inquiry signal line 5 is used to inquire whether initialization processing is to be performed or not to each of the main memories 3 and 4.
is connected. In this example, the main memory 3 and the main memory 4 are 2 MB in size, and 4 MB in main memory 4. Further, the 2 MB main memory 3 is provided with a mask circuit 6 for masking the pit 10t which is the most significant bit of the address space. In this example, the 4MB main memory 4 does not require a mask circuit.

Further, the numbers in the main memory 3.4 represent module numbers.

FIG. 112 is an explanatory diagram showing an example of how main memory addresses are used. In this example, the address line is 82 bits, of which 22 bits from pit 10 to bit 31 correspond to up to 4MB as the main memory address space of the module, and 8 bits from pit 2 to pit 9 are used to specify the module number. ing.

Next, the main memory initialization method of the present invention shown in FIG. 1 will be explained with reference to FIG. 2. First, /01H/ (anything is fine) is specified as the module number and /OH/ is specified as the address, and at the same time, the signal indicating whether or not to perform initialization processing is set to high level (or low level) on signal @5. .

As a result, the module number is cleared and 700 H/ is written into the main memory 3 and the main memory 4 at the same time. Therefore, when the address becomes /I FFFFFH/Ic, /Q OH/ is written to all 2MB of main memory 3, but
Since bit 1a, which is the most significant bit of the address space, is masked to tQr by the mask circuit 6, a non-existing address will not be specified from now on. The address becomes /8FFFFFH/, /QQH/ is written to all 4MB of main memory 4, and the main memory initialization process ends.

In this way, the initialization process for the entire main memory can be completed in the same time as the time required for the initialization process for one module of the main memory with the largest content among the main memories constructed in the system.

(Effects of the Invention) As explained above, the present invention adds one inquiry signal line for inquiring whether initialization processing is being performed, and connects the upper bits that are not used in the address space of each main memory to /Q By providing a masking circuit for /, it is possible to support main memories of different capacities, and when initializing a system that has multiple main memories on a common path, the main memories configured in the system, This has the effect of shortening the time required for the main memory initialization process by rounding the time required for the initialization process for one module of the main memory with the maximum capacity to be able to execute the initialization process for the entire main memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the system configuration in the main memory initialization method of the present invention. FIGS. 2C and 4 are explanatory diagrams each showing an example of the use of main memory addresses. The wta diagram is a block diagram showing an example of a system configuration in a conventional main memory initialization method. 11F...CPU 2.8...Common bus 3.4. F, 11...Main memory 5 ##a a #Signal line 6...Mask circuit

Claims (1)

[Claims] an inquiry signal line installed in parallel with the common path for inquiring whether initialization processing is in progress for the plurality of main memories connected to the common path; and an inquiry signal line provided inside the plurality of main memories. The apparatus is characterized by comprising a mask circuit for masking unused upper bits in the address space of the main memory and for ignoring the module number of the main memory during the initial processing. main memory initialization method.