JPH0195375A - Parallel graphic displaying/processing system - Google Patents

Abstract

PURPOSE:To process a division graphic element in parallel and to constitute respective processing modules with the input output buffer small in capacity and an arithmetic means by informing a next processing module of an arithmetic result at respective stages of a clipping. CONSTITUTION:A processing module 3-1 is composed of an input buffer 11, a coordinates converting part 12, a clipping part 13, an output buffer 14, etc., and other processing modules 3-2-3-n are composed in the same way. The modules 3-1-3-n in a parallel processing part 3 can inform other modules of the processing information on the way. Consequently, by informing the next processing module of the arithmetic result at respective stages of the clipping in the part 1, the divided graphic element is processed in parallel. Thus, since buffers 11 and 14, the converting part 12, the arithmetic means like the part 13, etc., of respective modules can be made shorter than the maximum length of the graphic element, respective modules can be miniaturized. Namely, respective processing modules can be constituted by the input output buffer of the small capacity and the arithmetic means.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Prior Art (Figures 6 to 8) Problems to be Solved by the Invention Means for Solving the Problems (Figure 1) Effects Embodiment (Figures 2 to 5) Effects of the invention [Summary] Regarding the parallel graphic display processing method, the capacity of the input buffer etc. can be reduced by dividing a graphic element consisting of a plurality of vertices and making it possible to perform clipping processing. The object of the present invention is to be able to be configured with processing modules, and is equipped with a parallel processing means having a plurality of processing modules equipped with an input buffer, a coordinate conversion means, and a clipping means, and a distribution means for distributing graphic elements to each processing module. In the parallel figure display processing method, divided figure information is output by dividing a figure element consisting of multiple vertices, and the final data of the previous figure element is added to the beginning of the next divided figure element to this divided figure information. At the same time, a graphic element division means adds a graphic element continuation flag to the end of the previous divided graphic element or the beginning of the next graphic element, and adds the first data to the final data of the divided graphic information; Integrating means is provided to maintain the input order and combine processing results for the divided graphic elements, and the processing module is configured to transfer intermediate results of clipping to the next processing module.

[Industrial application field]

The present invention relates to a parallel graphic display processing system, and more particularly to one in which divided graphic elements can be processed in parallel by notifying other processing modules of the intermediate results of clipping.

[Conventional technology]

For example, in a graphic display device, a viewport W is defined within the display surface, and figures such as vectors and polygons are displayed within the viewport W. At this time, for example, as shown in FIG. 6, the original figure to be displayed is at the viewport W.
If it protrudes, it is necessary to clip the protruding part.

For example, as shown in FIG. 6(A), the end point Q1 (X1S
)'1), Q2 When drawing the vector L represented by (x2, y2) so that the end point P1 is located at point 01 outside the viewport W, two points Q inside the viewport W
1', Q2'' to obtain the vector l, and then it is necessary to remove the protruding portion outside the viewport W.

Further, as shown in FIG. 6(B), the vertex Q1(xi, y
+) , Q2 (X2,72)% Q3 (X3,
)F3) 1Q4 (X4% 3F4) SQs
When displaying the polygon P represented by (xs, y5) so that the vertex Q1 is located at the point o1, it is necessary to similarly remove the protruding portion.

By the way, clipping processing, which is processing for this protruding portion, requires a very large amount of calculation, and therefore, the amount of clipping processing is determined depending on the number of vertices.

In addition, graphic display devices are required to have high processing speeds, with a processing capacity of 20,000 to 40,000 polygons/second for polygons and 200,000 to 400,000 vectors/second for vectors. There is.

Therefore, in order to increase the speed, conventionally, as shown in FIG. -2----21-n are provided, and these are arranged in parallel between the distribution section 2o and the integration section 22.

Here, the distribution unit 20 divides the input graphic element group into graphic element units and divides them into each processing module 21-1, 21-2-.
---21- It is distributed to n.

In this case, one or more graphic elements are distributed so that the number of vertices and end points are approximately equal so that the load among the processing modules is evened out.

As shown in FIG. 8(A), the input graphic elements are identifiers P (Pl, P
2-=P n ), the coordinate values of each vertex in the case of a polygon, and the coordinate values of each end point in the case of a vector. For example, in the case of two dimensions, these coordinate values are [x
i, yi (i=1.2-)), and in the case of three dimensions (
xiSyi,zi (i=1.2-.)].

As shown in FIG. 8(B), the processing module 21
When inputting the graphical element with the identifier P1 to -1 and inputting the graphical elements with the identifiers P2 and P3 to the processing module 21-2, the number α of vertices of the identifier P1 and the number of vertices (end points) of the identifiers P2 and P3 β and γ are distributed such that the sum of β and γ is approximately equal to α.

In the processing module 21-1, when the graphic element with the identifier P1 is input to the power buffer 31, the coordinate conversion unit 32, Clipping section 33
Other calculation units perform calculation processing such as coordinate transformation, brightness calculation, clipping processing, etc., and the results are output.
4 will be entered. Other processing modules 21-2, -21
Similar processing is performed for -n.

The integration unit 22 includes each of these processing modules 21-1.21.
-2-21- Recombine the calculation results in H so that the order of the graphical elements matches. In this case, as shown in FIG. 8(C), the coordinate values of the calculation results are entered for each identifier P1, P2, . . . Pn.

[Problem that the invention seeks to solve]

In such conventional methods, it is necessary to process each graphic element. By the way, in some current graphic display devices, the maximum number of vertices of a polygon to be processed is 128, and the data for each vertex is a three-dimensional coordinate value,
Due to brightness, surface inclination, etc., approximately 6 watts per vertex is required, and the capacity of the input/output cover sofa must be as large as the longest side of the graphic element, so a very large capacity arithmetic unit and An in/out cover sofa is required. Therefore, these individual processing modules could not be configured by one LSI.

SUMMARY OF THE INVENTION An object of the present invention is to provide a parallel graphic display processing system in which individual processing modules can be constructed using small-capacity input/output cover sofas and calculation means.

[Means for solving problems]

In order to achieve the above object, in the present invention, as shown in FIG. 1
．． , 3-2- and 3-n are arranged. These processing modules 3-1 to 3-n have a smaller capacity than the conventional one shown in FIG.

In the present invention, when the graphic element input to the distribution section 2 is a polygon, it can be divided by the graphic element division section 1 and input to the processing module.

Therefore, when the graphic element input to the distribution section 2 is a polygon, the data is first transmitted to the input buffer 11 until the processing capacity of the first processing module 3-1 is filled. In this way, for example, the data of polygon P1 as shown in FIG. 1(B) can be converted to data as shown in FIG.
If the full processing capacity is reached when inputting to the processing module 3-1 up to the apex (addi) in the state of Pl-1, then
The processing module 3-2 transmits an amount of data matching its processing capacity in the state of Pl-2 from the next vertex (addi+1) to the vertex (addj). At this time, the graphic element dividing unit 1 sends the graphic element continuation flag (F) indicating that the transfer of the graphic element is in progress, and the data of the apex of the division position of the divided graphic element (coordinate value addi in the illustrated example). It is added and distributed to the processing module 3-2. The graphic element continuation flag is added to the last part before the divided graphic element or to the forefront of the next element, as shown in FIGS. If the polygon cannot be processed by the processing module 3-2, the graphic element continuation flag and the vertices of the division position of the graphic element are added in the same manner as shown in FIG. 1(C) in the state of Pl-3. Next processing module 3-3 (
At this time, the data of the first vertex of the polygon (coordinate value add1 in the example shown) is added to the end, and if there is enough processing capacity, the data of the next graphic element P2 is sent. Then move on to the process. The integrating unit 4 integrates the divided graphic elements and deletes the continuation flag F from the divided graphic elements.

[Effect]

The processing module 3-1 is composed of a power buffer 11, a coordinate transformation section 12, a clipping section 13, an output buffer 114, etc., and the other processing modules 3-2--3-n are similarly constructed. Each of the processing modules 3-1 to 3-n in the parallel processing section 3 is configured to be able to notify others of processing information in progress. Therefore, by notifying the calculation results at each stage of clipping to the next processing module, the divided graphic elements can be processed in parallel. Therefore, the processing module's input buffer, calculation means such as the output cover sofa coordinate conversion section and clipping section can be made shorter than the maximum length of the graphic element, so each processing module can be made smaller than conventional ones. It is also possible to configure it with an LSI of 1 chip.

〔Example〕

An embodiment of the present invention will be described based on FIGS. 2 to 5.

Fig. 2 is a configuration diagram of an embodiment of the present invention, Fig. 3 is an explanatory diagram of the operation of the clipping section in the present invention, Fig. 4 is an explanatory diagram of a graphic display program and coordinate transformation, and Fig. 5 is an explanatory diagram of surface painting processing. be.

In the figure, the same symbols as those on the map indicate the same parts, 5 is a segment management section, 6 is a segment buffer, 7 is a fill section, 8 is a straight line creation section, 9 is a frame buffer, and IO is a display device.

The segment management unit 5 sequentially reads and outputs the display list written in the segment buffer 6 for display.

A display list for display is written in the segment buffer 6, and this display list is a program, and graphic elements such as vectors and polygons to be drawn are also written therein.

The surface painting section 7 calculates the horizontal vector contained in the polygon after the clipping process, for example, as shown in FIG. 5(A).
For the polygon shown in , a horizontal vector as shown by the dotted line in FIG. 3(B) is calculated.

The straight line creation unit 8 creates a straight line by converting a vector into a sequence of points.

The frame buffer 9 is used to store images to be displayed on the display 10 as dot information.

The coordinate transformation unit 12 performs coordinate transformation such as rotation and expansion of coordinates. For example, when the graphic display program shown in Fig. 4 (B) is given for surface l, surface 2, etc. as shown in Fig. 4 (A), this program means the following. .

The first SET-MTX indicates the set of coordinate transformation matrices, in this case (1, l5O-1
, 1, O) is the coordinate transformation matrix.

The next 5ET-CLR (8) specifies that the color of the polygon to be drawn next is set to (8), and the surface painting color is specified by this.

The third line has the coordinates (0,8), (0,7), (3,7), (
3, 8) instructs to draw the surface l specified by Similarly, the 4th line indicates the polygon color change specified in the next 5th line, and the 5th line indicates the polygon color change of surface 2 (2, 7
), (2,5), (5,5) (5,7).

The coordinate transformation is performed using the formula shown in FIG. 4(C).

In the example in Figure (B), (abc)-(1,110), (d
ef)-=(-1, 1, O), so clockwise 4
The figure is rotated by 5° and enlarged by a-fold.

The clipping unit 13 performs clipping processing, and in the present invention, the clipping processing is performed after dividing a polygon into a plurality of graphic elements. Clipping processing in the present invention will be explained with reference to FIG.

As shown in FIG. 3(A), when performing clipping processing on the polygon Pa displayed by vertices 1 to 5 within the view boat w, as shown in FIG. It is divided into vertices 1, 5, 4, and 3 as shown in . These are then processed by a clipping unit 13 in a separate processing module.
It is processed in parallel.

That is, the clipping section of the first processing module extends the top surface of the view boat w in the horizontal direction and calculates the intersection point 1' with the straight line between the vertices 1 and 2, as shown in FIG. The lower surface of the port w is extended in the horizontal direction, and the intersection point 3' with the straight line between the vertices 2 and 3 is calculated. At this time, the second
In the clipping section of the processing module, intersection points 5' and 4' are similarly calculated as shown in FIG. 3(E). In addition, in the first processing module, the calculated intersection points 1' and 3'
The coordinates of are notified to the second processing module. This results in
The second processing module performs processing as shown in FIG. As shown in Figure (F), processing is performed assuming that the vertices of the graphic element are 1'' and 2.3''.

Next, each crimping section extends the left and right surfaces of the viewport W in the vertical direction and calculates the intersection with the straight line 2-3' and the intersection with the straight line 3'-4''.Thus,
As shown in Figure 3 (H), the first processing module calculates the intersection points 3'' and 2'', and as shown in Figure 3 (I), the second processing module calculates the intersection points 3'' and 4''. In this way, the calculated intersection points 2', 311 and 311'
, 4'' into one figure, we can create the figure 3 (J
), a clipped polygon P' can be displayed within the viewport W. Of course, the same processing is performed even if the graphic element is a three-dimensional display, but at this time, the information is notified to other processing modules each time the processing is performed in the X-axis direction and Y-axis direction, that is, in each coordinate axis direction. Become.

The present invention shown in FIG. 2 will now be described in detail.

(11 Write the graphic display program in the segment buffer 6 in advance and start it. At this time, the graphic elements and view boards are the vertices 1 to 5 and the W
3 (B
), (C), the graphic element dividing unit 1 distributes the data to the processing modules 3-1 and 3-2 via the distribution unit 2. These data are then set in the input buffer 11 of each processing module. Then each processing module 3-1
．． Coordinate transformation processing is performed by the coordinate transformation unit 12 3-2.

(2) The divided graphic elements subjected to the coordinate conversion process are subjected to clipping processes in the upper and lower surface directions in the respective clipping units 13 as shown in FIGS. 3(D) and (E).

(3) Next, the clipping section 13 of each processing module:
Perform crimp processing on the left and right sides. As a result, in the processing module 3-1, vertex 2 is clipped to 2', and vertex 3 is clipped to 2'.
' is clipped to 31'.

Also, since the processing module 3-1 notifies the processing module 3-2 that vertex 1 is clipped to 1' and vertex 3 is clipped to 3', the processing module 3-2 processes the Thus, the divided graphic elements of vertices 1'-5'-5-4"-3" will be looked at and handled. As a result, the processing module 3-2 clips the vertex 3' to 3'' and the vertex 4' to 4''.

(4) Since these processes will be sent to the output sofa 14 of each processing module, the integration unit 4 combines them in the order of processing modules 3-1, 3-2, that is, in the order of division of graphic elements. By doing this, Figure 3 (J)
It is possible to create a clipped polygon P' shown in FIG. In this way, the integrating unit 4 integrates the graphic elements while maintaining the order, and combines the divided elements.

(5) The data of this polygon P' is input to the area painting section 7, where it is subjected to an area painting process as shown in FIG. 5, and each vector is outputted as a dot by the straight line generation section 8.

The dot information thus obtained is set in the frame buffer 9, and a predetermined image is displayed on the display 10.

In this way, polygons having a large number of vertices can be divided and processed in parallel, so the capacity of each processing module can be reduced, and as a result, it can be configured with a one-chip LSI or the like.

〔Effect of the invention〕

According to the present invention, the capacity of each input buffer and output buffer of the parallel processing module can be reduced.
The scale of each processing module can be reduced.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the principle of the present invention, Fig. 2 is a configuration diagram of an embodiment of the present invention, Fig. 3 is an explanatory diagram of the operation of the clipping section of the present invention, and Fig. 4 is an explanatory diagram of a graphic display program and coordinate transformation. , FIG. 5 is an explanatory diagram of surface painting processing, FIG. 6 is an explanatory diagram of clipping processing, FIG. 7 is a block diagram of a conventional parallel graphic display processing method, and FIG. 8 is a diagram of the operating principle of the conventional method. 1--Graphic element division section 2--Distribution section 3--Parallel processing section 4--Integration section

Claims (1)

[Claims] Parallel processing means (3) having a plurality of processing modules each including an input buffer (11), coordinate transformation means (12), and clipping means (14), and distribution for distributing graphical elements to each processing module. In the parallel figure display processing method having the means (2), divided figure information is outputted by dividing a figure element composed of a plurality of vertices, and this divided figure information includes the information of the previous divided figure element at the beginning of the next divided figure element. A graphical element that adds the final data of the graphical element, adds a graphical element continuation flag to the end of the previous divided graphical element or the beginning of the next graphical element, and adds the first data to the final data of the divided graphical information. A dividing means (1) and an integrating means (4) that maintains the input order of the graphical elements and combines the processing results for the divided graphical elements are provided, and the processing module transfers the intermediate results of clipping to the next processing module. A parallel graphic display processing method characterized by: