JPH0141250Y2 - - Google Patents
Info
- Publication number
- JPH0141250Y2 JPH0141250Y2 JP18368783U JP18368783U JPH0141250Y2 JP H0141250 Y2 JPH0141250 Y2 JP H0141250Y2 JP 18368783 U JP18368783 U JP 18368783U JP 18368783 U JP18368783 U JP 18368783U JP H0141250 Y2 JPH0141250 Y2 JP H0141250Y2
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- transmitting
- supplied
- output
- transmission
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000005540 biological transmission Effects 0.000 claims description 16
- 230000005236 sound signal Effects 0.000 claims description 10
- 230000003321 amplification Effects 0.000 description 4
- 238000003199 nucleic acid amplification method Methods 0.000 description 4
- 230000010355 oscillation Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Transceivers (AREA)
Description
【考案の詳細な説明】
本考案は、受信専用と考えられていたチユーナ
に送信機能を加えた送受信機に関する。[Detailed Description of the Invention] The present invention relates to a transmitter/receiver in which a transmitting function is added to a tuner that was thought to be only for receiving.
従来、受信専用と考えられていたチユーナに送
信機能を加えた送受信機はない。 Conventionally, there is no transmitter/receiver that adds a transmitting function to the tuner, which was thought to be only for receiving.
本考案は、局部発振器としてPLL回路を有す
るチユーナにおいて、PLL回路の分周比を送信
選択と同時に切替えることにより、一瞬に受信周
波数と同一の周波数で送信可能とした送受信機を
提供することを目的とするものである。 The purpose of this invention is to provide a transmitter/receiver that can instantaneously transmit at the same frequency as the receiving frequency by switching the frequency division ratio of the PLL circuit at the same time as transmission selection in a tuner that has a PLL circuit as a local oscillator. That is.
本考案は前記した目的を達成せんとするもの
で、その構成は、局部発振器がPLL回路で構成
された受信機において、受信周波数が送信のとき
のロツク周波数となるべくPLL回路のプログラ
マブルカウンタの分周比を切替える手段と、前記
PLL回路の電圧制御発振器の出力が送信のとき
のみ供給される送信回路と、前記PLL回路の電
圧制御発振器に供給される位相比較器の出力に送
信のときのみオーデイオ信号を加算する加算手段
とを備えたものである。 The present invention aims to achieve the above-mentioned object, and its configuration is such that, in a receiver whose local oscillator is a PLL circuit, a programmable counter of the PLL circuit is divided so that the reception frequency becomes the lock frequency at the time of transmission. means for switching the ratio;
a transmitting circuit to which the output of the voltage controlled oscillator of the PLL circuit is supplied only when transmitting; and an adding means which adds an audio signal to the output of the phase comparator supplied to the voltage controlled oscillator of the PLL circuit only when transmitting. It is prepared.
以下、本考案を実施例により説明する。 The present invention will be explained below with reference to examples.
図は本考案の一実施例を示すブロツク図であ
る。 The figure is a block diagram showing one embodiment of the present invention.
１は受信アンテナ、２は高周波増幅段、３は混
合段、４はPLL回路からなる局部発振器、５は
中間周波増幅段、６は復調段を示し、アンテナ
１、高周波増幅段２、混合段３、局部発振器４、
中間周波増幅段５および復調段６によりチユーナ
を構成してある。 1 is a receiving antenna, 2 is a high frequency amplification stage, 3 is a mixing stage, 4 is a local oscillator consisting of a PLL circuit, 5 is an intermediate frequency amplification stage, and 6 is a demodulation stage. Antenna 1, high frequency amplification stage 2, mixing stage 3 , local oscillator 4,
An intermediate frequency amplification stage 5 and a demodulation stage 6 constitute a tuner.
局部発振器５は電圧制御発振器（VCO）１１、
VCO１１の出力が供給されるバツフア増幅器１
２、バツフア増幅器１２の出力周波数をＮ分周す
る分周器１３、基準周波数発振器１４、分周器１
３の出力を分周するプログラマブルカウンタと該
プログラマブルカウンタの出力と基準周波数発振
器１４の発振出力とを位相比較する位相比較回路
とを備えた位相比較器１５、位相比較器１５の出
力が供給されるローパスフイルタ１６、ローパス
フイルタ１６の出力を一方の入力とし、かつ出力
をVCO１１に制御出力として供給する加算器１
７とを備えている。位相比較器１５内のプログラ
マブルカウンタは送受信切換スイツチSW−1の送
信指示出力を受けたとき中間周波数に対応する分
周比の補正が除去された分周比で分周がされるよ
うに構成してある。 The local oscillator 5 is a voltage controlled oscillator (VCO) 11,
Buffer amplifier 1 to which the output of VCO 11 is supplied
2. A frequency divider 13 that divides the output frequency of the buffer amplifier 12 by N, a reference frequency oscillator 14, and a frequency divider 1.
The output of the phase comparator 15 is supplied with a phase comparator 15 comprising a programmable counter that frequency-divides the output of the reference frequency oscillator 14 and a phase comparator circuit that compares the phases of the output of the programmable counter and the oscillation output of the reference frequency oscillator 14. Low-pass filter 16, an adder 1 that takes the output of the low-pass filter 16 as one input and supplies the output to the VCO 11 as a control output
7. The programmable counter in the phase comparator 15 is configured so that when it receives the transmission instruction output from the transmission/reception switch SW- 1 , the frequency is divided by a division ratio from which the correction of the division ratio corresponding to the intermediate frequency is removed. There is.
また、プログラマブルカウンタに設定した設定
値は駆動回路１８に供給し、駆動回路１８の出力
を表示器１９に供給して送受信周波数を表示する
ように構成してある。 Further, the set value set in the programmable counter is supplied to a drive circuit 18, and the output of the drive circuit 18 is supplied to a display 19 to display the transmission/reception frequency.
一方、加算器１７にはオーデイオ信号源２１の
出力が送受信切換スイツチSW1−2を介して供給
してある。またバツフア増幅器１２の出力は送受
信切換スイツチSW1−3を介して送信回路２１に
供給してある。なお、２２は送信アンテナであ
る。また送受信切換スイツチSW1−1〜SW1−3は
連動して切換るように構成してある。 On the other hand , the output of the audio signal source 21 is supplied to the adder 17 via transmission/reception changeover switches SW1-2 . Further, the output of the buffer amplifier 12 is supplied to a transmitting circuit 21 via transmitting/receiving changeover switches SW1-3 . Note that 22 is a transmitting antenna. Further, the transmission/reception changeover switches SW1-1 to SW1-3 are configured to be switched in conjunction with each other .
以上の如く構成した本考案の一実施例におい
て、受信状態のときは送受信切換スイツチSW1−
１〜1−3は図に示した接点位置に切換えられてい
る。 In one embodiment of the present invention configured as described above, when in the receiving state, the transmitting/receiving switch SW 1 -
1 to 1-3 are switched to the contact positions shown in the figure.
この状態では位相比較器１５内のプログラマブ
ルカウンタは中間周波数に対応する補正を行なつ
て分周比が設定される。また加算器１７にはオー
デイオ信号が供給されておらず、かつ送信回路２
１にバツフア増幅器１２の出力は供給されていな
い。 In this state, the programmable counter in the phase comparator 15 performs correction corresponding to the intermediate frequency to set the frequency division ratio. Further, the adder 17 is not supplied with an audio signal, and the transmitting circuit 2
1 is not supplied with the output of the buffer amplifier 12.
この状態においては従来のチユーナと同様に作
用し、受信アンテナの受信電波に対する受信が行
なわれる。いま中間周波数を10.7MHzとすればプ
ログラマブルカウンタへの設定値はたとえば〔受
信周波数（ＭHz）−10.7〕のデータとなり、VCO
１１は受信周波数（ＭHz）−10.7MHzの発振を行
なう。 In this state, the tuner operates in the same manner as a conventional tuner and receives radio waves received by the receiving antenna. If the intermediate frequency is now 10.7MHz, the set value to the programmable counter is, for example, [reception frequency (MHz) - 10.7], and the VCO
11 performs oscillation at the reception frequency (MHz) -10.7MHz.
またこのとき表示器は受信周波数を表示してい
る。 At this time, the display is also displaying the reception frequency.
送受信切換スイツチSW1−1〜SW1−3を送信側
に切換えたときは、加算器１７にオーデイオ信号
源２０からのオーデイオ信号が供給され、またバ
ツフア増幅器１２の出力は送信回路２１に供給さ
れる。同時にプログラマブルカウンタは中間周波
数に対する補正が行なわれない。したがつてロー
パスフイルタ１６から加算器１７を介して制御さ
れるVCO１１は受信時に指定した受信周波数と
同一周波数の発振を行なうべくPLL回路４はロ
ツクされる。しかるに加算器１７にはオーデイオ
信号源２０からのオーデイオ信号が供給されてい
るため、VCO１１の発振出力は受信周波数と同
一の周波数の搬送波をオーデイオ信号で変調した
被変調波が、バツフア増幅器１２を介して送信回
路２１に供給され、送信アンテナを介して送信さ
れる。 When the transmission/reception changeover switches SW 1 - 1 to SW 1 - 3 are switched to the transmission side, the audio signal from the audio signal source 20 is supplied to the adder 17, and the output of the buffer amplifier 12 is supplied to the transmission circuit 21. Ru. At the same time, the programmable counter is not compensated for the intermediate frequency. Therefore, the PLL circuit 4 is locked so that the VCO 11 controlled by the low-pass filter 16 via the adder 17 oscillates at the same frequency as the reception frequency designated at the time of reception. However, since the adder 17 is supplied with the audio signal from the audio signal source 20, the oscillation output of the VCO 11 is a modulated wave obtained by modulating a carrier wave of the same frequency as the receiving frequency with the audio signal, which is transmitted via the buffer amplifier 12. The signal is supplied to the transmitting circuit 21 and transmitted via the transmitting antenna.
またこのとき表示器１９は送信周波数（受信周
波数と同一）を表示している。 Also, at this time, the display 19 is displaying the transmission frequency (same as the reception frequency).
以上説明した如く本考案によれば、送受信切換
スイツチの送信指示により受信していた周波数と
同一の送信が行なえ、また送信から受信に切替え
ることにより送信周波数と同一周波数の受信が行
なえて、所謂トランシーブ操作が行なえる。 As explained above, according to the present invention, it is possible to perform transmission at the same frequency as the receiving frequency by the transmission instruction of the transmitting/receiving switch, and it is also possible to receive at the same frequency as the transmitting frequency by switching from transmitting to receiving. Can be operated.
図は本考案の一実施例の構成を示すブロツク図
である。
３……混合段、４……局部発振器、５……復調
段、１１……VCO、１２……バツフア増幅器、
１３……分周器、１４……基準発振器、１５……
位相比較器、１６……ローパスフイルタ、１７…
…加算器、２０……オーデイオ信号源、２１……
送信回路。
The figure is a block diagram showing the configuration of an embodiment of the present invention. 3...Mixing stage, 4...Local oscillator, 5...Demodulation stage, 11...VCO, 12...Buffer amplifier,
13... Frequency divider, 14... Reference oscillator, 15...
Phase comparator, 16...Low pass filter, 17...
... Adder, 20 ... Audio signal source, 21 ...
Transmission circuit.
Claims (1)
おいて、受信周波数が送信のときのロツク周波数
となるべくPLL回路のプログラマブルカウンタ
の分周比を切替える手段と、前記PLL回路の電
圧制御発振器の出力が送信のときのみ供給される
送信回路と、前記PLL回路の電圧制御発振器に
供給される位相比較器の出力に送信のときのみオ
ーデイオ信号を加算する加算手段とを備えてなる
ことを特徴とする送受信機。 In a receiver in which the local oscillator is a PLL circuit, there is provided a means for switching the division ratio of a programmable counter of the PLL circuit so that the reception frequency is the lock frequency for transmission, and a means for switching the division ratio of a programmable counter of the PLL circuit so that the reception frequency is the lock frequency for transmission, 1. A transmitter/receiver comprising: a transmitting circuit that is supplied only when transmitting data; and an adding means that adds an audio signal to the output of a phase comparator that is supplied to a voltage controlled oscillator of the PLL circuit only when transmitting.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18368783U JPS6093344U (en) | 1983-11-30 | 1983-11-30 | transceiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18368783U JPS6093344U (en) | 1983-11-30 | 1983-11-30 | transceiver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6093344U JPS6093344U (en) | 1985-06-26 |
| JPH0141250Y2 true JPH0141250Y2 (en) | 1989-12-06 |
Family
ID=30397484
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18368783U Granted JPS6093344U (en) | 1983-11-30 | 1983-11-30 | transceiver |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6093344U (en) |
-
1983
- 1983-11-30 JP JP18368783U patent/JPS6093344U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6093344U (en) | 1985-06-26 |
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