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JPH0134512B2 - - Google Patents

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Publication number
JPH0134512B2
JPH0134512B2 JP6891783A JP6891783A JPH0134512B2 JP H0134512 B2 JPH0134512 B2 JP H0134512B2 JP 6891783 A JP6891783 A JP 6891783A JP 6891783 A JP6891783 A JP 6891783A JP H0134512 B2 JPH0134512 B2 JP H0134512B2
Authority
JP
Japan
Prior art keywords
synchronization signal
vertical synchronization
frequency
counter
generation circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP6891783A
Other languages
Japanese (ja)
Other versions
JPS59193680A (en
Inventor
Junji Sakamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP6891783A priority Critical patent/JPS59193680A/en
Publication of JPS59193680A publication Critical patent/JPS59193680A/en
Publication of JPH0134512B2 publication Critical patent/JPH0134512B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00Details of colour television systems
    • H04N9/64Circuits for processing colour signals
    • H04N9/642Multi-standard receivers

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Color Television Systems (AREA)
  • Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)

Description

【発明の詳細な説明】 (イ) 産業上の利用分野 本発明は、NTSC、PAL又はSECAM等の異方
式の複合映像信号を受信するテレビ受像機又は記
録再生するビデオテープレコーダ(以下VTRと
称する)或は再生用装置としてのビデオデイスク
(以下VDと称する)において、前述のNTSC方
式の同信号を受信又は再生しているかを自動的に
判別するテレビ放送方式の自動判別方式に関す
る。
[Detailed description of the invention] (a) Industrial application field The present invention is directed to a television receiver that receives composite video signals of different formats such as NTSC, PAL, or SECAM, or a video tape recorder (hereinafter referred to as VTR) that records and plays back composite video signals of different formats such as NTSC, PAL, or SECAM. ) or a video disc (hereinafter referred to as VD) as a playback device, relates to an automatic television broadcast system discrimination method for automatically determining whether the above-mentioned NTSC signal is being received or played back.

(ロ) 従来技術 従来のテレビ受像機又はVTR等において、受
像又は再生している複合映像信号が、例えば
NTSC方式かPAL方式かにより各放送方式に対
応して設計したテレビ受像機又はVTR等を用い
るか、1台のテレビ受像機又はVTRに、両方式
を受像又は再生可能な回路を具備せしめ、切換ス
イツチにてその都度切換えを行つていたので特に
両方式の混在地域では極めて不便であつた。
(b) Prior art In a conventional television receiver or VTR, etc., the composite video signal received or reproduced is, for example,
Depending on whether the system is NTSC or PAL, you can use a TV receiver or VTR designed for each broadcasting system, or equip one TV receiver or VTR with a circuit that can receive or play back both systems. This was extremely inconvenient, especially in areas where both types were used, as the switch had to be changed each time.

(ハ) 発明の目的 本発明は、NTSC方式又はPAL方式等の水平
走査線数又はフイールド周波数の異なる複数の方
式のテレビ放送を受像又は記録された信号を再生
する際、複合映像信号から前記の方式のうちいず
れの方式かを自動的に判別し得るテレビ放送方式
の自動判別方式を提供することを目的とする。
(c) Purpose of the Invention The present invention provides the above-mentioned method from a composite video signal when reproducing a signal received or recorded from a plurality of television broadcasting systems having different numbers of horizontal scanning lines or field frequencies, such as the NTSC system or the PAL system. An object of the present invention is to provide an automatic discrimination method for television broadcasting methods that can automatically determine which method is used among the TV broadcasting methods.

(ニ) 発明の構成 水平同期信号周波数又は、その整数倍の周波数
の信号を分周し、第1放送方式の第1垂直同期信
号の到来が予想される期間中、第1分周出力信号
を発生するとともに、第2放送方式の第2垂直同
期信号の到来が予想される期間中、第2分周出力
信号を発生するカウンタと、各種放送方式に対応
し、前記カウンタをリセツトする為に用いられる
垂直同期信号を発生する垂直同期信号発生回路と
前記カウンタの第1分周出力信号と前記垂直同期
信号発生回路からの垂直同期信号との論理積をと
る第1アンドゲートと、前記カウンタの第2分周
出力信号と前記垂直同期信号発生回路からの垂直
同期信号との論理積をとる第2アンドゲートと、
前記第1及び第2アンドゲートの出力信号の値を
保持する保持手段とから成り、前記保持手段の出
力によりテレビ放送方式を判別することを特徴と
する。
(d) Structure of the invention A signal having a horizontal synchronizing signal frequency or an integral multiple thereof is frequency-divided, and the first frequency-divided output signal is transmitted during a period in which the first vertical synchronizing signal of the first broadcasting system is expected to arrive. a counter that generates a second frequency-divided output signal during a period in which the second vertical synchronization signal of the second broadcasting system is expected to arrive; a vertical synchronization signal generation circuit that generates a vertical synchronization signal, a first AND gate that performs an AND of a first frequency-divided output signal of the counter, and a vertical synchronization signal from the vertical synchronization signal generation circuit; a second AND gate that performs an AND of the frequency-divided-by-2 output signal and the vertical synchronization signal from the vertical synchronization signal generation circuit;
and holding means for holding the values of the output signals of the first and second AND gates, and the television broadcast system is determined based on the output of the holding means.

(ホ) 実施例 第1図は、本発明のテレビ放送方式の自動判別
方式を示すブロツク図、第2図は第1図を説明す
るための波形図を示す。
(E) Embodiment FIG. 1 is a block diagram showing an automatic discrimination method for television broadcasting systems of the present invention, and FIG. 2 is a waveform diagram for explaining FIG. 1.

次に図面に従つて本発明を説明すると、第1図
においてはクロツク信号発生回路、2はカウン
タ、は垂直同期信号発生回路、はANDゲー
ト5,6を有するゲート回路、7はフリツプフロ
ツプ(F/F)等より成るメモリ、8,9は判別
出力端子、10はORゲートを示す。第2図イは
前記クロツク信号発生回路の出力波形、ロ,ニは
各々異方式、例えばNTSC方式とPAL方式の各
複合映像信号より導出した垂直同期信号発生回路
の出力波形、ハ,ホは前記ロ,ニに対応するカウ
ンタの出力波形、ヘ,トはメモリ7の出力波形、
チはカウンタ2と接続されたORゲート9の入力
波形を示す。
Next, the present invention will be explained according to the drawings. In FIG. 1, 1 is a clock signal generation circuit, 2 is a counter, 3 is a vertical synchronization signal generation circuit, 4 is a gate circuit having AND gates 5 and 6, and 7 is a flip-flop. (F/F), etc., 8 and 9 are discrimination output terminals, and 10 is an OR gate. In Figure 2, A is the output waveform of the clock signal generation circuit, B and D are the output waveforms of the vertical synchronization signal generation circuit derived from composite video signals of different systems, for example, NTSC and PAL systems, and C and H are the output waveforms of the vertical synchronization signal generation circuit. Output waveforms of the counters corresponding to B and D, F and G are output waveforms of the memory 7,
1 shows the input waveform of the OR gate 9 connected to the counter 2.

先ず放送方式の一例としてNTSC方式とPAL
方式を上げて説明すると、第1図のクロツク信号
発生回路の出力VHが第2図イに示す如く現わ
れ、カウンタ2に加わる。
First of all, NTSC and PAL are examples of broadcasting systems.
To explain the system in detail, the output VH of the clock signal generating circuit 1 shown in FIG. 1 appears as shown in FIG. 2A and is added to the counter 2.

このとき垂直同期信号発生回路からの垂直同
期信号が、NTSC方式の複合映像信号からの導出
したものである場合、周期は1/60秒でカウンタ2
によつてクロツク信号VHのパルスをカウントし、
水平走査線数が1フイールド当り525本/2とな
つているので、前記カウンタ2の出力を例えば
256〜272(n1=256、22=272)の間に発生するよ
うに設定しておくと、この間に受信信号又は再生
信号中の垂直同期信号VVが存在し、第2図ハに
示すタイミング(n0本目)でカウンタ2をリセツ
トし、従つて第2図ハの実線で示す波形の出力が
カウンタ2から得られ、これに伴つてメモリ7の
出力として第2図ハに示す出力が現われる。
At this time, if the vertical synchronization signal from the vertical synchronization signal generation circuit 3 is derived from an NTSC composite video signal, the period is 1/60 seconds and the counter 2
counts the pulses of the clock signal V H by
Since the number of horizontal scanning lines is 525/2 per field, the output of counter 2 is, for example,
If it is set to occur between 256 and 272 (n 1 = 256, 2 2 = 272), the vertical synchronization signal V V in the received signal or reproduced signal will exist during this period, and the result will be shown in Figure 2 C. The counter 2 is reset at the timing shown (n 0th line), and the output of the waveform shown by the solid line in FIG. 2C is obtained from the counter 2. Along with this, the output shown in FIG. appears.

一方垂直同期信号発生回路からの垂直同期信
号が、PAL方式の複合映像信号から導出したも
のである場合、周期は1/50秒でカウンタ2によつ
てクロツク信号VHのパルスをカウントし、水平
走査線が1フイールド当り625/2本となつてい
るので、前記カウンタ2の出力を例えば300〜325
(n1′=300、n2′=325)の間に発生するように設定
しておくと、この間に受信信号又は再生信号中の
垂直同期信号VVが存在し、第2図ニに示すタイ
ミング(n0′本目)でカウンタ2をリセツトし、
従つて第2図ホの実線で示す波形となる。従つて
これに伴い、メモリ7の出力として第2図トに示
す波形が得られる。
On the other hand, if the vertical synchronization signal from the vertical synchronization signal generation circuit 3 is derived from a PAL system composite video signal, the period is 1/50 seconds and the pulses of the clock signal V H are counted by the counter 2. Since the number of horizontal scanning lines is 625/2 per field, the output of the counter 2 is, for example, 300 to 325.
(n 1 ′ = 300, n 2 ′ = 325), the vertical synchronization signal V V in the received signal or reproduced signal exists during this period, as shown in Figure 2 D. Reset counter 2 at the timing (n 0 'th),
Therefore, the waveform is shown by the solid line in FIG. 2E. Accordingly, the waveform shown in FIG. 2G is obtained as the output of the memory 7.

なおNTSC方式又はPAL方式の該当タイミン
グにてて垂直同期信号VVが到来しなかつた場合
(いずれの場合も欠落)、カウンタ2の出力は第2
図ホの破線に示すn2′のタイミングで立下り、こ
の場合カウンタ2の出力VA(第2図チによりOR
ゲート10を介してリセツトがかけられる。
Note that if the vertical synchronization signal V V does not arrive at the relevant timing of the NTSC system or PAL system (missing in either case), the output of counter 2 will be the second one.
In this case, the output V A of counter 2 (OR
A reset is applied via gate 10.

前述の第1図の端子8に現われる電圧VN(第2
図ヘ)がNTSC用の制御電圧として現われ、この
とき端子9はローレベルのままの状態、一方端子
9に現われる電圧VP(第2図ト)がPAL用の制御
電圧として現われ、このとき端子9はローレベル
のままの状態に保持され、前記制御電圧VN又は
VPによつてセツトを自動的にNTSC方式又は
PAL方式に切換えることができる。
The voltage V N (second
Figure F) appears as a control voltage for NTSC, and at this time terminal 9 remains at a low level, while voltage V P appearing at terminal 9 (Figure 2 G) appears as a control voltage for PAL, and at this time terminal 9 remains at a low level. 9 is kept at a low level, and the control voltage V N or
VP automatically sets the NTSC or
You can switch to PAL format.

前述のクロツク信号発生回路としては、専用の
同回路即ちVTR又はビデオカメラの如く、テレ
ビ放送波ではなく、自己の発振回路によるもの、
テレビ受像機の如く、同期分離回路を備え、その
出力による場合のいずれでも良く、又一例として
NTSC方式とPAL方式の例について説明したが、
SECAM方式との判別も同様である。
The above-mentioned clock signal generation circuit may be a dedicated circuit such as a VTR or video camera, which uses its own oscillation circuit instead of using television broadcast waves.
Like a television receiver, it may be equipped with a synchronization separation circuit and use its output.
I explained examples of NTSC and PAL systems, but
The same is true for discrimination with the SECAM method.

(ヘ) 発明の効果 本発明のテレビ放送方式の自動判別方式によれ
ば、受信された放送波又は磁気テープ等に記録さ
れた複合映像信号の方式が、例えばNTSC方式と
PAL方式の走査線数の差異即ち525本と625本及
び垂直周期の差異即ち1/60秒と1/50秒を検出し
得、簡単な構成で所期の目的が達成できる。
(F) Effects of the Invention According to the automatic television broadcast system discrimination system of the present invention, if the system of the received broadcast wave or composite video signal recorded on a magnetic tape etc. is, for example, NTSC system or
It is possible to detect the difference in the number of scanning lines of the PAL system, ie, 525 lines and 625 lines, and the difference in the vertical period, ie, 1/60 second and 1/50 second, and achieve the desired purpose with a simple configuration.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明のテレビ放送方式の自動判別方
式のブロツク図、第2図は第1図における各部波
形図を示す。 主な図番の説明、1…クロツク信号発生回路、
2…カウンタ、3…垂直同期信号発生回路、4…
ゲート回路、7…メモリ。
FIG. 1 is a block diagram of an automatic discrimination system for a television broadcasting system according to the present invention, and FIG. 2 is a waveform diagram of each part in FIG. 1. Explanation of main drawing numbers, 1...Clock signal generation circuit,
2...Counter, 3...Vertical synchronization signal generation circuit, 4...
Gate circuit, 7...memory.

Claims (1)

【特許請求の範囲】[Claims] 1 水平同期信号周波数又はその整数倍の周波数
の信号を分周し、第1放送方式の第1垂直同期信
号の到来が予想される期間中、第1分周出力信号
を発生するとともに、第2放送方式の第2垂直同
期信号の到来が予想される期間中、第2分周出力
信号を発生するカウンタと、各種放送方式に対応
し、前記カウンタをリセツトする為に用いられる
垂直同期信号を発生する垂直同期信号発生回路
と、前記カウンタの第1分周出力信号と前記垂直
同期信号発生回路からの垂直同期信号との論理積
をとる第1アンドゲートと、前記カウンタの第2
分周出力信号と前記垂直同期信号発生回路からの
垂直同期信号との論理積をとる第2アンドゲート
と、前記第1及び第2アンドゲートの出力信号の
値を保持する保持手段とから成り、前記保持手段
の出力によりテレビ放送方式を判別することを特
徴としたテレビ放送方式の自動判別方式。
1 Divide the frequency of the horizontal synchronization signal frequency or a signal with a frequency that is an integer multiple thereof, and generate the first frequency-divided output signal during the period in which the arrival of the first vertical synchronization signal of the first broadcasting system is expected; A counter that generates a second frequency-divided output signal during a period when the second vertical synchronization signal of the broadcasting system is expected to arrive, and a vertical synchronization signal that is used to reset the counter in correspondence with various broadcasting systems. a vertical synchronization signal generation circuit, a first AND gate that takes an AND of a first frequency-divided output signal of the counter and a vertical synchronization signal from the vertical synchronization signal generation circuit, and a second AND gate of the counter;
a second AND gate that performs a logical product of the frequency-divided output signal and the vertical synchronization signal from the vertical synchronization signal generation circuit; and a holding means for holding the values of the output signals of the first and second AND gates; An automatic determination method for a television broadcasting method, characterized in that the television broadcasting method is determined based on the output of the holding means.
JP6891783A 1983-04-18 1983-04-18 Automatic discriminating system of television broadcast system Granted JPS59193680A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6891783A JPS59193680A (en) 1983-04-18 1983-04-18 Automatic discriminating system of television broadcast system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6891783A JPS59193680A (en) 1983-04-18 1983-04-18 Automatic discriminating system of television broadcast system

Publications (2)

Publication Number Publication Date
JPS59193680A JPS59193680A (en) 1984-11-02
JPH0134512B2 true JPH0134512B2 (en) 1989-07-19

Family

ID=13387481

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6891783A Granted JPS59193680A (en) 1983-04-18 1983-04-18 Automatic discriminating system of television broadcast system

Country Status (1)

Country Link
JP (1) JPS59193680A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0620278B2 (en) * 1987-05-18 1994-03-16 三菱電機株式会社 Synchronous frequency mode judgment circuit
JP2574356B2 (en) * 1988-01-19 1997-01-22 松下電器産業株式会社 Broadcast system identification device
JPH0731656Y2 (en) * 1988-06-06 1995-07-19 日本電気ホームエレクトロニクス株式会社 Television signal type automatic determination circuit

Also Published As

Publication number Publication date
JPS59193680A (en) 1984-11-02

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