JPH01241161A - Solid-state image sensing device - Google Patents

Abstract

PURPOSE:To prevent the stagnation of electric charge below a read gate and suppress the development of residual images, by making a p-type impurity concentration thin towards the direction of signal charge transmission. CONSTITUTION:There are different plane forms of a channel stopper 20 and this device makes the channel width of a read gate part 21 wide towards the direction of signal charge transmission. The wider the channel width becomes, the less crosswise diffusion effects of a p<+> type layer at the channel stopper 20 interact each other and a p-type impurity concentration becomes thin. This approach cancels an impurity concentration change in a channel which arises from crosswise diffusion of an n-type layer in an accumulation region 17 which is the cause for the development of a residual image. Thus, the development of residual images are suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an imaging device, and particularly to a solid-state imaging device using a semiconductor.

[Conventional technology]

Conventionally, a CCD type solid-state image sensor is known as a solid-state image sensor. For details on this solid-state image sensor, see, for example, the literature: Yanai et al.: ``Proceedings of the National Conference of the Television Society, 1986 ``2/3 inch 280,000 pixel index
-CCD image sensor".

Figure 2 shows a conventional interline CCD solid-state image sensor (
This figure shows an example of a circuit for IL-CCD. The light receiving sections 7 are regularly arranged in the horizontal and vertical directions. A vertical COD register 1 is installed adjacent to one side of the row of light receiving sections 7.
1 is provided, and a readout gate 8 is provided between the vertical CCDL/register 11 and the light receiving section 7. A horizontal shift register 1 is installed at the end of the vertical CCD register 11 in the charge transfer direction.
2 is provided. Next, the operation of this ILCCD will be briefly explained. Signal charges generated by photoelectric conversion are stored in the light receiving section 7. The readout gate 8 opens every field period or frame period, and the signal charge is transferred to the light receiving section 7.
The data is then transferred to the heavy CCD register 11. The signal charge is then transferred to the output amplifier 13 through the vertical COD register 11 and the horizontal COD register 12, and is output to the outside of the device.

FIG. 3 is a plan view of the two-dimensionally arranged repeating cell section 10 of the IL-CCD shown in FIG. The light receiving section 17 and the vertical COD register 19 are separated. A portion 15 surrounded by a solid line is the first polycrystalline silicon electrode.

The first polycrystalline silicon electrode 15 is connected to the vertical CCD register 19
It is used as an electrode. Another portion 16 surrounded by a solid line is the second polycrystalline silicon electrode. The second polycrystalline silicon electrode 16 is used as an electrode of the vertical COD register 19 and an electrode of the read gate section 18. What parts are not covered with the first and second polycrystalline silicon electrodes 15, 16 and are not the channel topper 14? i7
This is M area 17.

FIG. 4 is a sectional view taken along line AA' in FIG. 3. A p-type well 5 is formed on the main surface of the n-type silicon substrate 6, with a shallow junction depth in the storage region 17 and a deep junction depth in the vertical COD register 19. Channel Totsuba 1
4 consists of P ten areas 4. In the storage region 17, an n-type region 2 is formed in a P-type well 5 with a shallow junction depth. Signal charges are accumulated in the reverse bias capacitance of the pn junction between the n-type region 2 and the p-type well 5 or the P-type region 4. The vertical CCD register 19 is of a buried type and consists of an n-type buried) PJ3. As mentioned above, there is a p-type well 5. p+ region 4, n-type region 2. A buried layer 3 is formed.

A second polycrystalline silicon electrode 1 is formed on the read gate section 18 and the vertical COD register 19 with a thermal oxide film 80 interposed therebetween.

In this IL-COD, the storage region 17 has a shallow junction depth.
By forming it within the mold well 5, the blooming phenomenon is suppressed. Furthermore, afterimages are suppressed by setting the impurity concentration of the n-type region 2 of the storage region 17 to such a concentration that the n-type region 2 is completely depleted when reading out the stored charge.

FIG. 5 shows the potential distribution of the signal charge transfer path 93 when reading signal charges of the element shown in FIG. 4. Signal r transferred to n-type region 2 of storage region 17
The d load is transferred to the vertical COD register 3 via the read gate section 95. At this time, the potential of the storage region 84 is fixed to the depletion potential of the n-type layer 2. The potential of the read gate portion 85 forms a barrier in the signal charge read direction due to a change in impurity concentration due to the lateral diffusion 94 of the n-type layer 2 in the storage region. Therefore, a portion 90 of the signal charge 91 transferred to the vertical CCD register section 86 remains under the readout gate 85, causing an afterimage. Here, 87 is a distance N1xμm in the signal charge transfer direction, 88 is the potential VP (V) of the transfer path, 89 is the potential of the light receiving section, and 92 is a p-type well layer.

[Problem to be solved by the invention]

In the above-mentioned conventional technology, no consideration was given to the stagnation of charges under the readout gate, and there was a problem of generation of an afterimage.

An object of the present invention is to prevent charge from stagnation under the readout gate and to suppress afterimages.

[Means to solve the problem]

The above object is achieved by reducing the P-type impurity concentration in the channel under the read gate in the direction of signal charge transfer.

[Function] Reducing the p-type impurity concentration below the readout gate toward the signal readout direction works to cancel out changes in impurity concentration due to lateral diffusion of the n-type layer in the storage region. This suppresses the formation of a potential barrier due to a change in impurity concentration in the channel under the readout gate, so that signal charges remain under the readout gate, thereby suppressing the generation of afterimages.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. A schematic plan view of an Elm CCU according to an embodiment of the present invention is the same as FIG. 2, and FIG. 1 is a plan view of a two-dimensionally arranged repeating cell portion. In FIG. 1, components having the same functions as those in FIG. 3 are indicated by the same symbols. A cross-sectional view of a repeating cell portion according to an embodiment of the present invention is approximately the same as FIG. 4.

The difference between the embodiment of the present invention shown in FIG. 1 and the conventional example shown in FIG. 3 is the planar shape of the channel stopper 20. The channel width of the read gate section 21 is widened in the direction of signal charge transfer. The wider the channel width, the less the influence of the lateral diffusion of the P layer of the channel stopper 20, and the lower the p-type impurity concentration in the channel.

This makes it possible to cancel out the change in impurity concentration in the channel due to the lateral diffusion of the n-type layer 2 in the accumulation region 17, which is the cause of the afterimage, thereby suppressing the afterimage.

Another embodiment of the present invention will be described using FIG. 7.

The embodiment of the present invention shown in FIG. 7 differs from the embodiment shown in FIG. 1 in the planar shape of the channel stopper 22 and the structure of the polycrystalline silicon electrode. The structure of the channel stopper 22 is similar to that shown in FIG.
The channel width is made wider in the signal charge transfer direction. As a result, as in the case of the embodiment shown in FIG.
It has the effect of suppressing afterimages. In this embodiment, unlike FIG. 1, by using diagonal lines in the planar shape of the channel stopper 22, the channel width of the read gate portion 25 can be changed continuously. Next, we will discuss the differences in the structure of polycrystalline silicon electrodes. The difference from the embodiment shown in FIG. 1 is that third polycrystalline silicon electrodes 23 and 24 are newly provided.

Here, the third polycrystalline silicon electrode is formed in the first layer. The third polycrystalline silicon electrode is the shaded area 23, 24 in FIG. One of the third polycrystalline silicon electrodes 24 is used as a read gate electrode, and the other third polycrystalline silicon electrode 23 is used as an element isolation electrode. This allows vertical COD register 15
．． 16 pulse shape becomes simple. In addition, separation between elements becomes easier. Note that 100 and 101 are vertical COD gate electrodes.

Another embodiment of the present invention will be described using FIG. 8.

The embodiment of the present invention shown in FIG. 8 differs from the embodiment shown in FIG. 1 in the planar shape of the channel stopper 27 and the blooming phenomenon suppressing structure.

The structure of the channel stopper 27 is similar to that shown in FIG. 1, so that the channel width of the read gate portion 29 is made wider in the signal charge transfer direction. As a result, as in the case of the embodiment shown in FIG. 1, there is an effect of suppressing afterimages. In this embodiment, unlike FIG. 7, manufacturing variations can be reduced by using an acute angle in the planar shape of the channel stopper 27. Next, we will discuss the differences in the blooming phenomenon suppression structure. The difference from the embodiment shown in FIG. 1 is that a transparent electrode 35, for example made of a polycrystalline silicon thin film or ITO (indium tin oxide), is repeatedly provided on a part or the entire surface of the cell section, and a stripe shape, n
The ten layers 32 and the channel section 33 for sweeping out excess charge are now provided.

Note that one of the channel portions 33 closer to the light receiving portion 30
An n-type layer 34 is provided in the portion. A sectional view taken along line BB' in FIG. 8 is shown in FIG. 9. The difference from the cross-sectional view of the conventional example shown in FIG. Of which n
A P-type layer 37 is formed near the type layer 38. A transparent type j@44 is formed on these n-type layers 36 and 38 and the channel portion 39 with a thermal oxide film 81 interposed therebetween. Further, the p-type well layer 43 has a constant junction depth,
N-type r in vertical COD channel section! An n-type layer 42 is provided to cover I41.

In this IL-CCD, by controlling the potential of the transparent electrode 44, excess charge generated in the n-type layer 38, which becomes a photodiode, is swept out through the channel portion 39 to the n-type layer 36, thereby suppressing the blooming phenomenon. . By adopting this method, the P-type well layer 43 of the photodiode can be made deep, and the sensitivity can be improved. In addition, by canceling the impurity concentration change in the channel 39 due to the lateral diffusion of the n-type layer 38 by the p-type layer 37, a higher potential than when suppressing the blooming phenomenon is applied to the transparent electrode 44, and the n-type of the photodiode is removed without residual charge. layer 38
Accumulated charges can be swept out to the n♦ layer 36. This allows a so-called shutter operation with variable sensitivity to be performed by changing the signal accumulation time. Furthermore, by covering the n-type layer 41 of the vertical COD channel with the p-type layer 42 having a higher concentration than the p-type well layer 43, it is possible to prevent unnecessary charges from flowing into the n-type layer 41 and suppress the smear phenomenon. can.

Another embodiment of the present invention will be described using FIG. 6.

The embodiment of the present invention shown in FIG. 6 differs from the embodiment shown in FIG. 8 in the impurity structure of the read channel section 55 and the blooming suppression structure. The impurity structure of the read channel portion 55 narrows the width of the p-type layer 156 in the signal transfer direction. The narrower the width, the greater the influence of lateral diffusion, and the lower the p-type impurity concentration within the channel 55.

As a result, as in the case of the embodiment shown in FIG. 1, there is an effect of suppressing afterimages. Note that a portion 62 surrounded by a dotted line is a p-layer for element isolation. Next, we will discuss the differences in Brussing suppression structures. The difference from the embodiment shown in FIG. 8 is that an excess charge sweep gate 61 is formed of a third polycrystalline silicon layer, and an n+ layer 6o serves as an excess charge sweep drain.
The opening portion 58 is widened by providing an independent layer 60 and electrically connecting the gate 61. FIG. 10 shows a cross section taken along line cc' in FIG. 6.

The difference from the cross-sectional view of the embodiment shown in FIG. 9 is that the thermal oxide film 82 on the nx layer 83, which serves as the excess charge drain, is removed to connect to the excess charge drain gate 47. Further, a p-type layer 48 is provided on an n-type layer 49 that serves as a photodiode. This prevents the silicon/thermal oxide film 82 interface from becoming depleted and increasing dark current. Note that 46 is a readout gate electrode;
45 is a vertical CCD gate electrode.

Further, in FIG. 6, a P-type layer 59 whose width becomes narrower toward the signal charge transfer direction is introduced into the excess charge sweep-out channel portion 57. Thereby, as in the case of the readout channel 55 described above, there is an effect of suppressing afterimages. Unlike the p-type layer 56 in the readout channel described above, the P-type layer 59 of this example does not have an acute angle in its planar shape, so that manufacturing variations can be reduced.

Another embodiment of the present invention will be described using FIG. 11. 1st
The embodiment of the present invention shown in FIG. 1 differs from the embodiment shown in FIG.
These are the planar shape of the mold layer 65 and the planar shape of the p-type layer 68 which becomes a photodiode. The p-type layer 65 in the excess charge sweeping channel 64 has a width narrowing from the storage region 67 toward the signal transfer direction, as in FIG. As a result, as in the case of the embodiment shown in FIG. 6, there is an effect of suppressing afterimages. Further, in this embodiment, the planar structure of the p-type layer 68 which becomes a photodiode is removed in the readout channel portion 6:3, and the width of the removed portion is narrower than the width of the readout channel 63. Due to the lateral diffusion of the p-type layer 68, the p-type concentration becomes thinner in the read channel 63 toward the signal transfer direction. As a result, as in the case of the embodiment shown in FIG. 6, there is an effect of suppressing afterimages.

The structures described above in each embodiment of the present invention can of course be applied to the read channel section and the excess charge sweeping channel section of any embodiment.

The present invention can be applied to both -dimensional and two-dimensional sensors, such as frame transfer type COD image sensors, MO5 type image sensors, and CPD type image sensors.

〔Effect of the invention〕

According to the present invention, by thinning the p-type impurity concentration toward the signal charge transfer direction in the readout channel and the excess charge sweep-out channel, it is possible to eliminate charge stagnation due to non-uniformity of the impurity concentration within the channel. , has the effect of suppressing afterimages.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a planar layout of a pixel section in an embodiment of the present invention, FIG. 2 is a diagram showing a circuit configuration of a conventional CCD type solid-state image sensor, and FIG. 3 is a plan view of a pixel section in FIG. 2. A diagram showing the layout, FIG. 4 is a diagram showing the cross-sectional structure taken along line A-A' in FIG. 3, FIG. 5 is a diagram showing FIG. 4, and FIG. 9 is a diagram showing B-B in FIG.
FIG. 10 is a diagram showing a cross-sectional structure taken along line cc' in FIG. 6.

Claims (1)

[Claims] 1. A solid-state imaging device having a pixel array including a photoelectric conversion element and a signal charge readout element, and a sequential and vertical scanning element for scanning the pixel array, wherein the signal charge readout element is a MOS type. The p-type impurity concentration in the channel is made thinner from the photoelectric conversion element side toward the signal charge readout direction so that a potential depression is not formed in the channel of the transistor from the photoelectric conversion element side toward the signal charge readout direction. A solid-state imaging device characterized by: 2. In claim 1, a MOS transistor for sweeping out excess charge is newly provided in the pixel array, and p-type impurity in the channel of this transistor is directed from the photoelectric conversion element side to the direction of sweeping out the excess charge. A solid-state imaging device characterized by being thinner toward the front.