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JPH01244634A - Production device for semiconductor wafer - Google Patents

Production device for semiconductor wafer

Info

Publication number
JPH01244634A
JPH01244634A JP63072722A JP7272288A JPH01244634A JP H01244634 A JPH01244634 A JP H01244634A JP 63072722 A JP63072722 A JP 63072722A JP 7272288 A JP7272288 A JP 7272288A JP H01244634 A JPH01244634 A JP H01244634A
Authority
JP
Japan
Prior art keywords
wafer
carrier
semiconductor
wafer carrier
slot
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63072722A
Other languages
Japanese (ja)
Inventor
Kenji Kiriyama
桐山 建二
Kazuhiro Mitsui
三井 和浩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TERU BARIAN KK
Tel Varian Ltd
Original Assignee
TERU BARIAN KK
Tel Varian Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TERU BARIAN KK, Tel Varian Ltd filed Critical TERU BARIAN KK
Priority to JP63072722A priority Critical patent/JPH01244634A/en
Publication of JPH01244634A publication Critical patent/JPH01244634A/en
Pending legal-status Critical Current

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  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

PURPOSE:To remove wafer extraction operation to an unnecessary slot such as an empty slot, to quicken wafer extraction operation and to improve the throughput capacity of a device by previously identify whether or not semiconductor wafers are present regarding all slots in a wafer carrier and beforehand storing the presence data of the wafers. CONSTITUTION:A wafer carrier 2 is loaded onto a carrier elevating base 8 in a load locking chamber, whether or not semiconductor wafers 6 at every slot 7 of the wafer carrier 2 are present is identified by a wafer position sensing mechanism 9 while lifting the carrier elevating base 8, and wafer housing information is stored previously in a memory. The wafer carrier 8 is elevated or lowered so that the specified semiconductor wafer 6 and a conveying arm 5a shows a height at the same level, and the extraction work of the semiconductor wafer 6 is conducted. Since the presence data of the semiconductor wafers in each slot in the wafer carrier is stored beforehand in the memory at that time, the extraction operation of the semiconductor wafers need not be performed to all slots in the wafer carrier, and extraction operation is shortened.

Description

【発明の詳細な説明】 [発明の構成] (産業上の利用分野) 本発明は半導体ウェハの製造装置に係り、特にロードロ
ック室を備えた半導体ウェハの製造装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Structure of the Invention] (Industrial Application Field) The present invention relates to a semiconductor wafer manufacturing apparatus, and more particularly to a semiconductor wafer manufacturing apparatus equipped with a load lock chamber.

(従来の技術) 従来より、半導体の製造装置例えばCVD装置等では、
多数の半導体ウェハを収容したウェハキャリアを予備真
空室となるロードロック室に収容し、この後、ウェハキ
ャリアから所定の半導体ウェハを搬送装置により取出し
て処理室内へと搬送する構成のものが知られている。
(Prior Art) Conventionally, in semiconductor manufacturing equipment such as CVD equipment,
There is a known structure in which a wafer carrier containing a large number of semiconductor wafers is stored in a load lock chamber that serves as a preliminary vacuum chamber, and then a predetermined semiconductor wafer is taken out from the wafer carrier by a transport device and transported into a processing chamber. ing.

ところで、近年の半導体製造工程では、多品種・少量生
産化に対応するために、半導体ウェハ毎の管理が行われ
ており、同じウェハキャリア内の半導体ウェハでも途中
で異なる製造工程に流れる場合があり、この場合には該
当するウェハキャリアのウェハ収容棚(以下、スロット
)は空の状態となる。このように近年の半導・体製造工
程では、同一キャリア内でも処理の異なる半導体ウェハ
が収容されているため、キャリアの各スロットと半導体
ウェハとを対応させて生産管理することが行われている
By the way, in recent semiconductor manufacturing processes, in order to respond to high-mix, low-volume production, each semiconductor wafer is managed, and even semiconductor wafers in the same wafer carrier may be transferred to different manufacturing processes midway through. In this case, the wafer storage shelf (hereinafter referred to as slot) of the corresponding wafer carrier becomes empty. As described above, in recent semiconductor manufacturing processes, semiconductor wafers that undergo different processing are housed within the same carrier, so production management is carried out by associating each slot of the carrier with a semiconductor wafer. .

このように、半導体ウェハの収容されていない空きスロ
ットを有するウェハキャリアがあるため、従来の半導体
製造装置では、ウェハ搬送装置によリウエハキャリアか
ら処理室内ヘウエハを搬送する過程で、ウェハ搬送装置
に所定の半導体ウェハが搭載されているか否かの検出を
行っていた。
As described above, since some wafer carriers have empty slots that do not accommodate semiconductor wafers, in conventional semiconductor manufacturing equipment, during the process of transporting wafers from the rewafer carrier to the processing chamber by the wafer transport equipment, the wafer transport equipment It was detected whether or not a predetermined semiconductor wafer was mounted.

このとき、ウェハ搬送装置に半導体ウェハが搭載されて
いなければ、該当するキャリアのスロットは空きスロッ
トであることがわかる。こうして、キャリアの全スロッ
トに対して半導体ウェハの有無の確認を行い該情報を記
憶し、処理終了後は元のスロットに半導体ウェハを収容
するように構成していた。
At this time, if no semiconductor wafer is mounted on the wafer transport device, it can be seen that the slot of the corresponding carrier is an empty slot. In this way, the presence or absence of semiconductor wafers is confirmed in all slots of the carrier, and this information is stored, and after the processing is completed, the semiconductor wafers are accommodated in the original slots.

(発明が解決しようとする課題) しかしながら、上述したような従来の半導体製造装置で
は、半導体ウェハの有無を確認するためには、空きスロ
ットに対してもウェハ搬送装置を動作させなければなら
ず、従って、全スロットに対してウェハ搬送装置を動作
させることになる。
(Problem to be Solved by the Invention) However, in the conventional semiconductor manufacturing apparatus as described above, in order to confirm the presence or absence of a semiconductor wafer, the wafer transport device must be operated even for empty slots. Therefore, the wafer transfer device is operated for all slots.

このようなウェハ検出動作は、半導体ウェハのキャリア
からの取出し速度の低下を招き、装置全体の処理能力低
下の原因になるという問題があった。
Such a wafer detection operation has the problem of causing a decrease in the speed at which the semiconductor wafer is taken out from the carrier, resulting in a decrease in the throughput of the entire apparatus.

本発明は、上述した問題点を解決するためになされたも
ので、予めウェハキャリアの全スロットについて半導体
ウェハの有無を確認し、これを記憶しておくことで、不
要なスロット、例えば空スロットに対するウェハ取出し
動作を排除してウェハ取出し作業の迅速化を可能とし、
装置の処理能力が向上する半導体ウェハの製造装置を提
供することを目的とする。
The present invention has been made to solve the above-mentioned problems, and by checking in advance the presence or absence of semiconductor wafers in all slots of a wafer carrier and storing this information, unnecessary slots, such as empty slots, can be It eliminates the wafer unloading operation and speeds up the wafer unloading process.
It is an object of the present invention to provide a semiconductor wafer manufacturing apparatus that improves the throughput of the apparatus.

[発明の構成] (課題を解決するための手段) 本発明の半導体ウェハの製造装置は、半導体ウェハを多
数収容したウェハキャリアをロードロック室内に収容し
、前記ウェハキャリアから所定の半導体ウェハを搬送機
構により処理室内に搬送して処理する半導体ウェハの製
造装置において、前記ウェハキャリア内の半導体ウェハ
の収容位置を予め検出するウェハ検出機構と、前記ウェ
ハ検出機構のウェハ位置情報を記憶する記憶機構と、前
記記憶機構に基づいて前記搬送機構の動作を制御する搬
送制御機構とを特徴とするものである。
[Structure of the Invention] (Means for Solving the Problems) A semiconductor wafer manufacturing apparatus of the present invention stores a wafer carrier containing a large number of semiconductor wafers in a load lock chamber, and transports a predetermined semiconductor wafer from the wafer carrier. A semiconductor wafer manufacturing apparatus that transports and processes semiconductor wafers into a processing chamber by a mechanism includes: a wafer detection mechanism that detects in advance a storage position of a semiconductor wafer in the wafer carrier; and a storage mechanism that stores wafer position information of the wafer detection mechanism. , a transport control mechanism that controls the operation of the transport mechanism based on the storage mechanism.

(作 用) 予めウェハキャリア内の半導体ウェハの収容状態を検出
してこれを記憶しておくことで、不要なウェハ取出し動
作が排除でき、ウェハの取出し作業が迅速に行え、装置
全体の処理能力の向上を図ることができる。
(Function) By detecting and storing the storage status of semiconductor wafers in the wafer carrier in advance, unnecessary wafer unloading operations can be eliminated, wafer unloading work can be performed quickly, and the processing capacity of the entire device can be increased. It is possible to improve the

(実施例) 以下、本発明をマルチチャンバ型CVD装置に適用した
一実施例について図を参照して説明する。
(Example) Hereinafter, an example in which the present invention is applied to a multi-chamber type CVD apparatus will be described with reference to the drawings.

中央部に配置されたウェハ搬送室1の一方には、これを
挟んで両側に夫々ウェハキャリア2を収容するロードロ
ック室3が配設されており、また、ウェハ搬送室1の他
方にはウェハ搬送室1を中心としてほぼ90度の角度間
隔をおいて3つのチャンバ4が同円周上に配設されてい
る。
A load-lock chamber 3 that accommodates wafer carriers 2 is disposed on both sides of the wafer transfer chamber 1 located in the center, and a load-lock chamber 3 that accommodates wafer carriers 2 is disposed on both sides of the wafer transfer chamber 1 located in the center. Three chambers 4 are arranged on the same circumference at angular intervals of approximately 90 degrees with the transfer chamber 1 as the center.

このような半導体製造装置における処理は、ウェハ搬送
室1の搬送装置、例えば搬送アーム5aによりウェハキ
ャリア2から所定の半導体ウェハ6を一枚取出してこれ
をチャンバ4側の搬送アーム5bへ移載し、この後処理
内容に合わせて複数のチャンバ4のうち所定のチャンバ
へと移送収容して処理を行う。例えば、第1のチャンバ
内で表面の自然酸化膜のエツチング処理を行った後、第
2のチャンバ内でCVD処理して薄膜を形成し、次の第
3のチャンバ内でN2ガス雰囲気下における熱処理を行
う。
Processing in such semiconductor manufacturing equipment involves taking out one predetermined semiconductor wafer 6 from the wafer carrier 2 using a transfer device in the wafer transfer chamber 1, such as the transfer arm 5a, and transferring it to the transfer arm 5b on the chamber 4 side. Then, according to the content of the post-processing, the material is transferred to a predetermined chamber among the plurality of chambers 4 and processed. For example, after etching the natural oxide film on the surface in a first chamber, CVD treatment is performed in a second chamber to form a thin film, and then heat treatment is performed in a N2 gas atmosphere in a third chamber. I do.

両ロードロック室3内に収容するウェハキャリア2は、
第2図に示すように、棚状に構成されており、各欄(以
下、スロット)7に夫々半導体ウェハ6が収容が収容さ
れている。
The wafer carrier 2 accommodated in both load lock chambers 3 is
As shown in FIG. 2, it has a shelf-like structure, and each column (hereinafter referred to as a slot) 7 accommodates a semiconductor wafer 6, respectively.

このウェハキャリア2は、キャリア昇降台8上に載置さ
れており、キャリア昇降台8の下降時に図示を省略した
キャリア搬送機構によりウェハキャリア2が搭載される
。処理作業時には、このウェハキャリア2を上昇させて
、処理対象の半導体ウェハ6とウェハ搬送機構の搬送ア
ーム5aとが同レベルとなるようにして取出しを行う。
The wafer carrier 2 is placed on a carrier elevating table 8, and when the carrier elevating table 8 is lowered, the wafer carrier 2 is mounted by a carrier transport mechanism (not shown). During processing, the wafer carrier 2 is raised so that the semiconductor wafer 6 to be processed and the transfer arm 5a of the wafer transfer mechanism are at the same level, and the wafer carrier 2 is taken out.

また、キャリア昇降台8の昇降路に沿って、例えばフォ
トセンサ等のウェハ位置検出機構9が上記キャリア昇降
台8の昇降路を水平または約手ススロット斜めに横切る
ように対向して配設されており、このウェハ位置検出機
構9により、ウェハキャリア昇降時に、ウェハキャリア
2の各スロット7内の半導体ウェハ6の有無を検出する
ことができる。
Further, along the hoisting path of the carrier hoisting table 8, a wafer position detection mechanism 9 such as a photo sensor is disposed facing each other so as to horizontally or diagonally cross the hoisting path of the carrier hoisting table 8. With this wafer position detection mechanism 9, the presence or absence of a semiconductor wafer 6 in each slot 7 of the wafer carrier 2 can be detected when the wafer carrier is moved up and down.

このウェハ位置検出機構9により検出されたウェハ位置
情報は、装置制御部10のウェハ収容情報記憶機構11
に記憶され、この記憶されたウェハ収容情報に基づいて
搬送系制御機構12が搬送機構の搬送アーム5aの動作
を制御する。
The wafer position information detected by the wafer position detection mechanism 9 is stored in the wafer accommodation information storage mechanism 11 of the apparatus control section 10.
Based on the stored wafer accommodation information, the transport system control mechanism 12 controls the operation of the transport arm 5a of the transport mechanism.

このようなCVD装置では、ロードロック室3内のキャ
リア昇降台8にウェハキャリア2を搭載した後、キャリ
ア昇降台8を上昇させなからウェハ位置検出機構9によ
りウェハキャリア2の各スロット7毎の半導体ウェハ6
の有無を検出し、該ウェハ収容情報を記憶機構11に記
憶しておく。
In such a CVD apparatus, after the wafer carrier 2 is mounted on the carrier lifting table 8 in the load lock chamber 3, the wafer position detection mechanism 9 detects each slot 7 of the wafer carrier 2 without raising the carrier lifting table 8. semiconductor wafer 6
The presence or absence of the wafer is detected and the wafer accommodation information is stored in the storage mechanism 11.

こうしてウェハキャリア2の全スロットにおけるウェハ
収容情報を記憶した後、所定の半導体ウェハ6と搬送ア
ーム5aとが同レベルの高さとなるようにウェハキャリ
ア8を昇降させて半導体ウェハ6の取出し作業を行う。
After storing the wafer accommodation information in all the slots of the wafer carrier 2 in this way, the wafer carrier 8 is raised and lowered so that a predetermined semiconductor wafer 6 and the transfer arm 5a are at the same height, and the semiconductor wafer 6 is taken out. .

このとき、ウェハキャリアの各スロットにおける半導体
ウェハの有無が、予め記憶機構に記憶されているので、
空スロットをとばして半導体ウェハを取出すことができ
、従来のようにウェハキャリアの全スロットに対して半
導体ウェハの取出し動作を行う必要はなく、取出し作業
の短縮化が図れる。さらに、処理の終了した半導体ウェ
ハを元のスロット内に収容する際にも、上記ウェハ収容
情報に基づいて予めウェハキャリアの昇降動作を行って
おけるので、ウェハ収容作業を迅速に行うことができる
At this time, since the presence or absence of a semiconductor wafer in each slot of the wafer carrier is stored in advance in the storage mechanism,
Semiconductor wafers can be taken out by skipping empty slots, and there is no need to take out semiconductor wafers from all slots of the wafer carrier as in the conventional case, thereby shortening the taking-out operation. Further, even when storing a semiconductor wafer that has been processed into the original slot, the wafer carrier can be moved up and down in advance based on the wafer storage information, so that the wafer storage work can be carried out quickly.

ところで上述した実施例では、ウェハ位置検出機構9を
固定とし、ウェハキャリア2を昇降させることで、半導
体ウェハの有無を確認したが、ウェハ位置検出機構を昇
降させるように構成してもよく、半導体ウェハとウェハ
検出機構とを相対的に移動させる手段であれば、いずれ
の構成でもよい。
By the way, in the above embodiment, the wafer position detection mechanism 9 is fixed and the wafer carrier 2 is raised and lowered to check the presence or absence of a semiconductor wafer. However, the wafer position detection mechanism 9 may be configured to be raised and lowered, Any structure may be used as long as it is a means for relatively moving the wafer and the wafer detection mechanism.

また、本発明はCVD装置以外の半導体製造装置にも適
用でき、例えばイオン注入装置、スパッタリング装置等
のロードロック室を有する半導体製造装置であればいず
れにも適用可能である。
Further, the present invention can be applied to semiconductor manufacturing equipment other than CVD equipment, and can be applied to any semiconductor manufacturing equipment having a load lock chamber, such as an ion implantation equipment or a sputtering equipment.

[発明の効果] 以上説明したように本発明の半導体ウニ11の製造装置
によれば、ロードロック室内のウニ/1キヤリアに収容
された半導体ウニノ1の取出し、収容作業を要領よく、
迅速に行うことが可能となり、装置全体の作業能率の向
上が図れる。
[Effects of the Invention] As explained above, according to the semiconductor sea urchin 11 manufacturing apparatus of the present invention, the semiconductor sea urchin 1 accommodated in the sea urchin/1 carrier in the load lock chamber can be smoothly taken out and accommodated.
This can be done quickly, and the work efficiency of the entire device can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明をマルチチャンバ型CVD装置に適用し
た実施例の装置構成を示す図、第2図(a)は第1図の
ロードロック室の構成を示す平面図であり、第2図(b
)その正面図である。 2・・・・・・ウェハキャリア、3・・・・・・ロード
ロック室、4・・・・・・チャンバ、5・・・・・・ウ
ニ11搬送アーム、6・・・・・・半導体ウェハ、8・
・・・・・キャリア昇降機構、9・・・・・・ウェハ検
出機構、10・・・・・・装置制御部、11・・・・・
・記憶機構、12・・・・・・搬送系制御機構。 出願人      チル・パリアン株式会社代理人 弁
理士  須 山 佐 − (a)
FIG. 1 is a diagram showing the device configuration of an embodiment in which the present invention is applied to a multi-chamber type CVD device, FIG. 2(a) is a plan view showing the configuration of the load lock chamber in FIG. 1, and FIG. (b
) is its front view. 2...Wafer carrier, 3...Load lock chamber, 4...Chamber, 5...Uni 11 transfer arm, 6...Semiconductor Wafer, 8.
...Carrier lifting mechanism, 9...Wafer detection mechanism, 10...Device control unit, 11...
- Storage mechanism, 12...transport system control mechanism. Applicant Chiru Parian Co., Ltd. Agent Patent Attorney Sasa Suyama - (a)

Claims (1)

【特許請求の範囲】  半導体ウェハを多数収容したウェハキャリアをロード
ロック室内に収容し、前記ウェハキャリアから所定の半
導体ウェハを搬送機構により処理室内に搬送して処理す
る半導体ウェハの製造装置において、 前記ウェハキャリア内の半導体ウェハの収容位置を予め
検出するウェハ検出機構と、前記ウェハ検出機構のウェ
ハ位置情報を記憶する記憶機構と前記記憶機構に基づい
て前記搬送機構の動作を制御する搬送制御機構とを備え
たことを特徴とする半導体ウェハの製造装置。
[Scope of Claims] A semiconductor wafer manufacturing apparatus in which a wafer carrier containing a large number of semiconductor wafers is accommodated in a load lock chamber, and a predetermined semiconductor wafer is transferred from the wafer carrier into a processing chamber by a transfer mechanism for processing, comprising: a wafer detection mechanism that detects in advance the accommodation position of a semiconductor wafer in a wafer carrier; a storage mechanism that stores wafer position information of the wafer detection mechanism; and a transfer control mechanism that controls the operation of the transfer mechanism based on the storage mechanism. A semiconductor wafer manufacturing device characterized by comprising:
JP63072722A 1988-03-25 1988-03-25 Production device for semiconductor wafer Pending JPH01244634A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63072722A JPH01244634A (en) 1988-03-25 1988-03-25 Production device for semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63072722A JPH01244634A (en) 1988-03-25 1988-03-25 Production device for semiconductor wafer

Publications (1)

Publication Number Publication Date
JPH01244634A true JPH01244634A (en) 1989-09-29

Family

ID=13497532

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63072722A Pending JPH01244634A (en) 1988-03-25 1988-03-25 Production device for semiconductor wafer

Country Status (1)

Country Link
JP (1) JPH01244634A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5803696A (en) * 1997-05-16 1998-09-08 Taiwan Semiconductor Manufacturing Company, Ltd. Safety interlock device for a standard manufacturing interface arm and equipment
JP2020140979A (en) * 2019-02-26 2020-09-03 東京エレクトロン株式会社 Load lock module, board processing device, and board transfer method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59175740A (en) * 1983-03-25 1984-10-04 Telmec Co Ltd Extractor for wafer in measuring device for semiconductor
JPS61267623A (en) * 1985-05-20 1986-11-27 Canon Inc Wafer transport apparatus
JPS61273441A (en) * 1985-05-23 1986-12-03 Canon Inc Wafer transfer device
JPS62290610A (en) * 1986-06-06 1987-12-17 Daifuku Co Ltd Travel driver for warehouse crane
JPS6332931A (en) * 1986-04-18 1988-02-12 ジエネラル・シグナル・コ−ポレ−シヨン Plasma etching system

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59175740A (en) * 1983-03-25 1984-10-04 Telmec Co Ltd Extractor for wafer in measuring device for semiconductor
JPS61267623A (en) * 1985-05-20 1986-11-27 Canon Inc Wafer transport apparatus
JPS61273441A (en) * 1985-05-23 1986-12-03 Canon Inc Wafer transfer device
JPS6332931A (en) * 1986-04-18 1988-02-12 ジエネラル・シグナル・コ−ポレ−シヨン Plasma etching system
JPS62290610A (en) * 1986-06-06 1987-12-17 Daifuku Co Ltd Travel driver for warehouse crane

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5803696A (en) * 1997-05-16 1998-09-08 Taiwan Semiconductor Manufacturing Company, Ltd. Safety interlock device for a standard manufacturing interface arm and equipment
JP2020140979A (en) * 2019-02-26 2020-09-03 東京エレクトロン株式会社 Load lock module, board processing device, and board transfer method

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